Embedded Media Applications Research Articles

A Reconfigurable Heterogeneous Multimedia Processor for IC-Stacking on Si-Interposer

This paper presents a heterogeneous multimedia processor for embedded media applications such as image processing, vision, 3-D graphics and augmented reality (AR), assuming integrated circuit (IC)-stacking on Si-interposer. This processor embeds reconfigurable output drivers for external memory interface to increase memory bandwidth even in a mobile environment. The implemented output driver reconfigures its driving strength according to channel loss between the implemented processor and the memory, so it enables highspeed data communication while achieving 8× higher memory bandwidth compared to previous embedded media processors. The implemented processor includes three main programmable intellectual properties, mode-configurable vector processing units (MCVPUs), a unified filtering unit (UFU), and a unified shader. MCVPUs have 32 integer (16 bit) cores in order to support dual-mode operations between image-level processing and graphics processing. This mode-configuration enables a frame-level pipelining in AR application, so the proposed processor achieves 1.7× higher frame rate compared to the sequential AR processing. UFU supports 16 types of filtering operations only with a single instruction. Most image-level processing consists of various types of filtering operations, so UFU can improve media processing performance and energy-efficiency. UFU also supports texture filtering which is performance bottleneck of common graphics pipeline. A memory-access-efficient (off-chip memory) texturing algorithm named as an adaptive block selection is proposed to enhance texturing performance in 3-D graphics pipeline. UFU has two-level on-chip memory hierarchies, a 512B level-0 (L0) data buffer, and an 8kB level-1 (L1) static random-access memory (SRAM) cache. The small-sized L0 data buffer limits direct references to the large-sized L1 SRAM cache to reduce energy consumed in on-chip memories. Unified shader consists of four homogeneous scalar processing elements (SPEs) for geometry operations in 3-D graphics. Each SPE has single-precision floating-point data-paths, since precision of geometry operations in 3-D graphics is important in today's handheld devices (high resolution). The proposed media processor is fabricated in 0.13 μm CMOS technology with 4 mm × 4 mm chip size, and dissipates 275 mW for full AR operation.

Application-specific clustered VLIW datapaths: early exploration on a parameterized design space

Specialized clustered very large instruction word (VLIW) processors combined with effective compilation techniques enable aggressive exploitation of the high instruction-level parallelism inherent in many embedded media applications, while unlocking a variety of possible performance/cost tradeoffs. In this work, the authors propose a methodology to support early design space exploration of clustered VLIW datapaths, in the context of a specific target application. They argue that, due to the large size and complexity of the design space, the early design space exploration phase should consider only design space parameters that have a first-order impact on two key physical figures of merit: clock rate and power dissipation. These parameters were found to be: maximum cluster capacity, number of clusters, and bus (interconnect) capacity. Experimental validation of their design space exploration algorithm shows that a thorough exploration of the complex design space can be performed very efficiently in this abstract parameterized design space.