Electrostatic Control Of Channel Research Articles

A new I–V model for surrounding-gate MOSFET considering gate-voltage-dependent quantum effect

We present a new I–V model for a long-channel surrounding-gate (SG) metal–oxide–semiconductor field-effect transistor (MOSFET). SG MOSFET is a strong candidate for next generation nanoscale devices due to a high electrostatic channel control, which in turn substantially reduces the short-channel effect. The new model takes into account quantum mechanical (QM) effects in the SG MOSFET using a double triangular QM well model in the strong inversion regime. In contrast with the old model, we consider the V g dependence of the QM effect. New model yields excellent agreement with 2-D numerical simulation results for various radii and gate oxide thicknesses of the SG MOSFET.

Pushing CMOS beyond the roadmap

Today, the 90 nm generation is in production and in spite of many roadblocks, the latest ITRS 04 expects that CMOS can be scaled down to the 22 nm node and beyond. However, for conventional bulk CMOS serious challenges are evident and new transistors with better electrostatic channel control, lower off-currents and higher on-currents will be needed. Among them, multi-gate devices with very thin silicon channels are most promising. Several architectures like FinFET, Wafer Bonded Double Gate and SON Gate All Around have been demonstrated with good electrical characteristics at gate lengths of 25–10 nm. Under certain assumptions for the SD regions, quantum mechanical simulations predict that silicon MOSFETs can be functional down to 2 nm gate length. Multi-gate transistors have also been implemented in high density Flash memory cells down to 20 nm. Large V t shifts suitable for multi-level storage were achieved. Therefore, it seems very realistic that the device roadmap will not end at the 22 nm node. Assuming that manufacturing and cost issues can be fulfilled, CMOS will continue to dominate in the nanoelectronics era.