Electronics Packaging Technology Conference Research Articles

(Invited) Hybrid Bonding for 3D Applications: Improvements and Limitations

Wafer direct bonding has attracted considerable concerns since it takes advantage of the ability to achieve strong adherence between flat, clean, and smooth surface without the use of intermediate materials. This technology experienced a consequent rise with the More than Moore's law. With this trend, added value to devices is provided by incorporating functionalities that do not necessarily scale according to "Moore's Law”. Indeed, this aims to realize three-dimensional (3D) integration systems by stacking devices and interconnecting them using Through-Silicon-Via (TSV) or Cu-Cu interconnections. Hybrid bonding is preferred to other chip stacking technologies because Cu-Cu hybrid bonding is easily capable of scaling down and present excellent reliability results.Hybrid bonding is key technology to address several applications especially images sensor. Even more specialized applications or better performances could be obtained through hybrid bonding pitch reduction [1]. High quality bonding for 3D technology has been demonstrated using an accurate wafer bonding tool with optimized metrology [2]. The total overlay values reached is below 110 nm with residuals values below 80 nm and scaling inferior to 0.5 ppm for interconnect pitches from 6.9 µm down to 0.6 µm. The electrical properties have been checked and confirmed the robustness of the fine pitch hybrid bonding module and the stability of the bonding interface [3]. The latest process and hardware developments have made it possible to greatly reduce scaling. However, distortion remains the most complicated parameter to optimize. It is strongly linked to the design of the chip (number of metal levels, stress...). Today, a minimum critical dimension design rule should be respected to avoid short between front side and backside layers and this is preventing pixel shrink. To reduce pixel size, distortion value needs to be decreased. For that purpose, in situ monitoring of the bonding wave is necessary as well as bonding chucks multiple vacuum zones in order to achieve homogenous bonding wave propagation.Even if hybrid bonding integration and performance have been considerably improved, we can notice that thermal budget is a main limitation for this technology. Indeed, to reach strong bonding energy which is mandatory for subsequent mechanical manufacturing; a bonding anneal of 800°C is required. By using plasma treatment prior bonding, anneal temperature can be decreased to 400°C. However, some devices cannot withstand such thermal budget because of thermosensitive materials integration (GST or quantum dots for example). To overcome this limitation, many studies have been performed on developing low temperature direct bonding process. Surface activated bonding (SAB) is a promising method to achieve high bonding energy at room temperature, but chemical surface treatments (as amino-alcohol organic molecule for example [4]) are easiest to implement for mass volume production and allows highly strong bonding at 200°C that can stand high stress process steps (grinding, CMP and dicing).Although specific plasma or surface preparation could decrease the required annealing temperature, the copper oxide will limit electrical performances with annealing below 250°C for standard hydrophilic bonding. That is why, new ECD Cu deposition like oriented nano-twin Cu is very promising to facilitate oxygen diffusion. [5][1] AYOUB, B., LHOSTIS, S., MOREAU, S., et al. Impact of Process Variations on the Capacitance and Electrical Resistance down to 1.44 µm Hybrid Bonding Interconnects. In : 2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC). IEEE, 2020. p. 453-458.[2] DETTONI.Florent, DELOFFRE, Emilie, GRAUER, Yoav, et al. Advanced overlay metrology for CIS bonding applications. ECTC 2023 to be published[3] AYOUB, Bassel, LHOSTIS, Sandrine, MOREAU, Stéphane, et al. Sub 1µm Pitch Achievement for Cu/SiO 2 Hybrid Bonding. In : 2022 IEEE 24th Electronics Packaging Technology Conference (EPTC). IEEE, 2022. p. 418-424.[4] FOURNEL, Frank, CALVEZ, Aziliz, LARREY, Vincent, et al. Impact of an Amino-Alcohol Organic Molecule on SiO2 and Si Bonding Energy. ECS Transactions, 2020, vol. 98, no 4, p. 3.[5] CHEN, Chih, JUANG, Jing-Ye, CHANG, Shih Yang, et al. Low-temperature Cu-to-Cu direct bonding enabled by highly (111)-oriented and nanotwinned Cu. In : 2019 6th International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D). IEEE, 2019. p. 38-38.

Comparative Reliability of Inkjet-Printed Electronics Packaging

This article compares the thermomechanical behavior of 3-D inkjet-printed microelectronics devices relative to those fabricated from traditional methods. It discusses the benefits and challenges in the adoption of additive manufacturing methods for microelectronics manufacture relative to conventional approaches. The critical issues related to the design and reliability of additively manufactured parts and systems stem from the change in the manufacturing process and the change in materials utilized. This study uses numerical modeling techniques to gain insight into these issues. This article is an extension of the same topic presented at the 2018 IEEE Electronics Packaging Technology Conference. An introduction providing an overview of the area, covering salient academic research activities and discussing progress toward commercialization is presented. The state-of-the-art modular microelectronics fabrication system developed within the EU NextFactory project is introduced. This system has been used to manufacture several test samples, which were assessed both experimentally and numerically. A full series of JEDEC tests showed that the samples were reliable, successfully passing all tests. The numerical model assessing the mechanical behavior of an inkjet-printed structure during layer-by-layer fabrication is presented. This analysis predicts that the stresses induced by the UV cure process are concentrated toward the extremities of the part and, in particular, in the lower layers which are constrained by the print platform. Subsequently, a model of a multilayer microelectronics structure undergoing JEDEC thermal cycling is presented. The model assesses the differences in mechanical properties between a conventional FR4/copper structure and an inkjet-printed acrylic/silver structure. The model identified that the influence of the sintering process on subsequent material properties, behavior of the inject-printed structure, and reliability of the inject-printed structure is significant. Key findings are that while stresses in the conventional and inkjet boards are relatively similar, the inkjet-printed board exhibits significantly greater deformation than the standard board. Furthermore, the mechanical stresses in the inkjet fabricated board are strongly dependent on the elastic modulus of the sintered silver material, which, in turn, is dependent on the sintering process.

Mechanical Testing for Stretchable Electronics

Stretchable electronics have been a subject of increased research over the past decade (Lacour, S., et al., 2006, “Mechanisms of Reversible Stretchability of Thin Metal Films on Elastomeric Substrates,” Appl. Phys. Lett., 88(20), p. 204103; Lacour, S., et al., 2004, “Design and Performance of Thin Metal Film Interconnects for Skin-Like Electronic Circuits,” IEEE Electron Device Lett., 25(4), pp. 179–181; and Maghribi, M., et al., 2005, “Stretchable Micro-Electrode Array,” International IEEE-EMBS Conference on Microtechnologies in Medicine and Biology, pp. 80–83.). Although stretchable electronic devices are a relatively new area for the semiconductor/electronics industries, recent market research indicates that the market could be worth more than $900 million by 2023 (PR Newswire, 2015, “Stretchable Electronics Market Worth $911.37 Million by 2023,” PR Newswire, Albuquerque, NM.). This paper investigates mechanical testing methods designed to test the stretching capabilities of potential products across the electronics industry to help quantify and understand the mechanical integrity, response, and the reliability of these devices. Typically, the devices consist of stiff modules connected by stretchable traces (Loher, T., et al., 2006, “Stretchable Electronic Systems,” Electronics Packaging Technology Conference (EPTC '06), pp. 271–276.). They require electrical and mechanical connectivity between the modules to function. In some cases, these devices will be subject to biaxial and/or cyclic mechanical strain, especially for wearable applications. The ability to replicate these mechanical strains and understand their effect on the function of the devices is critical to meet performance, process, and reliability requirements. In this paper, methods for simulating biaxial and out-of-plane strains similar to what may occur in a wearable device on the human body are proposed. Electrical and/or optical monitoring (among other methods) can be used to determine cycles to failure depending on expected failure modes. Failure modes can include trace damage in stretchable regions, trace damage in functional component regions, or bulk stretchable material damage, among others. Three different methods of applying mechanical strain are described, including a stretchable air bladder method, membrane test method, and lateral expansion method.

EPTC 2008 – Electronics Packaging Technology Conference, 9-12 December, Grand Copthorne Waterfront Hotel, Singapore

EPTC 2008 – Electronics Packaging Technology Conference, 9-12 December, Grand Copthorne Waterfront Hotel, Singapore

EPTC 2008, Electronics Packaging Technology Conference, 9-12 December, Grand Copthorne, Waterfront Hotel, Singapore

EPTC 2008, Electronics Packaging Technology Conference, 9-12 December, Grand Copthorne, Waterfront Hotel, Singapore

8th Electronics Packaging Technology Conference (EPTC 2006)

8th Electronics Packaging Technology Conference (EPTC 2006)

8th Electronics Packaging Technology Conference (EPTC 2006)

8th Electronics Packaging Technology Conference (EPTC 2006)

7th Electronics Packaging Technology Conference (EPTC 2005)

7th Electronics Packaging Technology Conference (EPTC 2005)

7th Electronics Packaging Technology Conference (EPTC 2005)

7th Electronics Packaging Technology Conference (EPTC 2005)

7th Electronics Packaging Technology Conference (EPTC 2005)

7th Electronics Packaging Technology Conference (EPTC 2005)

7th Electronics Packaging Technology Conference (EPTC 2005)

7th Electronics Packaging Technology Conference (EPTC 2005)

7th Electronics Packaging Technology Conference (EPTC 2005)

7th Electronics Packaging Technology Conference (EPTC 2005)

7th Electronics Packaging Technology Conference (EPTC 2005)

7th Electronics Packaging Technology Conference (EPTC 2005)