Electronic ICs Research Articles

ESD Protection for Power Electronic ICs and Discrete Devices

ESD Protection for Power Electronic ICs and Discrete Devices

A Novel Approach to Investigate Analog and Digital Circuit Applications of Silicon Junctionless-Double-Gate (JL-DG) MOSFETs

The double gate junctionless transistor (DG-JLT) has become the most promising device in sub nano-meter regime. DGJLT based circuits have improved performance and simpler fabrication than their inversion mode counterparts. This paper demonstrates the design of different analog and digital circuits using DGJLT. Amplifiers and inverters are the basic building block of electronic ICs. A MOS amplifier converts the variation of the gate to source voltage to a small current under transconductance and hence, the output voltage. A single-stage amplifier and differential amplifier have been designed with junctionless-double-gate (JL-DG) MOSFET. Trans-conductance, output voltage, and gain have been investigated using ATLAS 2D device simulator. The inverter is the primary logic gate that can be used to verify the device’s response in digital applications. Further, CMOS inverter have been designed using JL-DG MOSFET, and its performance parameters such as switching voltage, noise margin, and logic delay have been analyzed. A switching voltage of 0.43 V, noise margin of 0.265 V, and a delay of 19.18 psec have been obtained for the basic cell. CMOS inverter using JL-DG MOSFET at 20 nm channel length have prompted better performance results. Thus, The JL-DG MOSFET has a bright future in low-power analog and digital applications.

Chip Scale 12-Channel 10 Gb/s Optical Transmitter and Receiver Subassemblies Based on Wet Etched Silicon Interposer

In this paper, compact optical subassemblies are demonstrated based on a novel silicon interposer, which is designed and fabricated in a wafer scale process. The interposer includes the design of optical and electrical connections. A low-cost fabrication method, wet etching, is used to define light inputs and outputs as well as create the required recesses in the interposer to embed the chips into the silicon wafer at the same time. Impedance matched traces, for the high speed signals of the CMOS and opto–electronic ICs, are designed using advanced design system software and transferred onto the interposer by photolithography and electro-plating, which are accomplished on the deeply etched topology. The whole process flow of the silicon interposer patterning is designed and demonstrated, and the challenges are discussed. After the process, the optoelectronic dies and their complimentary CMOS parts are flipped and bonded on the interposer in close proximity, and a mechanical optical interface (MOI) is mounted for light coupling. Both transmitter and receiver subassemblies provide 12 parallel optical interconnections, and are scaled down to an area measuring 6 by 8 mm. Signal integrity testing is performed on a probe station for 10 Gb/s data signal delivering clear eye patterns for all channels (in both Rx and Tx subassemblies). The performance is further characterized using bit error rate (BER) testing. Both transmitter and receiver assemblies outperform a reference SFP+, with receiver sensitivity of −10 dBm at a BER lower than 10−12 after compensating for the MOI insertion loss. Finally, we also test the assemblies for crosstalk and demonstrate that the current design has a maximal additional penalty lower than 0.2 and 0.8 dB for transmitter and receiver, respectively.

On-Board Silicon Photonics-Based Transceivers With 1-Tb/s Capacity

Providing host Application-specific integrated circuit (ASIC) (e.g., microprocessors, switches, or field-programmable gate array (FPGAs)) with terabit per second optical transmission capabilities has emerged as a new requirement in exascale cloud data centers and high-performance computing. The combination of silicon photonics (Si-Phot) and 3-D interconnecting technologies stands as a unique solution for fulfilling this need while addressing the key factors of success that are more Gb/s/cm2, less pJ/bit, and less $/Gb/s. This paper is intended to present and evaluate several Si-Phot-based solutions for providing the host ASIC with 1-Tb/s optical transceivers. Two packaging architectures are proposed, making use of 3-D interconnecting building blocks, and motivated by the need for implementing a few hundreds of high-speed electrical interconnections. Models are given for each of the 3-D building blocks, and simulation of the overall electrical signal integrity is made for the two proposed transceiver architectures. In addition, using the capability of CMOS fabrication lines for producing low-cost transceiver chips (Si-Phot integrated circuits with their electronic ICs) and 3-D chip assemblies, it is also necessary to develop high-throughput/low-cost techniques for coupling the light from the chip to the fiber. One such technique will be presented.

Polarization-Independent Coherent Real-Time Analog Receiver for PON Access Systems

A 1.25-Gb/s ASK passive optical network (PON) system with a −51 dBm pre-FEC sensitivity (at BER = 2 × 10−3) is enabled by a real-time polarization-independent coherent receiver (PI-RX) that needs no DSP (nor ADC). The receiver, which only makes use of common DFBs and commercially available electronic ICs, is targeted for use on a 6.25-GHz UD-WDM grid and has a 52-dB dynamic range. Measurements of the robustness of the PI-RX against backreflections and crosstalk from coexistent adjacent channels show that this preliminary implementation is suitable for UD-WDM-PON systems with frequency spacing down to 5 GHz.

Silicon Photonics R&D and Manufacturing on 300-mm Wafer Platform

Industrial implementation of a silicon photonics platform using 300-mm SOI wafers and aiming at 100 Gb/s aggregate data-rate application is demonstrated. The integration strategy of electronic and photonic ICs, 300-mm process flow, and process variability are discussed, and performances of the passive and active optical devices are shown. An example of a low-cost LGA-based package together with a fiber assembly is given. RX and TX circuits operating at 25 Gb/s are demonstrated. Finally, the process evolution toward the integration of the backside reflector and multiple silicon etching level is demonstrated.

(Keynote) Silicon Photonics Technology for Optical Communications with High Bandwidth Density Requirements (1Tbit/s and 1,000 Gbit/s/cm²)

As many applications emerge with the need for providing System-In-Package with optical I/Os, Silicon photonics technology shows great assets over other optical technologies: - The integrations of all the optical functions required to establish an optical transmission link have been demonstrated (silicon based modulators and (de)multiplexers, integration of Ge/Si photodetectors and heterogeneous integration of III-V/Si lasers). The fabrication is achieved in CMOS fabs on 200 and 300mm-wafers. - Besides the Si-Photonics technology enables the use of 3D assembling techniques for interconnecting the Silicon-Photonic Integrated Circuit (PIC) with its required driving Electronics (Electronic IC). Micro pillars can be used with ultra-low parasitics between the PIC and its companion EIC. The talk will review how the Silicon photonics technology toolbox developed at CEA-Leti (including the photonic devices library and the 3D assembling techniques for interconnecting PICs and EICs) scales with transmission applications having denser integration requirements (Tbit/s-class transceiver with bandwidth density > 1,000 Gbit/cm²). The performances of several demonstrators will be presented (25Gb/s receiver and 16-QAM transmitter) made from hybridation of Si-PICs and CMOS Electronic ICs).

Inhaled corticosteroids used for the control of asthma in a “real-life” setting do not affect linear growth velocity in prepubertal children

SummaryBackgroundRecent guidelines recommend inhaled corticosteroids as the first-line treatment for persistent asthma. However, long-term corticosteroid treatment in children has raised concerns about potential growth rate deceleration. We aimed to assess the association of growth velocity with the use of inhaled corticosteroids in prepubertal children with asthma in a “real-life” setting.Material/MethodsThis study included 844 children aged 4–9.5 years coming to the hospital for regular check-ups between October 2006 and February 2009 for asthma with/without allergic rhinitis and no other known constraints of growth. Out of the 844 children, 790 had all data needed for analysis – 245 children were not treated with ICS, 545 children received ICS (fluticasone, budesonide) with/without INCS (fluticasone, mometasone or budesonide). During the study period, 48 children with/without ICS received short SCS courses.ResultsMean (SE) height at the first check-up was 123.1 (0.31) cm; range (100.0–147.8 cm). Mean (SE) linear growth velocity (LGV) of the included children was 0.185 (0.0035) mm/day between 2 check-ups. No significant difference was found in LGV between the group not treated with ICS (0.180 mm/day±0.0055) and the group treated with ICS (0.187±0.0044 mm/day). Also, there was no statistical difference between subgroups according to additional therapy with INCS and SCS. No significant correlation was found for LGV and daily dose of ICS (r=0.086, p>0.05).ConclusionsIn our retrospective study using electronic hospital database, ICS and combined use of corticosteroids did not show any association with LGV in prepubertal asthmatic children in a “real-life” setting.

Electrostatic Discharge Current Linear Approach and Circuit Design Method

The Electrostatic Discharge phenomenon is a great threat to all electronic devices and ICs. An electric charge passing rapidly from a charged body to another can seriously harm the last one. However, there is a lack in a linear mathematical approach which will make it possible to design a circuit capable of producing such a sophisticated current waveform. The commonly accepted Electrostatic Discharge current waveform is the one set by the IEC 61000-4-2. However, the over-simplified circuit included in the same standard is incapable of producing such a waveform. Treating the Electrostatic Discharge current waveform of the IEC 61000-4-2 as reference, an approximation method, based on Prony’s method, is developed and applied in order to obtain a linear system’s response. Considering a known input, a method to design a circuit, able to generate this ESD current waveform in presented. The circuit synthesis assumes ideal active elements. A simulation is carried out using the PSpice software.

Photonic integration: Si or InP substrates?

A brief review of recent progress in photonic integrated circuits (PICs) is presented. By examining Moore's Law and the roadmap of conventional electronic ICs, valuable lessons in host material selection for PICs are discussed. Finding a primary host material for integration is necessary and vital to the success of the PIC industry. Initial success has been achieved in both InP-based and silicon-based commercial PICs; however, we believe that cost and performance may select silicon as the primary host material, with the urgency to deploy optical interconnects on Si electronic ICs as one of the main reasons. A recently introduced hybrid silicon evanescent platform and devices and silicon/germanium APDs are reviewed as examples to understand the viability of silicon PICs and lead to an understanding of a possible roadmap to next generation large-scale PICs.

Toward High-Speed 40-Gbit/s Transponders

Today a 40-Gbit/s data rate is agreed by major optical telecommunication players as the next step in the network evolution, with an actual deployment foreseen in the 2007-2008 timeframe. R&D activities on technologies for 40-Gbit/s products are currently active but the path to 40-Gbit/s transponders is not yet fully settled. In this paper, we review the different component technologies currently considered for the actual development and the implementation of future 40-Gbit/s transponders. Dedicated paragraphs are devoted to electronic ICs and electrooptical devices, along with considerations on the technical solutions ensuring suitable interconnections or integration of the different components. Such advanced transponders should be compliant with the requirements of the different segments of the optical transport market. Solutions derived from choices made at lower data rates are projected for the shortest transmission paths, based on conventional nonreturn to zero modulation. In the peculiar case of long-haul transmission, signal distortion resulting from fiber propagation impairments calls for the generation of alternative modulation formats at the transmitter side and the potential need for electronic processing at the receiver side. This obviously has a clear impact on both the transponder design and the individual components features. Finally, recent advances in the field of innovative "all-optical" transponders implementing optical regeneration are also reported

120-Gb/s multiplexing and 110-Gb/s demultiplexing ICs

InP HBT ICs capable of 120-Gb/s multiplexing and 110-Gb/s demultiplexing operation have been developed. They feature a direct-drive series-gating configuration selector, an asymmetrical latch flip-flop, and broadband impedance matching with inverted microstrip lines. Their input sensitivity is less than 100 mV/sub pp/, and the output swing is more than 400 mV/sub pp/. To the best of our knowledge, this result is the highest data rate operation reported for electronic ICs. Moreover, an error-free multiplexing and demultiplexing operation at 100 Gb/s was demonstrated.

Design and Development of Optoelectronic Mixed Signal System-on-Package (SOP)

This paper describes the design and development of a 2.5-Gb/s optical transceiver module as a mixed signal SOP for access networks. The module development consists of concurrent design of an optoelectronic package optimizing optical, electrical, thermal, mechanical functions and optical subassembly and RFICs housed in a chip-on-board package. The optical subassembly (OSA) consists of laser and photodiode assembled on a silicon substrate. The transmit and the receiver sections are combined into a single fiber through a polymer coupler on silicon. The splitter between the transmit and receive section is realized using a polymer waveguide. The electronic ICs are assembled on a multilayer organic substrate. The package design includes optical coupling design, impedance matched transmission line design for RF signals, electrical layout design for mixed signals and thermal design for the package. The module is housed in a plastic molded nonhermetic package to achieve low cost packaging. The assembly is completed using passive alignment of optical devices and attachment of electronic devices using adhesives. In this paper, we present the details of the component design and the development of packaging process methods to achieve the design specifications, test results and process guidelines for assembly and integration.

Heterogeneous integration of OE arrays with Si electronics and microoptics

This paper describes recent developments of the smart pixel array (SPA) technology for massively parallel optical interconnect applications. Built on Honeywell's commercially successful 850 nm vertical cavity surface emitting laser (VCSEL) technology, the SPA employs a 2D array of VCSELs and photodetectors (PDs). It aims to push optical interconnect density and capacity to a new level, which brings chip-level input and output (I/O) capacity to the order of 100s to 1000s of gigabit per second (Gbps). This technology has several unique features that make it not only technically feasible but also practical for low cost manufacturing. First, it employs an optoelectronic (OE) array based on the new generation of oxide-confined VCSELs that have desired characteristics such as very high speed, high efficiency, and good array uniformity. Second, the OE array has monolithically integrated VCSELs and PDs that provides true bi-directional optical I/O solutions at the chip-scale. Third, it uses hybrid integration techniques such as solder bump bonding and wafer scale integration. The 2D arrays of VCSELs and PDs can be seamlessly integrated with a beam shaping micro-optics array, and with the state-of-the-art Si-based VLSI electronic ICs. Last, and perhaps most importantly, all of the technology implementations follow the guideline of being compatible with mainstream low cost manufacturing practices. Device performance characteristics, integration approach, and prototype demonstration SPA technology up to over 1000 I/O channels per chip are presented, including some early system prototype demonstrations. We believe the SPA technology provides future application specific integrated circuits (ASICs) with new form packaging solutions-a solution that give an ASIC with unprecedented large capacity of very high density and high speed I/Os. It can be used as a new building block to implement varieties of system architectures that are not possible to build with current electrical interconnection.

Plastic electronics and future trends in microelectronics

The celebrated information technology (IT), has been a phenomenal success. But, it is a narrow one. It has marched along a one-dimensional path of information processing and transmission, but extended little to the left — acquiring information, or to the right — executing on information. It is in the tremendous space and potential to the left and right of the evolution path that plastic electronics is envisioned as an enabling technology. Complementing the ever more powerful microelectronics, it has the potential to be a disruptive technology to microelectronics. While this has always been a distant possibility in the past, the time for a major breakthrough is now within sight. This has much to do with the state of microelectronics and with the recent profound progress in developing organic electronic materials. Microelectronics, as the engine driving today’s IT advances, has come to a crossroads. On the road to nanoelectronics, one sees exponentially increasing cost and diminishing return with billion dollar IC fab cost doubling every generation. The high cost is, on the one hand, squeezing out all but the largest players and on the other, slowing down innovation from within. Troubles at the physical foundation of today’s microelectronics are of as much concern, if not more so. The wiring challenge and the power dissipation crisis are only going to get worse with each further step of miniaturization. These problems are deeply rooted in the much-hyped digitalization, i.e. the paradigm of binary and serial signal processing. In this state of microelectronics, the opportunities for alternative technologies are emerging, and will be best pursued if not by our own initiatives then maybe by the movement of investors’ dollars to areas of greater return. At the crossroads, microelectronics can go down to nanoelectronics. But, it can also move up to macroelectronics, and can extend to the left and to the right, where plastic electronics enters as an enabling base technology. In contrast to silicon microelectronics, plastic electronics can be large-area (macrosize IC, display, memory films), large critical feature size (macro linewidth), and compatible with a continuous rotary fabrication (printing) process rather than the batch (lithographic) fabrication. The performance of individual plastic electronic devices or ICs is unlikely to match the silicon counterparts — now or ever — one might say. But disruptive technologies do not have to satisfy the same performance criteria as existing ones because they address new products and new markets, as the Harvard Business School teaching goes.

High-speed optoelectronic hybrid-integrated transmitter module using a planar lightwave circuit (PLC) platform

High-speed optoelectronic hybrid-integrated transmitter module has been developed using a silica-based planar lightwave circuit (PLC) platform on which a laser diode (LD) array and a two-channel LD driver IC were integrated. Heat absorption through a highly thermal conductive silicon terrace kept the average output power constant to within 5% during IC operation. Bit-error-rate (BER) measurement showed that this module operated successfully with a 9-Gb/s nonreturn-to-zero (NRZ) signal. This indicates that the PLC platform does not have any adverse effect on the frequency bandwidth of the integrated chips. This approach, using the PLC platform for integrating optoelectronic devices and electronic ICs, will lead to the development of a high-speed optical multichip module for optical signal processing.

Optics and electronics are living together

The differences between optoelectronic and electronic ICs are identified. Crystal growth and device fabrication techniques for optoelectronic ICs are discussed, focusing on their advantages and disadvantages. Two novel devices that exist only as discrete components and will perform even better when integrated with other components on a monolithic chip are highlighted. One is an integrated passive cavity laser, which overcomes one of the drawbacks of semiconductor lasers, i.e. that they emit light over a relatively wide spectral band and are thus less coherent than other lasers. The other is a surface-emitting laser which emits light normal to its top surface and can therefore be placed anywhere on the substrate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>