Electronic IC Research Articles

Co-Packaged Optics - Heterogeneous Integration of Photonic IC and Electronic IC

Abstract The trends in co-packaged optics will be investigated in this study. Emphasis is placed on the heterogeneous integration of photonic IC (PIC) and electronic IC (EIC). In particular, 2D and 3D heterogeneous integration of ASIC Switch, PIC and EIC w/o bridges, and heterogeneous integration of ASIC Switch, PIC and EIC on glass substrate will be discussed. Some recommendations will be provided.

Developing a highly responsive miniaturized security device based on a printed copper ammine energetic composite

This work presents a triggerable ultimate security device (USD) capable of physically destroying a memory chip that contains classified data within a few milliseconds upon the detection of intrusion. The USD is designed as an add-on module that can be positioned onto any electronic chip, IC circuit, or memory card without requiring any specialized chip design, substrate type or encapsulation solution. Its operation is simply based on the exothermic reaction of a solid-state printed energetic composite that physically disintegrates the sensible component in less than 1 ms. The solid-state energetic composite consists of a mixture of Al/CuO nanothermite with a copper ammine complex densely printed onto the chip that is meant to be destroyed. This energetic layer can be ignited through resistive heating or capacitance discharge in less than 50 µs. The paper details the fabrication and assembly of a test USD device and demonstrates that 400 mg of energetic composite can be used to irreversibly destroy one silicon chip (~120 mm 3 ) in less than 10 ms. The outcome of this work also shows that the reaction time and efficiency are highly dependent on the reactive material loading, i.e., the mass of nanothermites deposited into the device and memory card. • A novel ultimate security device concept is designed and developed. • The actuation is based on the reaction of a confined safe copper ammine energetics placed on the circuitry to be destroyed. • The pressure burst can be easily tuned by modifying the energetic composite solid loading. • A fast response is demonstrated. • The concept and technology hold potential for commercial scale production.

Reinforcing a Bridging Connection Design for Electronic IC Device with Complex Wire Layout Requirement

Reinforcing a Bridging Connection Design for Electronic IC Device with Complex Wire Layout Requirement

High-Dimensional Uncertainty Quantification of Electronic and Photonic IC With Non-Gaussian Correlated Process Variations

Uncertainty quantification based on generalized polynomial chaos has been used in many applications. It has also achieved great success in variation-aware design automation. However, almost all existing techniques assume that the parameters are mutually independent or Gaussian correlated, which is rarely true in real applications. For instance, in chip manufacturing, many process variations are actually correlated. Recently, some techniques have been developed to handle non-Gaussian correlated random parameters, but they are time-consuming for high-dimensional problems. We present a new framework to solve uncertainty quantification problems with many non-Gaussian correlated uncertainties. First, we propose a set of smooth basis functions to well capture the impact of non-Gaussian correlated process variations. We develop a tensor approach to compute these basis functions in a high-dimension setting. Second, we investigate the theoretical aspect and practical implementation of a sparse solver to compute the coefficients of all basis functions. We provide some theoretical analysis for the exact recovery condition and error bound of this sparse solver in the context of uncertainty quantification. We present three adaptive sampling approaches to improve the performance of the sparse solver. Finally, we validate our methods by synthetic and practical electronic/photonic ICs with 19 to 57 non-Gaussian correlated variation parameters. Our approach outperforms Monte Carlo by thousands of times in terms of efficiency. It can also accurately predict the output density functions with multiple peaks caused by non-Gaussian correlations, which are hard to capture by existing methods.

Guitar Audio Amplifier Using IC LM386

Abstract The paper proposes the development of a guitar audio amplifier that is made from a low-priced IC LM386 chip, this amplifier can also be used for radios and other electronic projects IC LM 386 is a reliable and versatile chip that can be used even to make an oscillator that can output sine or square waves. The purpose behind developing this guitar audio amplifier is to offer an easy and economical way to build a good sounding amplifier.

A molecular dynamic study of change in thermodynamic functions of silicon FCC cell with the change in temperature

In modern days silicon is being extensively used in making electronic semiconductor-based chips and IC’s. In this research, the change in different thermodynamic properties of silicon like lattice heat capacity, molar enthalpy and Debye temperature at constant pressure, with the change in temperature, has been investigated by using molecular dynamics (MD) simulation method. Knowing silicon’ thermodynamic functions are quite important, because many electronic companies are nowadays trying a lot to reduce the heat generated by their semiconductor chips as excessive heating of the chip not only warms up the device quickly but also reduces the chip life. The results obtained from this simulation help engineers to design electronic chips more efficiently. For simulation “Accelrys Materials Studio” (Version 5.0) software has been used. The simulation was run for silicon FCC diamond structured cell. The analysis tool used in the simulation is known as CASTEP (Cambridge Sequential Total Energy Package). This tool is specialized for performing molecular level thermodynamic analysis to generate data and graphs for the change in different temperature dependent properties of the molecular system. The interaction between silicon atoms was expressed by the Kohn-Sham potential and MD calculation was conducted on crystalline state of silicon at temperatures between 0 and 1000 K. Here, density function theory (DFT) based tool has been used to derive density of state relations. Results obtained by the simulation were compared with published experimental values and it was found that the simulation results were close to the experimental values.

Study on the Malfunction Characteristics of Mobile Device by AC High Electric Field

Due to the development of technology, core technologies and information leakage of companies through mobile devices are increasing. Therefore, Various researches on electronic devices and IC elements protection technologies have been conducted. In the case of high frequency electromagnetic waves, it is harmful to the human body and damages electronic devices, making it difficult to apply them to real life. In this study, we investigated the characteristics of malfunction of shooting and recording function of smartphone near 20kHz which is audible frequency, not electromagnetic wave of high frequency band. Experimental results show that the camera is touched arbitrarily or the focus of the camera is changed. It can be applied to various industrial technology fields in the future.

Insights Into Silicon Photonics Mach–Zehnder-Based Optical Transmitter Architectures

Mach–Zehnder-based modulator architectures lend themselves to the realization of high-data-rate Silicon Photonics transmitters. In this work the challenges set by the integration of such devices on silicon are analyzed in depth. The two main alternative electronic driver architectures, namely multistage and travelling wave, are compared with focus to power efficiency. This is, in fact, a key parameter when considering the stringent requirements of standard module form factors. A 25 Gbps multistage and a 56 Gbps travelling wave modulator have been realized. Each electro-optical transmitter is obtained by the 3D assembly of an electronic IC on top of a photonic IC through copper pillars. STMicroelectronics PIC25G Silicon Photonics platform has been adopted for the fabrication of optical devices, while 65 nm CMOS and 55 nm BiCMOS technologies are exploited to realize the electronic drivers. A 30% better power efficiency compared to Silicon Photonics state-of-the-art at similar data rates and comparable extinction ratio performance has been demonstrated in both cases. Since packaging is also a crucial aspect for Silicon Photonics high volume production, experiments on bare dice as well as on packaged chips are reported.

Improvement of Leakage Trip Operation Time through Electronic Circuits Analysis of the Circuit-Breakers for Human Body Protection Against Electric Shock

This paper analyzed the electronic circuit and investigated the electrical properties to improve the tripping time of domestic ELCB. The operating time of the ELCB showed different values according to the location of voltage waveform and the duration time of leakage current at the instant when the leakage input signal is occurred under rated voltage, and the maximum value of the time measured was up to 26 ms. This was due to the time delay of the IC characteristics used in the electronic circuit which is operated only for the reverse half cycle of the sine wave. The authors developed a prototype circuit breaker with optimized delay element and performed an operation test, through which reduction of the ELCB trip time required for the circuit breaker standard by half was possible. Reduction of operating time of ELCB implies improvement of human body protection against electric shock. It is expected that production of safer ELCB will be possible in the future if more advanced and reliable electronic circuit or IC is developed.

Automated Trace-Explosives Detection for Passenger and Baggage Screening

Based on a high-throughput trace-explosives detector, two security equipment were developed to check passengers and baggage before boarding an aircraft. The trace-explosives detector consists of an automated particles sampler and a compact mass spectrometer. In the automated particles sampler, particles adhering to a surface of the detection targets are removed by air jets. A cyclone preconcentrator is then used to collect the particles removed from the detection targets. The collected particles are vaporized by a vaporizer, and the vaporized molecules are analyzed by the mass spectrometer. For the passenger screening, the trace-explosives detector was installed into a boarding gate. When a passenger passes an electronic ticket ( $e$ -ticket) or IC card over the $e$ -ticket reader of the boarding gate, compressed air jets are emitted from a nozzle toward the $e$ -ticket. The throughput of the passenger screening is $\sim 1200$ persons/hour. For the baggage screening, on the other hand, the trace-explosives detector was combined with a conventional X-ray baggage screener. When a bag is put on the conveyor belt of the automated particle sampler, compressed air jets are emitted from nozzles. The trace analysis is finished, while an X-ray image of the bag is being obtained by the X-ray baggage screener. In the both security equipment, the tested explosives’ particulate simulants of 2, 4, 6-trinitrotoluene, 1, 3, 5-trinitro-1, 3, 5-triazacyclohexane, and triacetone triperoxide adhered to the detection targets are successfully detected. Accordingly, the newly developed security equipment will be useful tools for improving airport security in the near future.

IEEE Journal of Solid State Circuits: The Evolution and Future of This Flagship Publication

In 1966, the first and the second issues of IEEE Journal of Solid-State Circuits (JSSC) were published in September and December. The articles in these issues were expanded versions of papers from the 1966 International Solid-State Circuits Conference (ISSCC) [1]. The articles were written by groups of authors from companies and universities in the United States. A large number of the papers described various bipolar amplifiers with low-drift, wideband, band-pass, low-power, and frequency selective features; oscillators; and the differential sense amplifier for ferrite memory. The performance of NMOS versus bipolar transistors at very high frequencies and a tunnel diode log amp were also described. Digital and memory papers were also included, such as the bipolar OR logic, current mode switch, selection circuitry for magnetic thin-film memory, and MOS adaptive memory. Functional electronic linear IC blocks for the Apollo Lunar Excursion Module television camera was also described.

(Keynote) Silicon Photonics Technology for Optical Communications with High Bandwidth Density Requirements (1Tbit/s and 1,000 Gbit/s/cm²)

As many applications emerge with the need for providing System-In-Package with optical I/Os, Silicon photonics technology shows great assets over other optical technologies: - The integrations of all the optical functions required to establish an optical transmission link have been demonstrated (silicon based modulators and (de)multiplexers, integration of Ge/Si photodetectors and heterogeneous integration of III-V/Si lasers). The fabrication is achieved in CMOS fabs on 200 and 300mm-wafers. - Besides the Si-Photonics technology enables the use of 3D assembling techniques for interconnecting the Silicon-Photonic Integrated Circuit (PIC) with its required driving Electronics (Electronic IC). Micro pillars can be used with ultra-low parasitics between the PIC and its companion EIC. The talk will review how the Silicon photonics technology toolbox developed at CEA-Leti (including the photonic devices library and the 3D assembling techniques for interconnecting PICs and EICs) scales with transmission applications having denser integration requirements (Tbit/s-class transceiver with bandwidth density > 1,000 Gbit/cm²). The performances of several demonstrators will be presented (25Gb/s receiver and 16-QAM transmitter) made from hybridation of Si-PICs and CMOS Electronic ICs).

Heterogeneous Integration of Plasmonics with Si-Photonics & Microelectronics for High-Performance Optical Routing

Advanced packaging technologies impact future systems, since packaging determines functionality, cost and reliability of future systems. The future systems are very high complex systems and contain different physical functions. Therefore modularity in heterogeneous integration is required. Future systems combine optical and ultra high frequency functions. With this a large variety of materials will be applied. For all these components a common smart support substrate such as ‘Silicon’ will be of importance for future systems. Furthermore, System-in-Package is must for future subsystems in order to overcome the challenges.In tems of of today’s Peta-flop High-Performance Computing (HPC) applications the size and power consumption appear to be critical issues, signifying that new technological and architectural considerations are required in order to be able to move towards Exascale-computing powers. Whereas silicon photonics emerges as a powerful technology for low-loss and high bandwidth optical connectivity in integrated circuit environments, servers and network switches are already consolidating into high-density blade enclosures in order to reduce space and cooling requirements. These considerations determine additional tasks for switching infrastructures of miniature data networks: the next generation of routing circuitry has to provide high throughput capabilities while keeping in line with the requirements of small foot-print, low power consumption and low latency. Here, next generation computing architectures are needed with ultra low power consumption; ultra high performance with novel photonic interconnection technologies. The objective of the recently proposed high bandwidth photonics interconnection layer for converged microsystems using System-in-Package Technology, is to develop a CMOS compatible underlying technology to enable next generation optical computing architectures.We present within the framework of EU-PLATON project a photonic integrated system-in-package platform for Tb/s optical routing, where three different technologies, silicon photonics, plasmonics and electronics are merged. Compatibility between various components has to be ensured to allow for their seamless interfacing and interoperability. The 4x4 router architecture exploits a SOI platform employing 340x400nm2 waveguide structures and hosting four 7:1 SOI multiplexing circuits, four photodiodes, an electronic IC control circuit and the 4x4 dielectric-loaded surface plasmon-polariton (DLSPP)-based switching matrix.This work has been partly supported by the European FP7 research program PLATON, Contract Number 249135. www.ict-platon.eu

Fatigue of Solder Interconnects in Microelectronic Assemblies under Random Vibration

This study investigates vibration fatigue durability of solder interconnects of surface mount electronic IC packages under harmonic and random excitation, through accelerated stress testing and physics-of-failure (PoF) simulations. The solder material of interest is Sn3.0Ag0.5Cu. The test vehicle consists of several HVQFN (Heat-sink Very-thin Quad Flat-pack No-leads) components soldered onto a Printed Wiring Board (PWB). The fatigue damage accumulation rates under ED random vibration excitation is found to be much higher than under harmonic vibration excitation, for equivalent RMS responses of PWB. To understand the reasons for such discrepancy we use FEA-based modeling. For simplicity of modeling we use a simple PWB with a simple Leadless Ceramic Resistor (LCR) component. We use a multiscale FEA modeling approach where the global analysis provides insights into the PWB modal response under the given excitation and can be conducted in the frequency-domain or in the time-domain. The local FEA model allows us to establish a transfer function between PWB curvature (flexural strain) in the vicinity of the critical component and equivalent strain in the critical region of the critical solder joint. al analysis is conducted to investigate the PWB mode shapes and natural frequencies, and they are compared with the measured strain time history, to understand the modal participation factors under both harmonic and ED random vibration excitation. The failure data is found to correlate well with the modal participations. Multiscale finite-element (FE) simulations are conducted to assess the dynamic response of the critical interconnects. This is done with two steps, first using a FE global analysis in the frequency domain for the global response consisting of all participating modes. Participation factors for individual modes are estimated from the global response, using numerical filtering methods. Inverse FFT is used to convert the frequency-domain response into the time-domain response histories for each dominant mode. In the second step, dynamic FE local analysis is conducted to obtain the transfer function between the PWB flexure and the strain in the critical solder interconnect for each dominant mode. Finally, rainflow cycle counting and Coffin-Manson fatigue model are used to estimate durability model constants and to compare fatigue damage accumulation rates under harmonic versus ED random vibration excitation.

An Integrated 40 Gbit/s Optical Costas Receiver

In this paper, a highly-integrated widely-tunable optical homodyne receiver is reported with 40 Gbaud/s data rate. By using photonic and electronic integration, the receiver is realized within a size of 10 × 10 mm2, and the system is very robust and resistive to environmental changes. An integrated photonic coherent receiver circuit is demonstrated with 35 GHz photodetector bandwidth, and the integrated local oscillator (LO) laser covers a 40 nm range. The electronic IC (EIC) has a working frequency up to 50 GHz. The feedback loop is carefully analyzed and designed, and the experimental results show > 1.1 GHz loop bandwidth, which matches the design. The hold-in range is measured to be > 15 GHz. The phase noise of the transmitting laser has been cloned to the LO laser quite well, and both the linewidth measurement and phase noise measurement show no observable cross talk between binary phase shift keying (BPSK) data and the optical phase-locked loop (OPLL). Error free ( bit error rate <; 10-12) is achieved up to 35 Gbit/s. The system consumes 3 Watts of power.

MEMS Capacitive Accelerometer-Based Middle Ear Microphone

The design, implementation, and characterization of a microelectromechanical systems (MEMS) capacitive accelerometer-based middle ear microphone are presented in this paper. The microphone is intended for middle ear hearing aids as well as future fully implantable cochlear prosthesis. Human temporal bones acoustic response characterization results are used to derive the accelerometer design requirements. The prototype accelerometer is fabricated in a commercial silicon-on-insulator (SOI) MEMS process. The sensor occupies a sensing area of 1mm × 1mm with a chip area of 2mm × 2.4mm and is interfaced with a custom-designed low-noise electronic IC chip over a flexible substrate. The packaged sensor unit occupies an area of 2.5mm × 6.2mm with a weight of 25mg. The sensor unit attached to umbo can detect a sound pressure level (SPL) of 60dB at 500Hz, 35dB at 2kHz, and 57dB at 8kHz. An improved sound detection limit of 34-dB SPL at 150Hz and 24-dB SPL at 500Hz can be expected by employing start-of-the-art MEMS fabrication technology, which results in an articulation index of approximately 0.76. Further micro/nanofabrication technology advancement is needed to enhance the microphone sensitivity for improved understanding of normal conversational speech.

Highly integrated optical heterodyne phase-locked loop with phase/frequency detection

A highly-integrated optical phase-locked loop with a phase/frequency detector and a single-sideband mixer (SSBM) has been proposed and demonstrated for the first time. A photonic integrated circuit (PIC) has been designed, fabricated and tested, together with an electronic IC (EIC). The PIC integrates a widely-tunable sampled-grating distributed-Bragg-reflector laser, an optical 90 degree hybrid and four high-speed photodetectors on the InGaAsP/InP platform. The EIC adds a single-sideband mixer, and a digital phase/frequency detector, to provide single-sideband heterodyne locking from -9 GHz to 7.5 GHz. The loop bandwith is 400 MHz.

Electronic Ballast Control IC With Digital Phase Control and Lamp Current Regulation

A digital control architecture is presented for electronic ballasts that provides a phase sweep for reliable, soft lamp ignition and a smooth transition to lamp current regulation mode. The controller is based on an inner phase loop for fast regulation of the resonant tank operating point and an outer current loop for lamp current regulation. The inner loop operates on a simple digital control law that computes the required gate timing relative to the inductor current positive zero crossing. Phase control provides reliable drive of the resonant converter in the presence of large dynamic changes in the load impedance during lamp ignition and warm up and natural tracking of component variations with temperature and time. The primarily digital approach provides programmability for broad application, insensitivity to process and temperature variations, realization in low cost CMOS processes and few external components. Experimental results are presented for an integrated ballast controller fabricated in a 0.8 mum CMOS process used in a 400 W, 150 kHz HID electronic ballast.

A 40‐Gb/s SCM optical communication system based on an integrated CMOS transceiver

AbstractIn this letter, the feasibility of a 40‐Gb/s subcarrier multiplexed optical transmission system using low‐cost optical electronic components and CMOIS IC technology is studied. A test chip and its measurement results are reported. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 1272–1274, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22433

PRESENT AND FUTURE OF HIGH-SPEED COMPOUND SEMICONDUCTOR IC's

This paper describes state-of-the-art of high-speed electronic device and IC technologies for very high-speed lightwave communications systems. The technology of interest is for over 40-Gbit/s transmitter and receiver operations. Device technology including Si-Ge, GaAs-based, and InP-based heterostructure transistors as well as circuit design technology including analog/digital/mixed-signal and optoelectronic IC's are reviewed. The speed limiting factors are discussed to address the future trends toward 100 Gbit/s and beyond.