Electronic Design Automation Community Research Articles

Combining informetrics and trend analysis to understand past and current directions in electronic design automation

There has been increasing interest in the study of research communities with the goal of optimizing their outcomes and impact. While current methods can predict future trends, they offer little insight about the causes of the trends. However, causal insight is important for strategic decision making to improve a community. This paper presents a new method to predict the possible causes for inefficiencies in a community by relating them to disconnections between trends, like trends in the number of publications, patents, citations, and so on. The method combines traditional scientometric and webometric metrics and metric predictions with a recent model for trend analysis in a community. The proposed method was used to analyze electronic design automation (EDA) domain. The analysis showed intriguing disconnections between the trends of the number of papers, number of granted patents, and impact of its main publications. The analysis suggests a slightly decreasing impact and visibility of EDA, while having less novel, commonly-accepted knowledge in the area. The gained insight suggests three possible strategic decisions to improve EDA community: avoiding to ignore new ideas, reducing the complexity of framed problems, and keeping a minimal gap between real-life needs and academic solutions.

OPDB: A Scalable and Modular Design Benchmark

Progress in electronic design automation (EDA) has enabled us to manage the exponential growth of complexity in integrated circuits (ICs) allowed by Moore’s Law, and translate it into performance improvements. Furthermore, as Moore’s law slows down and with the collapse of Dennard scaling over the past decade, EDA tools become increasingly important in addressing inefficiencies in ICs. As new proposals and techniques are put forward to address the current and future issues of IC design, a concrete set of contemporary benchmarks needs to be used for their evaluation. Traditionally, EDA researchers have mainly relied on industry provided design benchmarks in evaluating the performance of their tools. However, due to their effort to maintain their competitive advantage, industry releases include older designs with limited information about the details of each design. This means that in multiple cases, new proposals are evaluated with significantly dated designs, often more than a decade old, especially in terms of scale. In this work, we describe OPDB: a scalable, modular, heterogeneous, and extensible design benchmark for the EDA community. OPDB leverages and extends the OpenPiton open-source, tile-based research infrastructure to create a surplus of design benchmarks that target different components. Due to the tiled nature of this architecture, OPDB benchmarks can be made arbitrarily large in order to evaluate the efficiency of EDA tools across different design scales and configurations. OPDB contains several accelerators enabling full SoC designs to be used as benchmarks for EDA tools.

Heterogeneity of abstractions in EDA tools: Reviewing models of computation for many-core systems targeting intensive signal processing applications

Designing many-core systems for intensive signal processing applications necessitates refreshing common practices in the design of Electronic Design Automation (EDA) tools. This should change the focus of the EDA community from old-fashioned foundations including heavy implementations and time-consuming simulations, to recent engineering practices promoting rapid design and acceptable accuracy. Hence, the challenge of the EDA community comes to define a design process for many-core systems which enables four goals: modeling conciseness, estimation accuracy, design rapidity, and exploration flexibility. In this scenario, the modeling task can be defined as a delicate design phase that requires choosing the adequate Model of Computation (MoC) at each step of the design process. Design models at each level of abstraction provide the basis for applying analysis, synthesis or verification techniques. Since modeling concepts and techniques can have a large influence on the quality, accuracy and rapidity of results, models and corresponding abstraction levels should be well-defined with clear and unambiguous semantics. In this paper, we aim to provide an analysis and comparative overview of common MoCs used in the specification and performance analysis of intensive signal processing applications and many-core architectures. After identifying conventional classifications, we propose a new taxonomy of MoCs based on their purpose in the design flow. The heterogeneity of MoCs in EDA tools is also discussed and various tools are reviewed and compared.

Boolean Satisfiability Solvers and Their Applications in Model Checking

Boolean satisfiability (SAT)—the problem of determining whether there exists an assignment satisfying a given Boolean formula—is a fundamental intractable problem in computer science. SAT has many applications in electronic design automation (EDA), notably in synthesis and verification. Consequently, SAT has received much attention from the EDA community, who developed algorithms that have had a significant impact on the performance of SAT solvers. EDA researchers introduced techniques such as conflict-driven clause learning, novel branching heuristics, and efficient unit propagation. These techniques form the basis of all modern SAT solvers. Using these ideas, contemporary SAT solvers can often handle practical instances with millions of variables and constraints. The continuing advances of SAT solvers are the driving force of modern model checking tools, which are used to check the correctness of hardware designs. Contemporary automated verification techniques such as bounded model checking, proof-based abstraction, interpolation-based model checking, and IC3 have in common that they are all based on SAT solvers and their extensions. In this paper, we trace the most important contributions made to modern SAT solvers by the EDA community, and discuss applications of SAT in hardware model checking.

Fast Monte Carlo Estimation of Timing Yield With Importance Sampling and Transistor-Level Circuit Simulation

Considerable effort has been expended in the electronic design automation community in trying to cope with the statistical timing problem. Most of this effort has been aimed at generalizing the static timing analyzers to the statistical case. On the other hand, detailed transistor-level simulations of the critical paths in a circuit are usually performed at the final stage of performance verification. We describe a transistor-level Monte Carlo (MC) technique which makes final transistor-level timing verification practically feasible. The MC method is used as a golden reference in assessing the accuracy of other timing yield estimation techniques. However, it is generally believed that it can not be used in practice as it requires too many costly transistor-level simulations. We present a novel approach to constructing an improved MC estimator for timing yield which provides the same accuracy as standard MC but at a cost of much fewer transistor-level simulations. This improved estimator is based on a unique combination of a variance reduction technique, importance sampling, and a cheap but approximate gate delay model. The results we present demonstrate that our improved yield estimator achieves the same accuracy as standard MC at a cost reduction reaching several orders of magnitude.

Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems

Multi-objective evolutionary algorithms (MOEAs) have received increasing interest in industry because they have proved to be powerful optimizers. Despite the great success achieved, however, MOEAs have also encountered many challenges in real-world applications. One of the main difficulties in applying MOEAs is the large number of fitness evaluations (objective calculations) that are often needed before an acceptable solution can be found. There are, in fact, several industrial situations in which fitness evaluations are computationally expensive and the time available is very short. In these applications efficient strategies to approximate the fitness function have to be adopted, looking for a trade-off between optimization performance and efficiency. This is the case in designing a complex embedded system, where it is necessary to define an optimal architecture in relation to certain performance indexes while respecting strict time-to-market constraints. This activity, known as design space exploration (DSE), is still a great challenge for the EDA (electronic design automation) community. One of the most important bottlenecks in the overall design flow of an embedded system is due to simulation. Simulation occurs at every phase of the design flow and is used to evaluate a system which is a candidate for implementation. In this paper we focus on system level design, proposing an extensive comparison of the state-of-the-art of MOEA approaches with an approach based on fuzzy approximation to speed up the evaluation of a candidate system configuration. The comparison is performed in a real case study: optimization of the performance and power dissipation of embedded architectures based on a Very Long Instruction Word (VLIW) microprocessor in a mobile multimedia application domain. The results of the comparison demonstrate that the fuzzy approach outperforms in terms of both performance and efficiency the state of the art in MOEA strategies applied to DSE of a parameterized embedded system.

Modelling tools built upon the hardware description language foundation

Hardware description languages (HDLs), mainly Verilog and VHDL including their analogue/mixed-signal (AMS) extensions, represent a significant investment by the electronic design automation community. HDL technology promises productivity advances, such as a medium for intellectual property exchange, model portability, model productivity, improved design collaboration, top-down design for AMS, AMS synthesis and rich mixed-level, mixed-signal simulation for improved simulation throughput. Modelling tools represent a step towards completion of the dwelling electronic design automation community's seek to build upon the HDL foundation. One such environment of tools described here is Paragon. Paragon is described and demonstrated on both behavioural models using multiple HDLs and compact device modelling applications. The various processes and modelling methodologies that are useful in designing and modelling complex mixed-signal circuits and systems are explored. The model creation processes of mixed-signal and mixed-technology systems at various levels of abstraction and hierarchy are described. Creation of compact behavioural models at a more abstract and language-independent level using these modelling methodologies is illustrated.

Synthesis of quantum-logic circuits

The pressure of fundamental limits on classical computation and the promise of exponential speedups from quantum effects have recently brought quantum circuits (Proc. R. Soc. Lond. A, Math. Phys. Sci., vol. 425, p. 73, 1989) to the attention of the electronic design automation community (Proc. 40th ACM/IEEE Design Automation Conf., 2003), (Phys. Rev. A, At. Mol. Opt. Phy., vol. 68, p. 012318, 2003), (Proc. 41st Design Automation Conf., 2004), (Proc. 39th Design Automation Conf., 2002), (Proc. Design, Automation, and Test Eur., 2004), (Phys. Rev. A, At. Mol. Opt. Phy., vol. 69, p. 062321, 2004), (IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 22, p. 710, 2003). Efficient quantum-logic circuits that perform two tasks are discussed: 1) implementing generic quantum computations, and 2) initializing quantum registers. In contrast to conventional computing, the latter task is nontrivial because the state space of an n-qubit register is not finite and contains exponential superpositions of classical bitstrings. The proposed circuits are asymptotically optimal for respective tasks and improve earlier published results by at least a factor of 2. The circuits for generic quantum computation constructed by the algorithms are the most efficient known today in terms of the number of most expensive gates [quantum controlled-NOTs (CNOTs)]. They are based on an analog of the Shannon decomposition of Boolean functions and a new circuit block, called quantum multiplexor (QMUX), which generalizes several known constructions. A theoretical lower bound implies that the circuits cannot be improved by more than a factor of 2. It is additionally shown how to accommodate the severe architectural limitation of using only nearest neighbor gates, which is representative of current implementation technologies. This increases the number of gates by almost an order of magnitude, but preserves the asymptotic optimality of gate counts