Electronic Code Book Mode Research Articles

Implementasi AES ECB dan Hashing MD5/SHA-256 Pada Aplikasi Penyuratan Android

The Riau Ministry of Religion Regional Office is still archiving assignment letters and official travel letters manually. The staff who take care of the correspondence section, namely personnel and legal unit staff, do not have an application that facilitates the activities of assignment letters and official travel letters to simplify filing and data containing certain information contained in letters which include assignment letters and official travel letters. Security is important because it relates to data. Therefore, a correspondence application was created to support the correspondence activities of the Riau Ministry of Religion Regional Office and make it easier for staff in the Civil Service and Legal unit to properly manage assignment letters and official travel letters as well as control books. Android application development uses the waterfall method and the ECB (Electronic Code Book) mode AES algorithm and MD5/SHA-256 hashing for security. By building this application, it will be easier for leaders and employees to exchange letters and confidential information, guaranteed security and the application built can be used by users easily. The results of the Black Box testing carried out on the application produced the expected output and the UAT test obtained a score of 89%. Application testing on sentences, Jpg, Png and PDF files has a fairly high level of security using statistical analysis methods, namely bit frequency testing, autocorrelation, 0/1 bit distribution, entropy.

A secure data parallel processing based embedded system for internet of things computer vision using field programmable gate array devices

SummaryTechnologies and new standards have converted the traditional networks and systems into new smart cities integrated networks. Different factors are behind to build these new networks in terms of hardware, software, standards, technologies, and infrastructure. Internet of things (IoT) is one of the popular network types based on small and portable devices. Some of the IoT applications are more critical and sensitive like smart healthcare systems wherein time data delivery is needed without any delay. Keeping in view the criticality of such applications, this study proposes a secure storage, processing and transmission (SSPT) technique. This technique is based on two modules named Advanced Encryption Standard (AES) in Electronic Code Book (ECB) mode and AES in Ciphered Message Authentication Code (CMAC) mode. In the first module, the AES is implemented in ECB mode to provide encryption to IoT computer vision data. In the second module, the AES is integrated with the CMAC algorithm to provide encryption, integrity, and authentication. The said modules are implemented in a field programmable gate array (FPGA) device which acts as a secure edge computing device. The SSPT is verified by the test vectors given by international standards such as the National Institute of Standards and Technologies (NIST) and Federal Information Processing Standards (FIPS) which are adaptable, proficient, and vigorous as compared to previous techniques.

The research of performance of the “Cypress” lightweight block cipher on different platforms

The Cypress block cipher is a lightweight algorithm based on the Feistel network with ARX-transformation as a round function. The Cypress block cipher supports 256-bit and 512-bit block and key length. The paper presents results of researches on the performance of lightweight block ciphers Cypress-256 and Cypress-512 and it gives comparison of performance of other well-known block ciphers such as AES-256, SPECK-64/128, SPECK-128/128, SPARX-128/128, DSTU GOST 28147: 2009. Performance was evaluated on Windows, Linux and Android platforms by measuring the encryption speed in the Electronic Code Book mode, in Mbps. The Cypress block cipher has demonstrated high performance on all selected platforms. Cypress-256 showed the best result (almost 3.5 Gbps) on the Windows 10 platform with 32-bit architecture. Cypress-512 also showed the best result (almost 5 Gbps) on the Windows 10 platform with 64-bit architecture. On the Linux platform with a 64-bit architecture, Cypress-256 showed a very high speed result (more than 8 Gbps). Cypress-256 and Cypress-512 block ciphers were also the best (1.3 Gbps and 1 Gbps, respectively) on the Android platform. In terms of performance and simplicity of implementation on different software and hardware platforms, Cypress algorithm has several advantages. Two variants of cipher (Cypress-256 and Cypress-512) are oriented on 32-bit and 64-bit architectures, respectively; high speed and compact implementation of transformations regardless of the platform used (server, workstation or mobile device). Minimum amount of memory is required for high-speed implementation, there is no need in pre-computed tables; there is an ability to organize efficient secure high-speed communication channels between mobile systems and servers, including those using hardware accelerators.

Hardware Acceleration of AES Cryptographic Algorithm for IPSec

This research considers the offloading of the IPsec packet encryption algorithm into an FPGA by proposing a hardware acceleration of the AES cryptographic algorithm for IPsec. We point out the benefits of relying on HW acceleration in terms of speed and energy efficiency for applications like IPsec. We present the description of the architecture of the proposed solution, the simulation results of our implementation of the AES algorithm in ECB (Electronic Code Book) mode. We also present the integration of the encryption core with the IPsec subsystem through a PCIe bus interface so that the resulting implementation is interoperable with other systems.

Power Consumption and Calculation Requirement Analysis of AES for WSN IoT.

Because of the ubiquity of Internet of Things (IoT) devices, the power consumption and security of IoT systems have become very important issues. Advanced Encryption Standard (AES) is a block cipher algorithm is commonly used in IoT devices. In this paper, the power consumption and cryptographic calculation requirement for different payload lengths and AES encryption types are analyzed. These types include software-based AES-CB, hardware-based AES-ECB (Electronic Codebook Mode), and hardware-based AES-CCM (Counter with CBC-MAC Mode). The calculation requirement and power consumption for these AES encryption types are measured on the Texas Instruments LAUNCHXL-CC1310 platform. The experimental results show that the hardware-based AES performs better than the software-based AES in terms of power consumption and calculation cycle requirements. In addition, in terms of AES mode selection, the AES-CCM-MIC64 mode may be a better choice if the IoT device is considering security, encryption calculation requirement, and low power consumption at the same time. However, if the IoT device is pursuing lower power and the payload length is generally less than 16 bytes, then AES-ECB could be considered.

TBLT-AES: A Robust Image Encryption Scheme

In the digital world, security is an important issue, and encryption is one of the ways to ensure confidentiality. Especially protection of multimedia data is now becoming a big challenge to us. A large number of algorithms for data and image encryption are reported in the literature. But due to their cryptographic weakness or high computational cost, many of them are not suitable in practical applications. In this paper, we introduce an image encryption scheme where a linear transformation is performed before encryption. The encryption is done by employing Advanced Encryption Standard (AES) in Electronic Code Book mode to achieve high throughput. The results showed that the correlation between adjacent image elements was significantly reduced by employing the proposed scheme compared to other schemes. The histogram, correlation, entropy analysis as well as differential cryptanalysis have been done to justify the strength of the proposed scheme.

XOR 연산의 자유 공간 병렬 처리를 이용한 광학적 CBC 블록 암호화 기법

본 논문에서는 블록암호화의 CBC(Cipher Block Chaining) 방식을 광학적인 XOR 연산을 이용하여 새로운 변형된 CBC 암호화 및 복호화 시스템을 제안한다. 제안한 방법은 광학적 XOR 연산의 병렬 처리를 위해 이중 인코딩 방법과 자유 공간 연결 광논리 게이트 방법을 사용한다. 또한 제안된 XOR 연산 기반의 CBC 암호화 방식의 광학적 구성도를 공학적으로 실제 제작 구현 가능한 광 모듈 형태의 광 암호화/복호화 장치로 제안한다. 제안된 방법은 기존의 CBC 방식을 광학적으로 구현했기 때문에 기존의 전자적인 CBC 방식의 장점과 광학적인 고속성과 병렬 처리의 특성으로 인해 많은 정보를 빠른 속도로 암호화 및 복호화가 가능하다. 또한, 광 병렬 처리의 특성상 데이터가 2차원으로 배열되어 데이타 크기가 증가된 평문 데이터와 암호키를 사용함으로써 기존의 전자적 CBC 방식보다도 한층 더 암호 강도가 강력해진 암호화 시스템을 제공한다. 컴퓨터 시뮬레이션 결과는 제안한 기법이 CBC 모드의 암호화 및 복호화 과정에 효율적임을 보여준다. 한편 제안된 방식은 CBC 방식 외에 ECB(Electronic Code Book) 방식과 CFB(Cipher Feedback Block) 방식에도 적용할 수 있다. In this paper, we propose a modified optical CBC(Cipher Block Chaining) encryption method using optical XOR logic operations. The proposed method is optically implemented by using dual encoding and a free-space interconnected optical logic gate technique in order to process XOR operations in parallel. Also, we suggest a CBC encryption/decryption optical module which can be fabricated with simple optical architecture. The proposed method makes it possible to encrypt and decrypt vast two-dimensional data very quickly due to the fast optical parallel processing property, and provides more security strength than the conventional electronic CBC algorithm because of the longer security key with the two-dimensional array. Computer simulations show that the proposed method is very effective in CBC encryption processing and can be applied to even ECB(Electronic Code Book) mode and CFB(Cipher Feedback Block) mode.

Real-Time Mode Hopping of Block Cipher Algorithms for Mobile Streaming

It has been shown that the encrypted information or ciphertext produced by symmetric-key block ciphers with Electronic codebook mode is vulnerable to ciphertext searching, replay, insertion and deletion because it encrypts each block independently. To compensate for this, each block of the encrypted information should be encrypted dependently. The encrypted information should be operated with a special mode. The operation mode should be changed. This paper analysis what an operational mode of block ciphers needs to feedback exactly and proposes a simple real-time changing operation mode technique that extends the existing mode changing opportunity. The new change operation mode technique considers the sign differences between the intra-feedback information and the public-feedback information, and then adaptively determines the corresponding change operation mode factor for each data block. This mode hopping technique for mobile streaming security is highly suitable for recent block computing in future various environments.

Randomness Analysis on Blowfish Block Cipher Using ECB and CBC Modes

Randomness of the output is one of the significant factors in measuring the security of any cryptographic algorithm.Non-random block cipher is vulnerable to any type of attack.This paper presents the National Institute of Standard and Technology (NIST) statistical tests of the Blowfish algorithm to investigate its randomness.Blowfish algorithm with Electronic Codebook (ECB) and Cipher Block Chaining (CBC) modes were conducted for these tests.In addition, comparisons between them were introduced.The analysis showed that Blowfish algorithm with ECB mode was inappropriate with data such as text and image files which have large strings of identical bytes.This inconsistency is due to the majority of the 188 statistical tests of NIST statistical tests failing in all rounds.

Study and Performance Evaluation of Security-Throughput Tradeoff with Link Adaptive Encryption Scheme

With the ever increasing volume of information over wireless medium, security has assumed an important dimension. The security of transmitted data over a wireless channel aims at protecting the data from unauthorized intrusion. Wireless network security is achieved using cryptographic primitives. Some properties that give encryption mechanism their cryptographic strength also make them very sensitive to channel error as well. Therefore, security for data transmission over wireless channel results in throughput loss. Trade-off between security and throughput is always a major concern in wireless networks. In this paper, a Link Adaptive Encryption scheme is evaluated that adapts to channel variations and enhances the security level of WLANs without making any compromise with the network performance. Numerical results obtained through simulation are compared with the fixed block length encryption technique in two different modes of operation- Electronic Code Book (ECB) & Cipher Block Chaining (CBC). Optimal block length is also computed, which is assumed to be the effective strength of the cipher. It has been observed that security attained with link adaptive scheme operating in ECB mode of cipher is a better solution for security and throughput trade-off. However, it is found that if computational security is a major concern, link adaptive scheme in CBC mode should be preferred.

Design of an Encryption-Decryption Module Oriented for Internet Information Security SOC Design

In order to protect the security of network data, a high speed chip module for encrypting and decrypting of network data packet is designed. The chip module is oriented for internet information security SOC (System on Chip) design. During the design process, AES (Advanced Encryption Standard) and 3DES (Data Encryption Standard) encryption algorithm are adopted to protect the security of network data. The following points are focused: (1) The SOC (System on Chip) design methodology based on IP (Intellectual Property) core is used. AES (Advanced Encryption Standard) and 3DES (Data Encryption Standard) IP (Intellectual Property) cores are embedded in the chip module, peripheral control sub-modules are designed to control the encryption-decryption module, which is capable of shortening the design period of the chip module. (2) The implementation of encryption-decryption with hardware was presented, which improves the safety of data through the encryption-decryption chip and reduce the load of CPU. (3) In our hardware solution, two AES (Advanced Encryption Standard) cores are used to work in parallel, which improves the speed of the encryption module. Moreover, the key length of AES (Advanced Encryption Standard) encryption algorithm is designed with three optional configurations at 128 bits, 256 bits and 192 bits respectively and six optional encryption algorithm modes: CBC (Cipher Block Chaining) mode, ECB (Electronic Code Book) mode, GCM (Galois/Counter Mode) mode, XTS(cipherteXT Stealing) mode, CTR (CounTeR) mode and 3DES respectively, which adds the flexibility to its applications.

A New Method for Encrypting Images with Few Details Using Rijndael and RC6 Block Ciphers in the Electronic Code Book Mode

ABSTRACT In this paper, we propose an efficient method for encrypting images with few details using Rijndael and RC6 block ciphers in Electronic Code Book (ECB) mode. Images with few details are images with large areas of similar gray levels such as medical images, infrared images, and logo images. This leads to encryption leakage if the Rijndael or RC6 block ciphers are used. The proposed method solves this problem by using a preprocessing step to eliminate the repeated patterns before encryption. A comparison is held between encryption of images with few details with preprocessing and encryption without preprocessing. Experimental results verify that the proposed preprocessing method gives the encryption algorithms the ability to encrypt images with few details in an efficient manner in the ECB mode.

Generic architecture and semiconductor intellectual property cores for advanced encryption standard cryptography

A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modern communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.

GeoSight fact finder, GIS based software package

The Data Encryption Standard (DES) or Data Encryption Algorithm (DEA), ANSI standard X3.92-1981, is a well known symmetric block cipher. In the basic mode of operation, electronic code book mode, it encrypts blocks of 64 bits of plain text into 64 bits of cipher text using a 56-bit key. Its internal structure, which is highly non-linear and contains 18 permutations and 16 expansions of bit blocks, does not encourage software implementation but is much better suited for hardware implementation. However, by a series of equivalence transformations, all expansions and but two of the permutations can be eliminated. Furthermore, then the 16-bit or 32-bit architecture of modern microprocessors can be fully exploited. Both a 16-bit version of the transformed algorithm (for 8086 and 80286) and a 32-bit version (for 80386 and 80486) have been implemented in assembly language. Depending on the actual processor employed, the implementation chooses 16-bit code or 32-bit code at run time. A sustained throughput of over 75,000 bytes second on a 33-MHz 80386 with cache and of over 8800 bytes per second on a 10-MHz 80286 with one wait state is obtained. The program needs only 13·3 kbytes for code and data. Hence this high-performance software DES implementation is also well suited for embedded applications, as for instance for encryption of serial communication lines or ISDN voice and data channels.

A high-performance software implementation of the Data Encryption Algorithm (DEA)

The Data Encryption Standard (DES) or Data Encryption Algorithm (DEA), ANSI standard X3.92-1981, is a well known symmetric block cipher. In the basic mode of operation, electronic code book mode, it encrypts blocks of 64 bits of plain text into 64 bits of cipher text using a 56-bit key. Its internal structure, which is highly non-linear and contains 18 permutations and 16 expansions of bit blocks, does not encourage software implementation but is much better suited for hardware implementation. However, by a series of equivalence transformations, all expansions and but two of the permutations can be eliminated. Furthermore, then the 16-bit or 32-bit architecture of modern microprocessors can be fully exploited. Both a 16-bit version of the transformed algorithm (for 8086 and 80286) and a 32-bit version (for 80386 and 80486) have been implemented in assembly language. Depending on the actual processor employed, the implementation chooses 16-bit code or 32-bit code at run time. A sustained throughput of over 75,000 bytes second on a 33-MHz 80386 with cache and of over 8800 bytes per second on a 10-MHz 80286 with one wait state is obtained. The program needs only 13·3 kbytes for code and data. Hence this high-performance software DES implementation is also well suited for embedded applications, as for instance for encryption of serial communication lines or ISDN voice and data channels.

Data encryption unit

The Data Encryption Standard (DES) or Data Encryption Algorithm (DEA), ANSI standard X3.92-1981, is a well known symmetric block cipher. In the basic mode of operation, electronic code book mode, it encrypts blocks of 64 bits of plain text into 64 bits of cipher text using a 56-bit key. Its internal structure, which is highly non-linear and contains 18 permutations and 16 expansions of bit blocks, does not encourage software implementation but is much better suited for hardware implementation. However, by a series of equivalence transformations, all expansions and but two of the permutations can be eliminated. Furthermore, then the 16-bit or 32-bit architecture of modern microprocessors can be fully exploited. Both a 16-bit version of the transformed algorithm (for 8086 and 80286) and a 32-bit version (for 80386 and 80486) have been implemented in assembly language. Depending on the actual processor employed, the implementation chooses 16-bit code or 32-bit code at run time. A sustained throughput of over 75,000 bytes second on a 33-MHz 80386 with cache and of over 8800 bytes per second on a 10-MHz 80286 with one wait state is obtained. The program needs only 13·3 kbytes for code and data. Hence this high-performance software DES implementation is also well suited for embedded applications, as for instance for encryption of serial communication lines or ISDN voice and data channels.