Faults In Electronic Circuits Research Articles

Soft fault diagnosis in linear circuits: Test selection and non-iterative identification procedure

The paper deals with the diagnosis of soft faults in linear electronic circuits. Circuits containing operational amplifiers operating at low frequencies are considered. A method for identifying single and double faults in the AC domain is proposed. The method is non-iterative and relies on certain relations derived from the modified nodal description of the circuit. An essential part of the paper is a procedure enabling the selection of measurement nodes and test frequencies. The algorithm considers the AC sensitivities, the measurement accuracy, and the diagnostic method applied. The effectiveness of both methods was verified on several electronic circuits. The simulation and laboratory tests were done. Considering parameter tolerances and measurement uncertainties leads to determining intervals of parameter values covering the actual faults.

Integer Algorithm: A Useful Tool for Fault Diagnosis of Analog Circuits

This paper presents an efficient numerical method to solve systems of nonlinear algebraic equations. The method uses a homotopy simplicial approach associated with an integer algorithm. The integer algorithm is discussed in detail and supplemented with original procedures that play an essential role during computation. The fundamental problem of initial simplex generation was solved using the bounded variable simplex optimization method. Efficient root finding of nonlinear equations has wide applications in numerical mathematics and various engineering problems. The proposed method was applied to solve nonlinear equations that arise during the diagnostics of multiple parametric faults in electronic circuits. Circuits made with surface mount technology were considered, as well as circuits designed in complementary metal-oxide-semiconductor and bipolar technology. A universal diagnostic procedure enables testing different circuit classes using standard measurement equipment. Laboratory and numerical experiments demonstrate that the proposed diagnostic procedure is effective.

Research on Electronic Circuit Fault Diagnosis Method Based on SWT and DCNN-ELM

Research on Electronic Circuit Fault Diagnosis Method Based on SWT and DCNN-ELM

Investigating the Use of Artificial Intelligence for Fault Detection in Electronic Circuits

Many control systems and industrial applications rely heavily on analogue electrical circuits. Diagnosing problems with such circuits the old-fashioned manner can be erroneous and time consuming, which can have a detrimental impact on the industrial product. Also Keeping up with the ever-increasing sophistication of modern electronics has made testing these systems a formidable challenge. Due to the complexity and amount of individual parts on a PCB, traditional simulation-based methods cannot be used, and instead, artificial intelligence-based methods must be prioritization intriguing area of study that has the potential to improve the safety and reliability of electronic systems is the use of artificial intelligence (AI) to the task of detecting faults in electronic circuits. Real-time defect identification, diagnosis, and localization are made possible by AI-based solutions, which can assist prevent system breakdowns and boost performance. Fault detection in electronic circuits has been approached using a wide variety of artificial intelligence (AI) based methods, each with their own set of benefits and drawbacks. The availability of labelled training data, the generalizability of AI models, and the interpretation of AI-based fault detection outcomes are just a few of the obstacles that must be overcome. Despite these limitations, problem detection based on AI has many potentials uses in industries like transportation, energy, healthcare, and more. In this study, we survey the landscape of available AI-based fault detection systems for electronic circuits, discussing their merits and shortcomings, difficulties, and possible applications. This study details an inquiry into the viability of utilising an AI approach to failure prediction and early detection in power systems. A machine-learning detector has been created to keep an eye on specific parts of electricity grids and anticipate any problems before they occur.The AI failure prediction system can quickly anticipate a system failure.

Design of electronic circuit fault diagnosis based on artificial intelligence

Design of electronic circuit fault diagnosis based on artificial intelligence

Design of electronic circuit fault diagnosis based on artificial intelligence

Design of electronic circuit fault diagnosis based on artificial intelligence

Electronic Circuit Fault Diagnosis and Prediction Technology Analysis

Electronic Circuit Fault Diagnosis and Prediction Technology Analysis

The Analysis of Electronic Circuit Fault Diagnosis Based on Neural Network Data Fusion Algorithm

Symmetries play very important roles in the dynamics of electrical systems. The relevant electronic circuits with fault diagnostics, including the optimized neural network algorithm model, are designed on the basis of symmetry principles. In order to improve the efficiency of the circuit pressure test, a circuit pressure function equivalent compression test method based on the parallel neural network algorithm is proposed. For the implementation stage of the circuit pressure test, the improved modified node algorithm (MNA) is used to build an optimization model, and the circuit network is converted into an ordinary differential equation for the circuit pressure function equivalent compression test. The test aims to minimize flux. Then, backpropagation (BP) neural network algorithm data fusion is introduced to optimize the minimum flux model of the cyclic pressure functional equivalent compression test. Finally, a simulation experiment is carried out to verify the effectiveness of the algorithm in the accuracy and efficiency of the pressure test. The results show that the improved BP neural network improves the data fusion accuracy and shortens the sample training time; compared with the uncompressed algorithm, the running time of the proposed algorithm is greatly reduced and the execution efficiency is high; compared with the vascular pressure test method, there is no significant difference in the convergence accuracy and it is at a level of 10−5. Since the parallel computing problem is not considered in either of the two-pulse tube pressure test methods, the convergence time of the algorithm increases exponentially with the increase in the number of parallel threads. However, the algorithm in this research considers the problem of parallel execution and uses a quad-core processor, with no significant change in computing time and high computing efficiency. Therefore, BP neural network data fusion can be used for the fault diagnosis of electronic circuits, with a high operating efficiency and good development prospects.

Adaptive Weighted VMD-WPEE Method of Power-Electronic-Circuit Multiple-Parameter-Fault Diagnosis

To improve the diagnostic accuracy rate of multiple parameter faults in widely used power electronic circuits, solving for the overlapping parameter fault characteristic signal is crucial. This paper proposes a novel approach for diagnosing the multiple parameter faults of power electronic circuits that can adaptively adjust the weights of each fault feature parameter according to the diagnostic accuracy rate to enhance their discriminability. According to the properties of multiple parameter faults in power electronic circuits, the measured signal that has been decomposed via the variational mode decomposition and wavelet packet energy entropy (VMD-WPEE) is used to extract the feature parameters. Furthermore, a classifier is selected and the threshold of the diagnostic accuracy rate is set. Then, the weight of each fault feature parameter is adjusted until the classifier yields the desired results. Finally, the proposed approach is applied to other classifiers and feature extraction methods. The high accuracy, high robustness, and advantages of the multiple-parameter-fault diagnosis method are demonstrated by the simulation and experimental results.

A method for multiple soft fault diagnosis of linear analog circuits

The problem of testing and diagnosing multiple soft faults in analog linear electronic circuits is discussed in this paper. An efficient method which detects faulty elements and evaluates their parameters is developed. The algorithm employs two diagnostic tests, carried out in AC state, providing rms values of the measured voltages. One of them, called a principal test, is used by the diagnosis procedure whereas the other test serves the validation purpose. Each of the voltages is an algebraic function of the tested parameters. The proposed algorithm solves least squares problem by minimizing the sum of squares of the differences between the measured voltages and the parametrized functions using the Levenberg-Marquardt method. The algorithm is applied to all testable sets of the elements and every time the result is verified using the validating test. The method may provide more than one set of the parameters which satisfy both tests due to ambiguity groups existing in the circuit. To adapt the method to the conditions encountered in practice, perturbations of the fault–free parameters and measurement uncertainty are taken into account. For illustration of the method the diagnoses of three benchmark linear electronic circuits are discussed using laboratory performed tests.

Electronic Circuit Health Estimation Through Kernel Learning

Degradation of electronic components is typically accompanied by a deviation in their electrical parameters from their initial values, which can ultimately lead to parametric faults in electronic circuits. Existing approaches to predict parametric faults emphasize identifying monotonically deviating parameters and modeling their progression over time. However, in practical applications, where the components are integrated into a complex electronic circuit assembly, product, or system, it is generally not feasible to monitor component-level parameters. To address this problem, a circuit health estimation method was developed using a kernel-based machine-learning technique. This method exploits features that are extracted from responses of circuit-comprising components exhibiting parametric faults, instead of the component-level parameters. The method was evaluated using data from simulation experiments on a benchmark Sallen–Key filter circuit and a dc–dc converter system.

Optimal Design of Rectification Circuit in Electronic Circuit Fault Self‐repair Based on EHW and RBT

Reliability of traditional electronic circuit is improved mainly by redundant fault-tolerant technology with large hardware resource consumption and limited fault self-repair capability. In complicated environment, electronic circuit faults appear easily. If on-site immediate repair is not implemented, normal running of electronic system will be directly affected. In order to solve these problems, Evolvable hardware (EHW) technology is widely used. The conventional EHW has some bottlenecks. The optimal design of Rectification circuit (RTC) is further researched on the basis of the previously proposed fault self-repair based on EHW and Reparation balance technology (RBT). Fault sets are selected by fault danger degree and fault coverage rate. The optimal designed RTC can completely repair faults in the fault set. Simulation results prove that it has higher self-repair capability and less hardware resource.

A Fast Classification Method of Faults in Power Electronic Circuits Based on Support Vector Machines

AbstractFault detection and location are important and front-end tasks in assuring the reliability of power electronic circuits. In essence, both tasks can be considered as the classification problem. This paper presents a fast fault classification method for power electronic circuits by using the support vector machine (SVM) as a classifier and the wavelet transform as a feature extraction technique. Using one-against-rest SVM and one-against-one SVM are two general approaches to fault classification in power electronic circuits. However, these methods have a high computational complexity, therefore in this design we employ a directed acyclic graph (DAG) SVM to implement the fault classification. The DAG SVM is close to the one-against-one SVM regarding its classification performance, but it is much faster. Moreover, in the presented approach, the DAG SVM is improved by introducing the method of Knearest neighbours to reduce some computations, so that the classification time can be further reduced. A rectifier and an inverter are demonstrated to prove effectiveness of the presented design.

Optimal design of RTCs in digital circuit fault self-repair based on global signal optimization

Since digital circuits have been widely and thoroughly applied in various fields, electronic systems are increasingly more complicated and require greater reliability. Faults may occur in electronic systems in complicated environments. If immediate field repairs are not made on the faults, electronic systems will not run normally, and this will lead to serious losses. The traditional method for improving system reliability based on redundant fault-tolerant technique has been unable to meet the requirements. Therefore, on the basis of (evolvable hardware)-based and (reparation balance technology)-based electronic circuit fault self-repair strategy proposed in our preliminary work, the optimal design of rectification circuits (RTCs) in electronic circuit fault self-repair based on global signal optimization is deeply researched in this paper. First of all, the basic theory of RTC optimal design based on global signal optimization is proposed. Secondly, relevant considerations and suitable ranges are analyzed. Then, the basic flow of RTC optimal design is researched. Eventually, a typical circuit is selected for simulation verification, and detailed simulated analysis is made on five circumstances that occur during RTC evolution. The simulation results prove that compared with the conventional design method based RTC, the global signal optimization design method based RTC is lower in hardware cost, faster in circuit evolution, higher in convergent precision, and higher in circuit evolution success rate. Therefore, the global signal optimization based RTC optimal design method applied in the electronic circuit fault self-repair technology is proven to be feasible, effective, and advantageous.

Multiple parametric faults diagnosis for power electronic circuits based on hybrid bond graph and genetic algorithm

Abstract Aiming at the problem to diagnosis multiple parametric faults in power electronic circuits, a new diagnosis framework based on hybrid bond graph (HBG) and genetic algorithm (GA) is presented. Firstly, the circuits are modeled by HBG modeling technique, in which the equivalent models of the key components are considered. Then, a set of residuals equations and a fault signature matrix (FSM) are derived from the HBG model. Each faulty component exhibits their degradation symptoms on residuals equations. Thus, faults can be detected by comparing residuals with fault detection thresholds and isolated based on FSM. Finally, GA method is employed to identify the component faults. The fitness function of GA is constructed by the residuals equations in which the faulty components are contained. Simulation and experiment are carried out to verify the feasibility and effectiveness. The results show that the developed method is applicable to diagnosis both single and multiple parametric faults.

A Discrete Event System approach to On-line Testing of digital circuits with measurement limitation

In the present era of complex systems like avionics, industrial processes, electronic circuits, etc., on-the-fly or on-line fault detection is becoming necessary to provide uninterrupted services. Measurement limitation based fault detection schemes are applied to a wide range of systems because sensors cannot be deployed in all the locations from which measurements are required. This paper focuses towards On-Line Testing (OLT) of faults in digital electronic circuits under measurement limitation using the theory of discrete event systems. Most of the techniques presented in the literature on OLT of digital circuits have emphasized on keeping the scheme non-intrusive, low area overhead, high fault coverage, low detection latency etc. However, minimizing tap points (i.e., measurement limitation) of the circuit under test (CUT) by the on-line tester was not considered. Minimizing tap points reduces load on the CUT and this reduces the area overhead of the tester. However, reduction in tap points compromises fault coverage and detection latency. This work studies the effect of minimizing tap points on fault coverage, detection latency and area overhead. Results on ISCAS89 benchmark circuits illustrate that measurement limitation have minimal impact on fault coverage and detection latency but reduces the area overhead of the tester. Further, it was also found that for a given detection latency and fault coverage, area overhead of the proposed scheme is lower compared to other similar schemes reported in the literature.

A framework for evaluating comprehensive fault resilience mechanisms in numerical programs

As HPC systems approach Exascale, their circuit features will shrink while their overall size will grow, both at a fixed power limit. These trends imply that soft faults in electronic circuits will become an increasingly significant problem for programs that run on these systems, causing them to occasionally crash or worse, silently return incorrect results. This is motivating extensive work on program resilience to such faults, ranging from generic mechanisms such as replication or checkpoint/restart to algorithm-specific error detection and resilience mechanisms. Effective use of such mechanisms requires a detailed understanding of (1) which vulnerable parts of the program are most worth protecting and (2) the performance and resilience impact of fault resilience mechanisms on the program. This paper presents FaultTelescope, a tool that combines these two and generates actionable insights by presenting program vulnerabilities and impact of fault resilience mechanisms in an intuitive way.

Non–Symmetric Finite Networks: The Two–Point Resistance

Abstract An explicit formula for the resistance between two nodes in a network described by non-symmetric Laplacian matrix L is obtained. This is of great advantage eg in electronic circuit fault analysis, where non-linear systems have to be solved repeatedly. Analysis time can be greatly reduced by utilization of the obtained formula. The presented approach is based on the “mutual orthogonality” of the full system of left and right-hand eigenvectors of a diagonalizable matrix L. Simple examples are given to demonstrate the accuracy of this approach to circuit networks

A New Method for Electronic Circuit Fault Knowledge Acquisition Using PSPICE

A new method for electronic circuit fault knowledge automatic generation Using PSpice has been put forward based on summarizing development of the intelligent fault diagnosis technology. A new algorithm of generating fault knowledge automatically has been designed by analysing the structure characteristics of the CIR file. The algorithm of search automatically has been designed by analysing the structure characteristic of the OUT file. The DC fault dictionary method has been improved and the fault order according to the minimum distance will guide the user to remove the fault. In the end, through these technologies, the fault knowledge query system has been empoldered. The feasibility of the proposed method has been proved by experiment results.

COMPLEX NETWORK APPLICATION IN FAULT DIAGNOSIS OF ANALOG CIRCUITS

Fault diagnosis has played an important role in the identification of fault mechanisms and the subsequent successful isolation of faults in electronic circuits. In this paper, we propose a novel procedure for fault diagnosis in analog circuits. We first generate a set of fault patterns from fault simulation, and our main task is to develop a practical description of the way in which these fault patterns interact. Our approach is based on the construction of a complex network that describes the inter-dependence of the various fault patterns. Analysis of this complex network shows that the degree distribution is scalefree-like and the connectivity is small-world. We henceforth identify a small number of fault patterns that are most highly connected (of highest degrees) with other fault patterns. Furthermore, we study the connection between this network of fault patterns and the original circuit, the purpose being to relate the information of the high-degree fault patterns with the physical circuit topology, thus allowing the physical fault locations and circuit elements to be identified. Our proposed approach will find applications in automatic fault diagnosis of large-scale electronic circuits.