Electron Mobility In Si Research Articles

Variable mechanism of electrical impedance for MCT high voltage switch under synergetic action of the mechanical and electric loads

To study the electromechanical coupling effect of Metal Oxide Semiconductor Controlled Thyristor (MCT) high voltage switch under the synergistic action of mechanical load and strong voltage in the actual use of penetrating hard targets and launching, the universal testing machine was used to simulate the overload environment. The rising edge time, falling time and impedance changes in the conduction path of MCT under different stress–strain were tested, respectively. Experimental results showed that the rise time of MCT decreased from 0.08 ms to 0.03 ms when the uniaxial compressive stress increased from 1.20 MPa to 7.3 MPa, and the rising edge time after unloading was 0.04 ms. The falling time had no obvious change with the increase of stress. The total resistance in the path decreased from 833.30 Ω to 564.22 Ω with the increase of strain. The stress–strain of each part of MCT under different uniaxial compressive stress was collected by COMSOL Multiphysics finite element software. Based on the Schrödinger equation, the potential energy operator was established. By introducing the strain Hamiltonian H ε,ν , the E(k)-k model near the minimum value of the conduction band of Si was established by using the k·p perturbation method. Combined with the physical field interface of Schrödinger equation in COMSOL Multiphysics, the valence band structure of Si material under uniaxial strain was studied on the basis of strain Hamiltonian perturbation. The results showed that the 6-degree degenerate valley (Δ6) in the conduction band was split into a 2-degree degenerate valley (Δ2) and a 4-degree degenerate valley (Δ4) due to the stress effect. The strain caused more electrons to occupy the lower Δ4 energy valley, resulting in a decrease in the effective mass of the total conductivity. Therefore, the electron mobility of Si was increased under uniaxial strain. The uniaxial compressive stress could more effectively reduce the curvature radius of valence band top, the effective mass of carriers and the interband scattering between light and heavy hole bands, which was beneficial to improve the hole mobility.

An Empirical Model for Bulk Electron Mobility in Si at Cryogenic Temperatures

An Empirical Model for Bulk Electron Mobility in Si at Cryogenic Temperatures

Phonon-limited electron mobility in Si, GaAs, and GaP with exact treatment of dynamical quadrupoles

We describe a new approach to compute the electron-phonon self-energy and carrier mobilities in semiconductors. Our implementation does not require a localized basis set to interpolate the electron-phonon matrix elements, with the advantage that computations can be easily automated. Scattering potentials are interpolated on dense $\mathbf{q}$ meshes using Fourier transforms and ab initio models to describe the long-range potentials generated by dipoles and quadrupoles. To reduce significantly the computational cost, we take advantage of crystal symmetries and employ the linear tetrahedron method and double-grid integration schemes, in conjunction with filtering techniques in the Brillouin zone. We report results for the electron mobility in Si, GaAs, and GaP obtained with this new methodology.

Low-Temperature RF Plasma Treatment Effect on Junctionless Pd-Al2O3-Ingaas Misfet Operation

The junctionless (JL) device concept for silicon-on-insulator MOSFETs was introduced by Colinge et al. in 2010 [1], demonstrating considerable gains in terms of process simplicity when compared to conventional inversion-mode MOSFETs. The objective of this work is to implement the JL device concept in an In0.53Ga0.47As channel, where the SiO2 insulator in [1] is replaced by a wider bandgap p-type In0.52Al0.48As barrier layer and to investigate the effect of low-temperature RF hydrogen plasma treatment on the main electrical parameters of such devices. The JL device architecture is particularly well suited to III-V channel materials. Firstly, the high doping concentration (Nd) present in the channel of a JL MOSFET is less problematic for In0.53Ga0.47As than it is for Si. Indeed, the bulk electron mobility in Si is ~100 cm2/V·s at Nd = 1×1019 cm-3, while in In0.53Ga0.47As the bulk mobility is ~4,000 cm2/V·s at a similar Nd level. Moreover, the JL architecture circumvents the difficulties associated with the implantation or regrowth techniques generally used to form the source/drain (S/D) regions of III-V inversion-mode MOSFETs. However in order to form a good Ohmic S/D contacts it is necessary to anneal the device at 350-400°C that could lead to diffusion of In atoms into the gate dielectric. In this work low-temperature RF plasma treatment (RFPT) [2] is proposed to improve S/D contacts and enhance the properties of JL MOSFETs. A structure consisting of a 32-nm-thick n- In0.53Ga0.47As (Nd = 2×1018 cm-3) on a 500-nm-thick p-In0.52Al0.48As (Na = 8×1015 cm-3) barrier was grown by metal organic vapour-phase epitaxy (MOVPE) on a p+-InP wafer (Fig. 1 (a)). In order to form a channel for the JL devices, the In0.53Ga0.47As layer was thinned using a 10% H2O2/10% HCl digital wet etching process to achieve channel thicknesses of 24, 20 and 16 nm. A gate enclosed device layout was employed to simplify the fabrication process flow (Fig. 1(b-e)). A surface passivation in 10% (NH4)2S for 30 min was performed before atomic layer deposition (ALD) of an 8.5-nm-thick Al2O3 gate oxide. A Pd gate was formed by e-beam evaporation and lift-off. The Al2O3 on the S/D contact areas was etched in dilute HF. The S/D contact formation was performed by e-beam evaporation of a Au/Ge/Au/Ni/Au stack and lift-off. The RFPT (13.6 MHz) was performed in forming gas (10%H2+90%N2) with additional heating of the sample holder (up to 200°C). Temperature of the samples at the RFPT did not exceed 250°C [2]. Well behaved Id-Vg characteristics measured on the 24-nm-thick In0.53Ga0.47As channel device are shown in Fig. 2. A threshold voltage (VT) of -0.55 V was extracted using the second-derivative method. Scaling the In0.53Ga0.47As channel thickness down to 16 nm improved the subthreshold swing (SS) but degraded the maximum Id and ION/IOFF due to the combined effect of S/D series resistance (RSD) and mobility degradation. As a result, the lowest SS value (115 mV/dec) was extracted on the 16-nm-thick In0.53Ga0.47As channel device and 190 mV/dec - on the 24-nm-thick In0.53Ga0.47As channel one, but the highest ION/IOFF value (1.5×105) was obtained on the 20-nm-thick In0.53Ga0.47As channel device and 2.0×104 - on the 24-nm-thick In0.53Ga0.47As channel one. The gate-to-channel Cgc-Vg characteristic featured a low frequency dispersion near the accumulation region, suggesting a low density of interface traps (Dit) in the upper part of the In0.53Ga0.47As bandgap. Moreover, the conductance analysis yielded low Dit values ranging from 1.5×1012 to 3.5×1012 cm-2×eV-1 from the conductance band edge to midgap, correspondingly. Measurements of RSD on circular transfer length method (CTLM) structures yielded the value of 12 kOhm on the 20-nm-thick In0.53Ga0.47As channel devices and contacts were strongly rectifying. RF plasma treatment with power 0.5 W/cm2 at 150°C resulted in Ohmic SD contact, a strong decrease of RSD down to 45 Ohm (Fig. 3) and increases the ION by two orders of magnitude (Fig. 2). Additionally, SS for the plasma treated devices decreases from 190 mV/dec to 150 mV/dec, and the threshold voltage shifts to positive values by 0.4 V (Fig.2). This is associated, correspondingly, with a decrease of Dit and negative charge in the gate dielectric. The conductance analysis yielded reduction of Dit at midgap down to 1.0×1012 cm-2×eV-1. [1] Colinge J.-P., Lee C.-W., Afzalian A., Akhavan N.D., Yan R., Ferain I., Razavi P., O'Neill B., Blake A., White M., Kelleher A.-M., McCarthy B., Murphy R. Nanowire Transistors Without Junctions. Nature Nanotechnology. Vol. 5, P. 225-229 (2010). [2] Nazarov A.N., Lysenko V.S., Nazarova T.M. Hydrogen Plasma Treatment of Silicon Thin-film Structures and Nanostructured Layers. Semiconductor Physics, Quantum Electronics & Optoelectronics. Vol. 11, P. 101-123 (2008). Figure 1

High Electron and Hole Mobility by Localized Tensile & Compressive Strain Formation Using Ion Implantation and Advanced Annealing of Group IV Materials (Si+C, Si+Ge & Ge+Sn)

Since the 90nm node the industry has been using S/D-stressor for strain-channel formation and increased hole & electron mobility. The S/D-stressor strain-Si method required optimizing the deep S/D junction with the shallow SDE implant junction. PMOS used recess etch eSiGe for p+ S/D tensile strain with precise lateral gate overlap distance control to induce channel compressive strain for increased hole mobility in Si while NMOS n+ S/D compressive strain is formed by deep amorphous implant with carbon and stacking fault dislocation defects that induces channel tensile strain for increased electron mobility in Si. With the switch in transistor design from 2-D planar to 3-D FinFET by the industry at the 22nm and 14/16nm nodes, increasing eSiGe Ge content above 55% has reached it’s limit in strain-Si S/D-stressor of -3GPa for hole mobility improvement therefore requiring higher mobility channel material at 10nm and beyond by using: 1) relaxed >70% SiGe to 100% Ge or 2) compressive strain >50% SiGe to 100% Ge for higher hole mobility. Higher electron mobility requires: 1) relaxed >95% SiGe to 100% Ge, 2) tensile strain-Si on >25% relaxed-SiGe or 3) tensile strain >50% SiGe to 100% Ge. Using CVD epitaxial growth of SiGe and Ge requires thick SRB (strain relaxed buffer) epilayers by blanket or selective epitaxial growth but this results in threading dislocation in the 106 to 109 /cm2 level results in high n+ and p+ junction leakage. The reported targets for NMOS is 2% tensile channel strain of >1.5GPa while for PMOS, 2% compressive channel strain of >-1.5GPa at 7nm node [1]. This paper will review strain-Si and strain-Ge formation by ion implantation and advanced annealing to form tensile and compressive strain channel for improved electron and hole mobility in Group IV materials. Carbon and Si implants was used to form surface tensile strained-channel SiC, GeC and GeSi material while Ge and Sn implants was used to form surface compressive strained-channel SiGe, SiGeSn and GeSn material. Improved hole mobility (µh) by >4x and electron mobility (ue) by >2x have been reported by use of implantstrain formation [2,3]. References 1] R. Kim et al., IEDM-2015, paper 34.1. 2] J. Borland et al., IWJT-2013, paper S4-4, p.49. 3] J. Borland et al., IWJT-2015, paper S2-1, p.12.

Two-band k · p model for Si-(110) electron devices

Carrier transport in Si-(110) surfaces is a topic of growing interest because of its presence in the lateral interfaces of vertical structures, such as FinFETs or tri-gate devices. It has been shown that the parabolic effective mass model cannot explain the experimental behavior of electron mobility in Si-(110) surfaces, and the strongly non-parabolic conduction band structure obtained by more accurate (and complex) methods is needed. A simpler model that can reproduce the required non-parabolic features of conduction band structure is described by a two-band k · p Hamiltonian. In this paper, we show the analytic solution of such a model for a square-well potential and a numerical implementation in a coupled Poisson-Schrödinger solver and one-particle Monte Carlo simulator. The electron mobility calculations are in good agreement with experimental results for bulk MOSFETs and SOI devices.

Electron mobility in silicon and germanium inversion layers: The role of remote phonon scattering

We calculate the electron mobility in Si and Ge inversion layers in single-gate metal-oxide-semiconductor field effect transistors. Scattering with bulk phonons, surface roughness and remote phonons is included in the mobility calculations. Various high-κ dielectric materials are considered for both Si and Ge substrates. Overall, Ge outperforms Si, but in general Ge is more affected by the use of high-κ dielectrics. HfO2 degrades the mobility substantially compared to SiO2 for Si substrates and may prohibitively degrade performance. HfO2 with Ge yields an improvement over Si with a mobility enhancement ≈3× at an electron sheet density of 1×1013 cm−3.

Study of The Transversal Electron Mobility in Heterojunction Bipolar Transistors with Strained SI1−x Gex-Base

ABSTRACTThe effective transversal mobility of the minority carrier electrons in asymmetrically strained p-type Si1−x Gex -layers, grown on a Si (100) substrate, is studied as a function of boron doping concentration and Ge-content x. The experiments are based on the temperature dependence (290 to 400K) of the collector current enhancement of heterojunction bipolar transistors with a pseudomorphic Si1−x Gex-base. The interpretation of these results is based on new insights about the effective density of states in the valence band of these strained layers [1]. We will present first experimental evidence of the theoretical calculations in [1]. From this we will derive then the value of the NcNv -product for the strained Si1−x Gex-alloy. This allows to extract the ratio of the electron mobility in Si and strained Si1−xGex. We found an enhancement of the mobility when the B-doping level is around 1018 cm−3 and 0.08<x<0.16. At higher values of the Ge-content and the doping level, the enhancement is reduced again.

Inversion electron mobility in Si−SiO 2 structures oxidized at low and high temperatures

By measuring the inversion currents, two types of Si−SiO 2 structure are studied with the silicon dioxide grown in dry oxygen (H 2 O below 1 ppm) at two temperatures (850°C and 1050°C). Inversion electron mobility and charges at the Si−SiO 2 interface for both types of oxide are strongly influenced by the oxidation temperature. The degrading effect of low temperature oxidation is explained by a higher level of strain at the Si−SiO 2 interface. It is shown that the low temperature post-oxidation N 2 anneal is insufficient and the electrical properties of low temperature oxide samples are inferior to those of the high temperature oxides.

Temperature dependence of mobility in silicon (100) inversion layers at low temperatures

Electron mobility of Si(100) n-inversion layers in MOSFETs having μ peak (4.2 K) 4000, 6500 and 12000 cm 2/V·s has been measured at temperatures between 1 and 80 K The carrier concentration dependence of the mobility extrapolated to T−0 and the temperature dependent part of the scattering probability are investigated.

Phonon-Limited Electron Mobility in Si(100) Inversion Layer at Low Temperatures

Calculation of electron mobility due to surfon scattering at temperatures 1 ≤ T ≤50 K and electron surface densities 10 12 ≤ N s ≤5 ×10 12 cm -2 indicates, when compared with measurements by Kawaguchi and Kawaji, that the surfon scattering alone cannot explain the temperature dependent part which they extracted.

Carrier concentration dependence and temperature dependence of mobility in silicon (100) N-channel inversion layers at low temperatures

The carrier concentration ( N s ) dependence of electron mobility in Si (100) inversion layers has been measured at temperatures T = 1.5−70K for high- and low-mobility MOSFETs. An extrinsic term is observed in the T-dependent part of the scattering probability, τ −1 T . At T = 4.4 K, τ −1 T depends on N s as N −1.9 s in low mobility samples. In high-mobility samples, τ −1 T increases with increasing N s in high N s region while τ −1 T ∝ N −1.6 s in low N s region. The N s -dependence of τ −1 T becomes weaker with increasing T in both of low- and high-mobility samples. At N s = 3 × 10 12 cm −2, τ −1 T depends on T as T 1.8 in low-mobility samples and τ −1 T ∝ T 2.0 in high- mobility samples at T 5 K.