Electromigration-induced Damage Research Articles

Effect of electromigration on microstructure and properties of CeO2 nanopartical-reinforced Sn58Bi/Cu solder joints

To mitigate the decrease in mechanical performance of Sn58Bi/Cu solder joints resulting from electromigration-induced damage. The CeO2 nanoparticles were incorporated into Sn58Bi solder by a melt-casting method, and their effects on the microstructure and properties of Sn58Bi/Cu solder joints under electromigration were investigated. The study results demonstrate that the addition of 0.125 ~ 0.5 wt% CeO2 nanoparticles refines the eutectic microstructure of Sn58Bi solder alloy. At an addition amount of 0.5 wt%, the composite solder alloy exhibits the maximum tensile strength of 68.9 MPa, which is 37% higher than that of the base solder. CeO2 nanoparticle-reinforced Sn58Bi solder can achieve excellent solderbility with Cu substrates and the joints can significantly inhibit the growth of the anodic Bi-rich layer, which is responsible for electromigration. With the extension of current stressing time, Bi-rich and Sn-rich layer are respectively formed on the anode and cathode in the joints. The intermetallic compound (IMC) layer grows asymmetrically, transitioning from a fan-shaped morphology to a flattened structure at the anode and to a thickened mountain-like morphology at the cathode. Adding the CeO2 nanoparticles helps to mitigate the decrease in mechanical performance caused by electromigration damage during current application to some extent. Over the current stressing period of 288 ~ 480 h, the fracture position shifts from the anodic IMC/Bi-rich interface to the cathodic Sn-rich/IMC interface. The fracture mechanism transitions from a brittle fracture characterized by plate-like cleavage to a ductile–brittle mixed fracture with fine dimples and cleavage.

Effects of Sn grain c-axis on electromigration in Cu reinforced composite solder joints

Sn grain orientation in solder matrix has recently been considered as one of the principal failure contributions in lead-free solder joints. Since β-Sn exhibits high anisotropy, the differences of electromigration behavior of solder joints with various grain orientations are dramatic. With different angle (θ) between the c-axis of Sn grain and the direction of electron flow, the solder joints often demonstrate varying degrees of electromigration-induced damage. The present investigation illustrated significant differences in microstructural features on the surface of Cu reinforced composite solder joints, even with similar angle θ. Two Cu particles reinforced Sn3.5Ag composite solder joints with the similar angle θ of 35° and 40° were selected to investigate the effects of Sn grain c-axis on electromigration under high current stressing for 528 h. A large number of Cu6Sn5 compounds were observed and occupied nearly the whole surface with clear polarization effect in one sample. In contrast, very few Cu6Sn5 were found on the surface of the solder matrix in the other sample after current stressing, and the Cu6Sn5 which was formed after reflow disappeared with subsequent current stressing. Even though polarization effect was not obvious, and the cathode interfacial dissolution was observed on such sample. Systematic study revealed that the angle θ alone was not a sole factor to determine the electromigration damage. It has to be considered along with the coordinate system containing the orientation of the c-axis of the Sn grain, a more dominative factor for the diffusing species.

Study of DC and AC Electromigration Behavior in Eutectic Pb-Sn Solder Joints

In this study, direct current (DC) and alternating current (AC) electromigration experiments were carried out using solder joints with a Cu/eutectic Pb-Sn/Cu joint configuration. During stressing using DC and AC, a fixed current density of 104 A/cm2 was applied to the joints at 150°C. In the joints stressed by DC, electromigration-induced damage occurred, and the corresponding microstructural changes mainly included valley and hillock formation in the solder region, pronounced phase segregation of Pb-rich and Sn-rich domains, asymmetric growth of Cu-Sn intermetallics at the interfaces, and excessive depletion of Cu at the cathode side. In contrast, no significant electromigration was observed after the AC treatments. This was especially true for the treatment with AC frequencies higher than 1 h−1. The dependence of the damage on AC frequency suggests that electromigration in solder joints can be inhibited to a large extent when a proper reverse current is delivered.

Failure mechanism analysis of electromigration dominated damage in TiSi2 nanowires

Electromigration-induced damage has been an important concern in very large scale integrated circuit design for a long time and will be a major road block in the pursuit of nanoelectronics devices and next generation power electronics. In this letter, the failure mechanism analysis on two-terminal TiSi2 nanowire devices was reported. Electromigration dominant mass migration is observed and verified by energy dispersive spectroscopy. The contribution of thermomigration is discussed based on temperature simulation. This work provides useful reference for future devices and the failure analysis on nanostructures.

Optical microscopy imaging method for detection of electromigration: Theory and experiment

AbstractElectromigration is a microscopic phenomenon involving electric field‐induced diffusion, which is very relevant to damage in interconnects. A common method to monitor interconnect degradation is through electrical resistance measurements, which requires direct electrical contacts. It is desirable to develop non‐contact methods to monitor electromigration damage formation. Recently, we have proposed a novel Optical Microscopy Imaging Method (OMIM). Here we provide theoretical proof and additional experimental results. OMIM provides a new method for studying electromigration‐induced damage. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Damages and Microstructural Variation of High-lead and Eutectic SnPb Composite Flip Chip Solder Bumps Induced by Electromigration

The electromigration behavior of the high-lead and eutectic SnPb composite solder bumps was investigated at 150 °C with 5 × 103 A/cm2 current stressing for up to 1711 h. The diameter of the bumps was about 125 μm. The underbump metallization (UBM) on the chip side was sputtered Al/Ni(V)/Cu thin films, and the Cu pad on the board side was plated with electroless Ni/Au. It was observed that damages occurred in the joints in a downward electron flow (from chip side to the substrate side), while those joints having the opposite current polarity showed only minor changes. In the case of downward electron flow, electromigration damages were observed in the UBM and solder bumps. The vanadium in Ni(V) layer was broken under current stressing of 1711 h while it was still intact after current stressing of 1000 h. The electron probe microanalyzer (EPMA) elemental mapping clearly shows that the Al atoms in the trace migrated through the UBM into the solder bump during current stressing. Voids were found in the solder bump near the UBM/solder interface. The Sn-rich phases of the solder bumps showed gradual streaking and reorientation upon current stressing. This resulted in the formation of uniaxial Sn-rich phases in the middle of the solder bump, while the columnar and fibrous Sn-rich phases were formed in the surrounding regions. The formation mechanism of electromigration-induced damage to the UBM structure and solder bump were discussed.

An optical microscopy imaging method for detection of electromigration-induced damage

Electromigration damage is a microscopic phenomenon involving electric field-induced diffusion, which is very relevant to damage in interconnects. Recently, we have developed a novel and useful optical microscopy method with which we can visually observe and record such damage formation during an accelerated stress test. This new non-contact technique provides complementary information to the more traditional probe of electrical resistance.

A thermodynamic model for electrical current induced damage

Electromigration-induced damage, which is in principal an irreversible mass diffusion under high current density, has been a concern for VLSI design for a long time. Miniaturization of electronic device sizes down to nano-scale will make electromigration a concern for all conducting components. This paper uses thermodynamics, statistical mechanics and mass transport (diffusion) principals to propose a model for electromigration process and a damage evolution model to quantify the degradation in microelectronics (and micro electromechanical system) solder joints subjected to high current densities. Entropy production in the system is used as a damage metric. The irreversible thermodynamic damage model utilized in this work has previously been successfully applied to thermo-mechanical fatigue of microelectronic solder joints. In this paper we extend this model to electromigration-induced degradation. Electromigration process is modeled by the atomic vacancy flux (mass diffusion) process. The proposed unified model is compared with several existing analytical and empirical models. A comparison of the damage evolution model proposed in here agrees well with empirical models proposed in the literature.

Electromigration-induced damage in bamboo Al interconnects

Depletion and hillock formation were examined in-situ in a scanning electron microscope (SEM) during electromigration of bamboo Al interconnect segments. Hillocks formed directly at the anode ends of the segments by epitaxial addition of Al at the bottom Al/TiN interface. Depletion occurred nonuniformly from the cathode end and stopped once the distance between the leading void and the hillock reached the critical length for electromigration at the given current density. A modified equation for the drift velocity is proposed, which includes the effect of nonuniform depletion and predicts that interconnects with nonuniform depletion are more reliable than those with uniform depletion.

Direct observation of a critical length effect in dual-damascene Cu/oxide interconnects

Electromigration results have provided clear evidence of a short or “Blech” length effect in dual- damascene, Cu/oxide, multilinked interconnects. The test structure incorporates a repeated chain of Blech-type line elements and is amenable to failure analysis tools such as focused ion beam imaging. This large interconnect ensemble provides a statistical representation of electromigrationinduced damage in the regime where steady-state interconnect stress is manifest. Statistical analysis yields a critical length of 90 μm for interconnects with line width 0.5 μm at j=1.0×106 A/cm2 and T=325 °C.

Effect of current crowding on vacancy diffusion and void formation in electromigration

In multilevel interconnects, current crowding occurs whenever the current changes direction, such as when passing through a via. We propose that in current crowding, the current-density gradient can exert a driving force strong enough to cause excess vacancies (point defects) to migrate from high to low current-density regions. This leads to void formation in the latter. This is a key feature of electromigration-induced damage in very large scale integrated interconnects.

Electromigration proximity effects of two neighboring fast-diffusion segments in single-crystal aluminum lines

In near-bamboo lines, electromigration-induced damage initiates at polygranular clusters which are longer than a critical length and which act as fast-diffusion segments. It has been proposed that two neighboring subcritical clusters can also lead to damage through the interaction of their stress fields. In order to prove the existence of, and to study, such proximity effects, artificial clusters were generated by creating continuous segments of plastic deformation in single-crystal aluminum lines using nanoindentation. Pairs of segments having different separation distances and lengths were made. In situ electromigration tests showed that these segments generated damage in the form of voids and hillocks even when the individual segments were shorter than the critical length. The void growth rate was found to be a function of the separation distance and segment length. A simple analytical model for the electromigration flux in these structures is shown to be consistent with the measured void growth rates. Electromigration characteristics such as the diffusivity, the effective charge, and the critical stress for void formation can be extracted from a comparison between experimental results and model predictions.

Interconnect Failure Mechanism Maps for Different Metallization Materials and Processes

AbstractA tool for simulation of electromigration and electromigration-induced damage, MIT/EmSim, has been used to investigate interconnect reliability, focusing on transitions in failure mechanisms associated with void nucleation, growth, and growth saturation. Conventional scaling of electromigration test results assume that the median time to electromigration-induced failure scales with the current density j to the power −n. The effects of transitions in failure mechanisms have been studied by characterizing the apparent current density exponent. When failure is limited by void nucleation, n=2 scaling is observed, and when failure requires substantial void growth, n=1 scaling is observed. When lines end at diffusion barriers such as W or liner-filled vias, void growth saturates in short lines at low current densities, and, depending on the failure criterion, lines under these conditions can be ‘immortal’. As growth saturates, apparent current density exponents increase above 2. Failure mechanism maps can be constructed to illustrate the failure mechanisms and scaling behavior as a function of line length and current density. Failure maps can be used in accurately scaling test results to service conditions, to suggest layout strategies for optimized circuit reliability, and to assess the reliability of new interconnect materials and structures.

Imaging Spatial Variations in Resistance Along Interconnects

ABSTRACTA non-destructive, non-contact method is described for imaging resistance variations along electrical conductors such as interconnects. In its basic implementation, an intensity modulated laser beam is scanned over the circuit carrying a d.c. current and the voltage induced in the circuit at the modulation frequency is used to vary the intensity of a synchronously scanned display. Resistance variations, such as caused by defects, produce variations in the image thereby identifying their spatial location. The voltage signal depends on a number of parameters including the temperature coefficient of resistivity of the conductor, the power of the incident laser, the absorption coefficient of the conductor and the rate of thermal diffusion to the surroundings. One advantage of the method is that it is possible to produce images of conductors below the surface. Whilst there is a degradation in contrast when imaging sub-surface features, it is still possible to identify and distinguish, for instance, tungsten vias and aluminum interconnects passivated by several microns of dielectric, as well as electromigration-induced damage. Under certain circumstances, other features in the immediate vicinity of the conductors, such as remanent photoresist and decohered interfaces, can also be imaged.

The electromigration short-length effect in Ti-AlCu-Ti metallization with tungsten studs

The electromigration short-length effect has been investigated by testing a two-level structure with Ti-AlCu-Ti stripes and interlevel tungsten (W) stud vias. This investigation represents a complete study of the short-length effect using a technologically realistic test structure. Lifetime measurements and resistance changes as a function of time were used to describe this phenomenon, where the latter approach provides new insights into the electromigration behavior of multilayered metallizations. A linear increase in resistance was followed by a resistance change with time that approached zero. For the same product of current density and stripe length, longer stripes increased in resistance to higher values than shorter stripes. The sigma of the lognormal distribution increased as the current density decreased and/or as the maximum allowed resistance change increased. The lifetime, or t50, at relatively small current densities did not obey Black’s empirical equation. Rather, the lifetime data obeyed a modified version of this equation that includes a critical current density jc as a new parameter. As an alternate approach to quantifying the short-length effect, we propose a novel and practical model for determining jc that focuses on the apparent saturation of the resistance increase with time of the W stud chains. Unlike the modified Black’s model, the resistance saturation approach allows one to estimate lower bound limits of jc. The threshold product, (jL)c, is determined from the modified Black’s model and from the resistance saturation model for stripe lengths of 50, 70, and 100 μm. Both models indicate that jc strongly depends on the fail criterion, or the magnitude of the resistance change, but is independent of temperature in the range 175–250 °C. No evidence was found of a (jL)c below which no electromigration-induced damage occurs.

Mechanisms of Stress-Induced and Electromigration-Induced Damage in Passivated Narrow Metallizations on Rigid Substrates

Narrow, passivated metal lines are generally used as interconnects in VLSI microcircuits at the chip level. In most metals, high electric current densities lead to a mass flow of constituent atoms accompanying the current of electrons. Electromigration (EM) has long been considered an important reliability concern in the semiconductor industry because the current-induced atomic fluxes can give rise to void formation and open circuits, or hillock formation and short circuits between nearby interconnects. The problem is exacerbated because of the continued trend of increasing the density of the devices on the chip. This means that the line widths of the interconnects have been reduced and are now in the submicron range; correspondingly, the current densities have increased and may be as high as 106 A/cm2. Recently, thermal-stress-induced damage in metallizations has also been recognized as an important reliability concern, perhaps of the same gravity as EM. Thermal stresses in the metallizations are caused by the different thermal expansion coefficients of the metal and the substrate. Stress-induced void and hillock formation are the main causes of in terconnect failures before service. More recently, concern has been growing that thermal stresses or thermal-stress-induced voids may enhance the subsequent electromigration damage during the service life of the microchips.For simplicity, this article addresses the case of pure aluminum metallizations on oxidized silicon substrates. However, much of what is said applies to other metal-rigid substrate systems as well, most notably to various aluminum and copper-based metallizations on ceramic substrates. The present treatment emphasizes void formation and growth in the metallizations during nd after cooldown from elevated temperatures, or those due to electromigration in service or testing conditions. Many of the mechanisms we explain are also applicable to hillock formation under compressive stresses, whether due to EM or thermal cycles during manufacturing.

Quantitative Analysis of Electromigration-Induced Damage in Al-Based Interconnects

Electromigration in metal interconnect lines produces sites of damage, such as voids, hillocks and whiskers, which by definition are the sites of flux divergence in the lines. Detailed observations of damage volume and morphology, especially in relation to the local microstructure, may yield vital information about the processes which produce the damage and ultimate failure in the interconnects. We present fractographic measurements of void volumes and the spacing between voids and corresponding hillocks in Al and Al-2% Cu interconnects which have been electromigration tested until failure. It is shown that the void density as well as the shape of failure voids depend on the current density. Further it is found that the distribution of the spacings between voids and corresponding hillocks changes as a function of current density.

Microstructural Analysis of Electromigration-Induced Voids and Hillocks

ABSTRACTInterconnect reliability is of continuing concern in modem VLSI circuits. This work presents analyses of the microstructural detail in electromigration-induced damage in Al and Al-Cu unpassivated interconnects. Such failure analysis is crucial for the characterization of the fundamental processes responsible for failure. Results, via TEM, SEM and focussed-ion beam techniques, suggest possible second phase precipitate-void growth interactions, show slit-like open circuit failures in narrow interconnects, and illustrate the microstructures of hillocks and whiskers formed during accelerated electromigration testing. These results are discussed in terms of existing models for electromigration failure processes and lifetimes. The results are further intended to suggest mechanisms for future modelling and to direct the design of more reliable interconnect material systems.

Morphology of electromigration-induced damage and failure in Al alloy thin film conductors

Distinct morphologies of electromigration-induced voids and failures are shown for Al, Al-2%Cu, and Al-2%Cu-l% Si narrow (1–6 µm) unpassivated thin film conductors. SEM and TEM images typically show large non-fatal voids and narrow slit-like open circuit failures for all film conditions and accelerated test conditions. Evidence for transgran-ular slit failures is shown for 1.33 µm wide conductors. A simple model for void growth is presented which accounts for the void morphologies seen. The observed morphologies and the results of void growth modelling suggest that slit voids nucleate after other voids and rapidly produce failure. These conclusions are discussed in terms of ‘classical’ models for electromigration failure processes and resistance and noise power monitoring techniques.

Early gate failures in biased GaAs field effect transistors from electromigration-induced damage superimposed on kirkendall voids

Electrical gate failures in GaAs field effect transistors (FETs) were analysed. In the analysis, the TiPt phase growth during high temperature storage was estimated using growth rates which were calculated at 100, 325 and 400°C from a (time) 1 2 dependence. The calculations reveal volume changes by -6.36% and -6.325% as a result of the formation of the TiPt and Ti 3Pt phases respectively. The volume changes and lattice mismatch give rise to mechanical strains causing metallurgical failure of the Ti/Pt layers and consequently the formation of AuAl intermetallics. Compressional stresses in the films relax through the formation of hillocks. In biased FETs a new failure mechanism, electromigration-induced damage superimposed on Kirkendall voids as a result of current crowding, occurs when the current density is as low as 1 × 10 4 A cm −2 and gives rise to early gate failures.