Electrical Gate Oxide Thickness Research Articles

Impact of Gate Process Technology on EOT of HfO2 Gate Dielectric

AbstractTo facilitate CMOS scaling beyond the 65 nm technology node, high-permittivity gate dielectrics such as HfO2 will be needed in order to achieve sub-1.3nm equivalent oxide thickness (EOT) with suitably low gate leakage, particularly for low-power applications. Polycrystalline silicon-germanium (poly-SiGe) is a promising gate material because it is compatible with a conventional CMOS process flow, and because it can yield significantly lower electrical gate-oxide thickness as compared with poly-Si. In this paper, the effects of the gate material (Si vs. SiGe) and gate deposition rate on EOT and gate leakage current density are investigated. Poly-Si0.75Ge0.25 gate material yields the lowest EOT and is stable up to 950°C for 30 seconds, providing 2 orders of magnitude lower leakage current compared to poly-Si gate material. A faster gate deposition rate (achieved by using S2H6 instead of SiH4 as the gaseous Si source) is also effective for minimizing the increases in EOT and leakage current with high-temperature annealing.

Sub-60-nm quasi-planar FinFETs fabricated using a simplified process

N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. The drive current for typical devices is found to be above 500 /spl mu/A//spl mu/m (or 1 mA//spl mu/m, depending on the definition of the width of the double-gate device) for V/sub g/-V/sub t/=V/sub d/=1 V. The electrical gate oxide thickness in these devices is 21 /spl Aring/, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness.

Characterization of inversion-layer capacitance of holes in Si MOSFET's

Inversion-layer capacitance (C/sub inv/) in p-channel Si MOSFET's is studied experimentally and theoretically with emphasis on the surface carrier concentration (N/sub s/) dependence, which is important in the quantitative description and the physical understanding. The amount of C/sub inv/ and its influence on the gate capacitance are compared between electron and hole inversion layers. It is experimentally verified that, under same physical thickness of gate oxides, the electrical gate oxide thickness, determined from the gate capacitance, is larger for inversion-layer holes than that for inversion-layer electrons, because of smaller values of C/sub inv/ for inversion-layer holes. Self-consistent Poisson-Schrodinger calculation of C/sub inv/ is performed on basis of the approximation of a constant effective mass and is compared with the experimental C/sub inv/. It is found that the calculation using the effective masses at the valence band edge can accurately represent the experimental results over a whole range of N/sub s/.