Electrical Characteristics Of MOS Capacitors Research Articles

Effect of oxide and interface traps on electrical characteristics of post-deposition annealed HfSiO4/n-Si structures

This study presents detailed results on the modifications in chemical composition, defective bonds, crystal properties based on x-ray photoelectron spectroscopy (XPS) depth profiles and x-ray diffraction of post-deposition annealed HfSiO4/Si structure. It also leads to a link to defect centers and their effect on the electrical characteristics of MOS capacitors. The HfSiO4 films were deposited on n-Si wafers by RF magnetron sputtering and annealed at room temperature (RT), 300 °C, 700 °C, 900 °C, 1100 °C under N2 ambient. That the atomic concentration values of each element in the oxide did not change significantly depending on the annealing temperature showed that the film was deposited with high homogeneity. It was determined that the shift direction of the binding energies of Hf 4f and O 1s XPS spectra were related to the bonding preference of oxygen rather than its concentration. The increase in Hf–M and Hf–Si oxygen defective bonds decreased the binding energy of the XPS spectra. It was determined from the XPS analyses of amorphous films that Hf–Si and Si–Si oxygen defective bonds may cause the positive charge trapping, resulting in the highest negative charge trapping/positive effective oxide charge density () in the 300 °C-MOS capacitor. It was determined that Hf–Hf oxygen defective bonds may be the precursors of negative charge trapping. Interface states only contributed to the dielectric constant (k) in the RT-MOS capacitor. The (barrier height) values showed that the efficiency of acceptor-like and donor-like interface states changes depending on the frequency.

Influences of coexisting O2 in H2O-annealing ambient on thermal oxidation kinetics and MOS interface properties on 4H–SiC (1–100)

On 4H–SiC (1–100) m-face substrate, the process design of SiO2 growth by a conventional thermal oxidation accompanied with post-oxidation annealing (POA) in H2O ambient was investigated, especially focusing on the impact of O2 or H2O composition in the POA ambient. From the oxidation kinetics study, the surface on m-face was found to be more reactive to O2 than to H2O in thermal oxidation at 1100–1300 °C, while co-existence of both oxidants resulted in the highest oxide growth rate. As for the electrical characteristics of MOS capacitors, it was clarified that the POA process in H2O with low O2 concentration ambient was beneficial in interface trap density (Dit) reduction on m-face, even though the observed competitive relationship between Dit and flat-band voltage (VFB) instability made it challenging to simultaneously suppress both of those two parameters on m-face. High O2 concentration POA ambient worsened both of those two parameters, suggesting additional defects being easily introduced on m-face by the coexisting O2 in the POA ambient.

A detailed study on frequency dependent electrical characteristics of MOS capacitors with dysprosium oxide gate dielectrics

Frequency dependent electrical characteristics of Al/Dy2O3/p-Si/Ag MOS capacitors have been systematically investigated incorporating interfacial chemical structures of the capacitors to specify where interface state signals arise from. The results show that capacitance (C) increases with decreasing in the applied voltage frequency due to the response time dependency of the interface states. Conductance (G) curves have a single peak at the relatively high frequencies as expected. Interestingly, the G curves exhibit two distinct peaks at 400 kHz and lower frequencies. These G peaks are associated with acceptor-like interface (Dit,ac) and donor-like interface (Dit,dn) states. Electrochemical analysis has also depicted that non-stoichiometric DySiOx and SiOx bonds are present at the interface between Dy2O3/Si gate stack. Owing to interactions between mobile charge carriers and possible defect sites present at the DySiOx and SiOx, the Dit,ac and Dit,dn signals have been observed at G curves. In addition, the C hysteresis loop widths decrease with decreasing in the voltage frequencies due to opposite polarity and response time dependencies of the Dit,ac and Dit,dn states. The oxide, interface and border trap densities of capacitors exhibit slight frequency variations and their orders are comparable with device used in the state of the art microelectronics technologies. On the other hand, barrier potential varies from 0.97 eV to 1.136 eV depending on the voltage frequencies. Leakage current density was found to be 1.61 × 10−7 Acm−2 at −1 V and Fowler–Nordheim tunneling mechanism dominates the leakage current conduction. Considering to these results, it can be concluded that the Dy2O3 shows promising dielectric and insulating behavior for the application in future microelectronics technology.

Real-time and on-site γ-ray radiation response testing system for semiconductor devices and its applications

The construction of a turnkey real-time and on-site radiation response testing system for semiconductor devices is reported. Components of an on-site radiation response probe station, which contains a 1.11GBq Cs137 gamma (γ)-ray source, and equipment of a real-time measurement system are described in detail for the construction of the whole system. The real-time measurement system includes a conventional capacitance–voltage (C–V) and stress module, a pulse C–V and stress module, a conventional current–voltage (I–V) and stress module, a pulse I–V and stress module, a DC on-the-fly (OTF) module and a pulse OTF module. Electrical characteristics of MOS capacitors or MOSFET devices are measured by each module integrated in the probe station under continuous γ-ray exposure and the measurement results are presented. The dose rates of different gate dielectrics are calculated by a novel calculation model based on the Cs137 γ-ray source placed in the probe station. For the sake of operators’ safety, an equivalent dose rate of 70nSv/h at a given operation distance is indicated by a dose attenuation model in the experimental environment. HfO2 thin films formed by atomic layer deposition are employed to investigate the radiation response of the high-κ material by using the conventional C–V and pulse C–V modules. The irradiation exposure of the sample is carried out with a dose rate of 0.175rad/s and ±1V bias in the radiation response testing system. Analysis of flat-band voltage shifts (ΔVFB) of the MOS capacitors suggests that the on-site and real-time/pulse measurements detect more serious degradation of the HfO2 thin films compared with the off-site irradiation and conventional measurement techniques.

Characterization of interface defects in BiFeO3 metal–oxide–semiconductor capacitors deposited by radio frequency magnetron sputtering

In this work, we study the structural and electrical properties of BiFeO3 MOS capacitors with a special focus on the oxide–semiconductor interface for gate dielectric applications. For this purpose BiFeO3 thin films with a thickness of 300 nm were deposited on p-type Si (100) substrates at 0 °C by RF sputtering. Half of the films were annealed at 550 °C for 30 min in atmospheric environment while the other half were kept as-deposited. XRD and SEM measurements were performed for both samples for structural characterization. MOS capacitors were fabricated by evaporation technique using Al from samples. For electrical characterizations of MOS capacitors, capacitance–voltage (C–V), conductance–frequency (Gp/ω–F) and leakage current density–voltage (J–V) measurements were performed. The XRD analyses show that BiFeO3 thin films are polycrystalline with some impurity phases, which influence the electronic device properties. The formation of crystallization is confirmed by SEM measurements. Debye length, barrier height and flat band voltages showed variations due to the frequency dependent charges, partially originating from interface defects, in the device structure. Therefore ignoring effects of frequency dependent charges can lead to significant errors in the analysis of electrical characteristics of MOS capacitors. Moreover, the obtained results from analyses of C–V, Gp/ω–F and J–V characteristics of annealed samples depict that all measured and calculated parameters are of the same order for novel MOS devices. Hence, the BiFeO3 dielectric layer in fabricated MOS devices exhibits a stable insulation property for gate dielectric applications.

2 MeV electron irradiation effects on the electrical characteristics of MOS capacitors with ALD Al2O3 dielectrics of different thickness

The effects of 2MeV electron irradiation on the electrical characteristics of atomic layer deposited layers of Al2O3 with different thickness are evaluated by using metal–oxide–semiconductor capacitors with a dielectric physical thickness ranging from 2.8nm to 11.6nm. The capacitance–voltage and current–voltage characteristics of the capacitors are analysed as a function of electron irradiation. A progressive radiation-induced positive charge trapping and increase of the leakage current with electron fluence is observed for the thickest layers subjected to electron irradiation. However, the effects are significantly lower or even negligible for the thinnest Al2O3 films.

(Invited) Study on Charge Storage and Optical Response of Hybrid Nanodots Floating Gate MOS Devices for Their Optoelectronic Application

We have designed and fabricated hybrid nanodots structures, in which Si quantum dots (QDs) and either Ni-silicide or Pt-silicide nanodots (NDs) are stacked with ultrathin SiO2 interlayer, as a novel functional floating gate (FG) to satisfy both multiple valued capability and large capacity on charge storage. Multiple-step charge injection to sililcide NDs through discrete energy states in Si-QDs and stable storage of many charges in deep potential wells in silicide NDs have been confirmed from electrical characteristics of MOS capacitors and transistors measured at room temperature. A unique optical response of the hybrid NDs FG to near-infrared light irradiation, which is caused by the transfer of photo-excited electrons from silicide NDs to Si-QDs, has also been demonstrated.

Experimental evidence and modeling of two types of electron traps in Al2O3 for nonvolatile memory applications

Al2O3-based dielectrics are currently considered as promising materials to use in nonvolatile memories. The electron trap density in this material is much higher than in conventional SiO2, being their characteristics critical for the application. Conventional capacitance-voltage (C-V) techniques were used to study the main effects of the electron traps on the electrical characteristics of MOS capacitors with atomic layer deposited Al2O3 as insulating layer. More detailed information about the trapping kinetics was obtained through the study of the constant capacitance voltage transient. Two different types of traps were found. One is responsible for the instabilities observed in C-V measurements, the other has characteristic trapping times three orders longer. A physical model is presented to explain the observed trapping kinetics exhibiting good agreement between experiments and simulations. The energy levels of the studied traps were determined at 2.2 and 2.6 eV below the Al2O3 conduction band, with densities of 2.9 × 1018 cm−3 and 1.6 × 1018 cm−3, respectively.

Behavior of Ta2O5-Si Capacitors with Different Gate Electrode under Constant Current Stress

The electrical characteristics of MOS capacitors with Ta2O5 as oxide and with different gate electrodes(Al, Au, W, TiN) are investigated using high frequency capacitance-voltage (C-V) and current–voltage (I-V)measurements. The influence of deposition techniques of gate electrode (reactive sputtering and evaporation)and the type of electrode material (different work functions) are observed. Charged trapping properties werestudied by measuring the gate voltage shift due to trapped charge generation in order to investigate theresponse to constant current stress (CCS) under various current/time conditions at room temperature. Theresults showed that the presence of pre-existing electron traps leads the changes of time dependent voltageduring gate injected CCS in the initial stage, followed by the slow positive charge build-up, same for all thestructures and characteristic for this oxide. Gate-induced defects due to ther rate of reaction of gate electrodewith the oxide are responsible for different behavior of the structures with different gate electrodes, observedin the initial stage of CCS. The Au-gated devices appear to be the most susceptible to the constant currentstress degradation. They also have highest values of capacitance and lowest leakage currents. Key Words: Gate electrode; Dielectric properties; Oxides; Constant current stress

Comprehension of Postmetallization Annealed MOCVD-TiO2on(NH4)2STreated III-V Semiconductors

The electrical characteristics of TiO2films grown on III-V semiconductors (e.g., p-type InP and GaAs) by metal-organic chemical vapor deposition were studied. With (NH4)2S treatment, the electrical characteristics of MOS capacitors are improved due to the reduction of native oxides. The electrical characteristics can be further improved by the postmetallization annealing, which causes hydrogen atomic ion to passivate defects and the grain boundary of polycrystalline TiO2films. For postmetallization annealed TiO2on (NH4)2S treated InP MOS, the leakage current densities can reach2.7×10−7and2.3×10−7 A/cm2at±1 MV/cm, respectively. The dielectric constant and effective oxide charges are 46 and1.96×1012 C/cm2, respectively. The interface state density is7.13×1011 cm−2eV−1at the energy of 0.67 eV from the edge of valence band. For postmetallization annealed TiO2on (NH4)2S treated GaAs MOS, The leakage current densities can reach9.7×10−8and1.4×10−7at±1 MV/cm, respectively. The dielectric constant and effective oxide charges are 66 and1.86×1012 C/cm2, respectively. The interface state density is5.96×1011 cm−2eV−1at the energy of 0.7 eV from the edge of valence band.

Effect of thin Si insertion at metal gate/high- k interface on electrical characteristics of MOS device with La 2O 3

The effect of a thin Si layer insertion at W/La 2O 3 interface on the electrical characteristics of MOS capacitors and transistors is investigated. A suppression in the EOT increase can be obtained with Si insertion, indicating the inhibition of diffusion of oxygen atoms into La 2O 3 layer by forming an amorphous La-silicate layer at the W/La 2O 3 interface. In addition, positive shifts in V fb and V th caused by Si insertion implies the formation of amorphous La-silicate layer at the top of La 2O 3 dielectrics reduces the positive fixed charges induced by the metal electrode. Consequently, a large improvement in mobility has been confirmed for both at peak value and at high E eff of 1 MV/cm with Si inserted nFETs. Although a degradation trend on EOT scaling has been observed, the insertion of thin Si layer is effective in pushing the scaling limit.

Electrical characteristics of MOS capacitors with HfTiON as gate dielectric

HfTiN film was deposited by co-reactive sputtering and then was annealed in different gas ambients at temperature of 650 °C for 2 min to form HfTiON film. Capacitance-voltage and gate-leakage characteristics were investigated. The N2O-annealed sample exhibited small interface-state and oxide-charge densities, and enhanced reliability, which was attributed to the fact that nitridation could create strong Si⊀N bonds to passivate dangling Si bonds and replaced strained Si-O bonds, thus forming a hardened dielectric/Si interface with high reliability. As a result, it is possible to prepare high-quality HfTiON gate dielectric of small-scaling CMOS devices in the industry-preferred N2O environment.

Simulation of the electrical characteristics of MOS capacitors on strained‐silicon substrates

AbstractIn this work, we analyze the electrical characteristics of MOS capacitors fabricated on strained silicon substrates using the commercial software Taurus/Synopsis. The effect of various parameters such as Germanium concentration in the Si1–xGex virtual substrate, thickness of the strained‐Silicon layer, oxide thickness, fixed charge and interface trapped charge on capacitance – voltage characteristics is examined. Experimental data are compared with simulation results. A strong influence of the s‐Si/SiGe heterostructure and its proximity to the s‐Si/SiO2 on the electrical characteristics of the system exists. Oxide charge inserted into simulation in order to fit experimental data shows an increase of charge with decreasing s‐Si thickness. The effect of interface traps on simulated C‐V characteristics is identical when traps are situated in the s‐Si/SiO2 or the s‐Si/SiGe interface. When increasing the thermal budget by increasing the post oxidation annealing time, the decrease of the hump phenomenon on the C‐V curves can be attributed to the Germanium diffusion, according to simulation. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

SiC MOSFETs with thermally oxidized Ta 2Si stacked on SiO 2 as high- k gate insulator

In this paper, we compare the electrical characteristics of MOS capacitors and lateral MOSFETs with oxidized Ta 2Si (O-Ta 2Si) as a high- k dielectric on silicon carbide or stacked on thermally grown SiO 2 on SiC. MOS capacitors are used to determine the dielectric and interfacial properties of these insulators. We demonstrate that stacked SiO 2/O-Ta 2Si is an attractive solution for passivation of innovative SiC devices. Ta 2Si deposition and oxidation is totally compatible with standard SiC MOSFET fabrication materials and processing. We demonstrate correct transistor operation for stacked O-Ta 2Si on thin thermally grown SiO 2 oxides. However the channel mobility of such high- k MOSFETs must be improved investigating the interface properties further.

MOS Capacitor Characteristics of 3C-SiC Films Deposited on Si Substrates at 1270°C

ABSTRACTSiC films were deposited on Si substrate by low pressure hot-wall CVD using C3H8 (5% in H2)-SiH4 (2.5% in H2)-H2 gas system at 1270°C and 1370°C. In this paper, we compare the electrical characteristics of MOS capacitors fabricated on the 3C-SiC films grown at high and low temperatures, 1370°C and 1270°C, respectively. Although the cross-sectional TEM images indicate similar micro-structural quality of the SiC/Si interface for both temperatures, a quicker elimination rate of stacking faults with increasing thickness was observed in the films grown at 1370°C. Rocking curves from XRD measurements also indicate better crystallinity of the films grown at 1370°C. On the other hand, atomic force microscopy shows that the average surface roughness reduces with the reduction in growth temperature. MOS capacitors were made on films grown at both temperatures and characterized by high-frequency capacitance-voltage (HFCV), conductance-voltage (G-V), and current-voltage (I-V) measurements at room temperature. The MOS capacitors fabricated on both films exhibit good and almost identical C-V characteristics. Measurements of current-voltage characteristics in accumulation region showed smaller leakage for the film deposited at 1270°C. It is concluded that the decrease of the deposition temperature from 1370°C to 1270°C does not bring any remarkable negative impact on the interface properties of fabricated MOS capacitors.

Characterization of Electronic Charged States of Si-Based Quantum Dots and Their Application to Floating Gate Memories

Si quantum dots (Si-QDs) with and without Ge core were prepared on thermally-grown SiO2 in a self-assembling manner by controlling the early stages of LPCVD. The surface potential changes in individual dots caused by charging or discharging of one electron or a few as were evaluated by using a AFM/Kelvin probe technique. The influence of phosphorous doping to Si-QDs on their electron charging and discharging characteristics was also been studied. Electrical characteristics of MOS capacitors and nMOSFETs with Si-QDs floating gates confirm multiple-step charging to and discharging from the Si-QDs floating gate at room temperature. From the temporal changes in the drain current with gate voltage switching, it is suggested that the change in the electron distribution in the Si-QDs floating gate play an important role to trigger the transition from a metastable charged state to the next charged state.

Three-dimensional integration: technology, use, and issues for mixed-signal applications

Three-dimensional (3-D) integration provides opportunities in large-scale integration of mixed-signal and general system-on-chip applications with improved performance, through increased density and mixing of different active and passive technologies. This paper reports a novel low-thermal-budget 3-D fabrication technique-multilayers with buried structures (MLBS) and an analysis of its applicability to mixed-signal integration. The MLBS technique uses a low temperature of 450/spl deg/C to transfer a single-crystal silicon layer over a processed wafer consisting of buried in-plane and out-of-plane interconnects obtained through a dual Damascene process. Devices can continue to be processed on this transferred layer. Electrical characteristics of MOS capacitors (D/sub it/=4.7/spl times/10/sup 10/ cm/sup -2/ eV/sup -1/) and 3-D integrated planar CMOS transistors (3-D CMOS), fabricated using MLBS, are consistent with integration requirements. Our analog analysis includes an investigation of thermal effects important to analog applications with continuous operation of transistors in forward active bias, as well as of the coupling isolation derived from use of a ground-plane. Use of high density local interconnectivity improves the thermal properties of 3-D CMOS over that of silicon-on-insulator, and use of a ground plane is shown to lead to an improvement of better than 8 dB in coupling isolation.

Thin fluorinated gate dielectrics grown by rapid thermal processing in O/sub 2/ with diluted NF/sub 3/

The authors report the application of rapid thermal processing (RTP) to the fabrication of ultrathin ( approximately 10 nm) high-quality fluorinated oxides in O/sub 2/+NF/sub 3/ (100 ppm diluted in N/sub 2/). NF/sub 3/ was used as the F source gas and was introduced either prior to rapid thermal oxidation (RTO) or with O/sub 2/ during the initial stage of RTO. The oxidation rate was enhanced because of the presence of NF/sub 3/. In addition, F depth profiles in fluorinated oxides were dependent upon the process conditions. The electrical characteristics of MOS capacitors have been studied and correlated with the chemical properties. The initial interface state density (D/sub t/) was found to decrease with F incorporation. The results suggest that the interfacial F incorporation plays a major role in determining the interface hardness for both hot-electron and radiation damages. >

MOS characteristics of fluorinated gate dielectrics grown by rapid thermal processing in O/sub 2/ with diluted NF/sub 3/

Rapid thermal processing (RTP) was applied to the fabrication of the ultrathin ( approximately 10 nm) high-quality fluorinated oxides in O/sub 2/+NF/sub 3/. NF/sub 3/ (diluted in N/sub 2/) was used as the F source gas and was introduced either prior to rapid thermal oxidation (RTO) or with O/sub 2/ during the initial stage of RTO. The electrical characteristics of MOS capacitors have been studied and correlated with the chemical properties. It was found that SiO/sub 2/ with a small amount of F incorporated shows reduced interface state generation under F-N injection, whereas excessive F incorporation is detrimental.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Blocking of silicon oxidation by low-dose nitrogen implantation

The oxidation characteristics of silicon implanted with a low dose of nitrogen (1–3×1015cm−2) have been studied for dry oxidation conditions at 1020°C. The wafers were subjected to a pre-oxidation annealing. Complete inhibition of the oxide growth occurs in the initial stage of oxidation, while the oxidation rate for prolonged oxidation is identical to that for pure silicon. The oxidation resistance increases with the implantation dose. The resistance is attributed to the formation of a nitrogen-rich surface film during annealing. This layer, which consists of only a few monolayers, is presumably composed of oxynitride. The electrical characteristics of MOS capacitors formed on implanted wafers show that the interface state density is not significantly increased by the low-dose N implantation.