Efficient Use Of Hardware Resources Research Articles

3D DFT by block tensor-matrix multiplication via a modified Cannon's algorithm: Implementation and scaling on distributed-memory clusters with fat tree networks

A known scalability bottleneck of the parallel 3D FFT is its use of all-to-all communications. Here, we present S3DFT, a library that circumvents this by using point-to-point communication – albeit at a higher arithmetic complexity. This approach exploits three variants of Cannon's algorithm with adaptations for block tensor-matrix multiplications. We demonstrate S3DFT's efficient use of hardware resources, and its scaling using up to 16,464 cores of the JUWELS Cluster. However, in a comparison with well-established 3D FFT libraries, its parallel efficiency and performance were found to fall behind. A detailed analysis identifies the cause in two of its component algorithms, which scale poorly owing to how their communication patterns are mapped in subsets of the fat tree topology. This result exposes a potential drawback of running block-wise parallel algorithms on systems with fat tree networks caused by increased communication latencies along specific directions of the mesh of processing elements.

Digital Division Algorithms for Efficient Execution on Integrated Circuits

In this paper, we analyse division algorithms for use on chips and propose the implementation of an optimal divider for these chips. By “optimal”, we refer to an algorithm that meets the following criteria: space efficiency – which involves minimizing resource utilization on the IC’s die area; speed efficiency – the algorithm's processing time (measured in n clock cycles); power efficiency – power consumption of the divider; implementation time – time for implementation of the algorithm using HDL. The chosen algorithm should strike a balance between space efficiency and processing speed, ensuring the efficient use of hardware resources while delivering swift computational results. The ultimate goal is to create a division module that aligns seamlessly with the integrated circuit's architecture, catering to computational efficiency and resource constraints.

Quantification of Regression Test Suite Execution Time in Parallel Execution Setup with Weighted Test Suite Split Algorithm

Regression test suite execution time study focus is essentially on two aspects. They are execution time reduction and making effective use of available hardware resources and manpower. This paper investigates how the regression test suite can be split into subsets to make use of parallel execution across several machines with identical execution speeds and asymmetrical execution speeds. In the symmetrical execution speed setup, long test execution time test cases are evenly distributed across all the hardware machines. However, in asymmetrical execution speed machines, more test cases are distributed to speed machines to make efficient use of hardware resources. In all the situations where there is automation tool to execute the individual test cases of test suite this approach can be employed to make effective use of hardware resources and to keep the execution time within bounds. The Algorithms can also be used in situations where there are queues involved and serial, fixed time service takes place for each of the entity being served.

Quantification of Regression Test Suite Execution Time in Parallel Execution Setup with Weighted Test Suite Split Algorithm

Regression test suite execution time study focus is essentially on two aspects. They are execution time reduction and making effective use of available hardware resources and manpower. This paper investigates how the regression test suite can be split into subsets to make use of parallel execution across several machines with identical execution speeds and asymmetrical execution speeds. In the symmetrical execution speed setup, long test execution time test cases are evenly distributed across all the hardware machines. However, in asymmetrical execution speed machines, more test cases are distributed to speed machines to make efficient use of hardware resources. In all the situations where there is automation tool to execute the individual test cases of test suite this approach can be employed to make effective use of hardware resources and to keep the execution time within bounds. The Algorithms can also be used in situations where there are queues involved and serial, fixed time service takes place for each of the entity being served.

Neuromorphic Time-Multiplexed Reservoir Computing With On-the-Fly Weight Generation for Edge Devices.

The human brain has evolved to perform complex and computationally expensive cognitive tasks, such as audio-visual perception and object detection, with ease. For instance, the brain can recognize speech in different dialects and perform other cognitive tasks, such as attention, memory, and motor control, with just 20 W of power consumption. Taking inspiration from neural systems, we propose a low-power neuromorphic hardware architecture to perform classification on temporal data at the edge. The proposed architecture uses a neuromorphic cochlea model for feature extraction and reservoir computing (RC) framework as a classifier. In the proposed hardware architecture, the RC framework is modified for on-the-fly generation of reservoir connectivity, along with binary feedforward and reservoir weights. Also, a large reservoir is split into multiple small reservoirs for efficient use of hardware resources. These modifications reduce the computational and memory resources required, thereby resulting in a lower power budget. The proposed classifier is validated for speech and human activity recognition (HAR) tasks. We have prototyped our hardware architecture using Intel's cyclone-10 low-power series field-programmable gate array (FPGA), consuming only 4790 logic elements (LEs) and 34.9-kB memory, making it a perfect candidate for edge computing applications. Moreover, we have implemented a complete system for speech recognition with the feature extraction block (cochlea model) and the proposed classifier, utilizing 15 532 LEs and 38.4-kB memory. By using the proposed idea of multiple small reservoirs along with on-the-fly generation of reservoir binary weights, our architecture can reduce the power consumption and memory requirement by order of magnitude compared to existing FPGA models for speech recognition tasks with similar complexity.

Implementation and Optimization of Image Processing on the Map of SABRE i.MX_6

Vision relieves humans to understand the environmental deviations over a period. These deviations are seen by capturing the images. The digital image plays a dynamic role in everyday life. One of the processes of optimizing the details of an image whilst removing the random noise is image denoising. It is a well-explored research topic in the field of image processing. In the past, the progress made in image denoising has advanced from the improved modeling of digital images. Hence, the major challenges of the image process denoising algorithm is to advance the visual appearance whilst preserving the other details of the real image. Significant research today focuses on wavelet-based denoising methods. This research paper presents a new approach to understand the Sobel imaging process algorithm on the Linux platform and develop an effective algorithm by using different optimization techniques on SABRE i.MX_6. Our work concentrated more on the image process algorithm optimization. By using the OpenCV environment, this paper is intended to simulate a Salt and Pepper noisy phenomenon and remove the noisy pixels by using Median Filter Algorithm. The Sobel convolution method included and used in the design of a Sobel Filter and then process the image following the median filter, to achieve an effective edge detection result. Finally, this paper optimizes the algorithm on SABRE i.MX_6 Linux environment. By using algorithmic optimization (lower complexity algorithm in the mathematical sense, using appropriate data structures), optimization for RISC (loop unrolling) processors, including optimization for efficient use of hardware resources (access to data, cache management and multi-thread), this paper analyzed the different response parameters of the system with varied inputs, different compiler options (O1, O2, or O3), and different doping degrees. The proposed denoising algorithm shows the meaningful addition of the visual quality of the images and the algorithmic optimization assessment.

A Novel Macroblock-Level Filtering Upsampling Architecture for H.264/AVC Scalable Extension

The scalable extension of the H.264/AVC standard, also called H.264/AVC SVC standard or simply SVC standard uses spatial upsampling in the spatial scalability modes. This work presents a novel upsampling architecture designed for operation at macroblock level and dyadic upsampling ratio with QVGA as the base layer resolution and VGA as the enhancement resolution.The adoption of a macroblock-level solution translates into a more efficient use of hardware resources with savings of approximately 25% in the number of ALUTs and DLRs and using about two hundred times less memory bits, when compared to previously published works. The designed architecture was synthesized targeting four FPGAs: Altera Cyclone III and Stratix IV and Xilinx Spartan 3E and Virtex 4. The best throughput was reached by the Xilinx Virtex 4 device, with a processing rate of 506 VGA frames per second. The worst result was reached by the Xilinx Spartan 3E FPGA, with 249 VGA frames per second. All target FPGAs surpasses the necessary throughput to decode VGA videos in real time. This very high throughput is important especially when low power applications are considered, since with low operation frequencies (9.34MHz) it is possible to reach real time (30 frames per second) for all target FPGAs.

Hardware-Efficient Emulation of Leaky Integrate-and-Fire Model Using Template-Scaling-Based Exponential Function Approximation

We present a method to emulate a leaky integrate-and-fire (LIF) model in a field-programmable gate array (FPGA) in a hardware-efficient manner. The simplified spike-response model (SRM0) is chosen as an LIF model. For the hardware-efficient implementation of SRM0, we adopt the template-scaling-based exponential function approximation (TS-EFA). This method allows high precision and low latency exponential function approximations with the efficient use of hardware resources. We subsequently propose an algorithm for SRM0, which leverages the advantage of TS-EFA. An implementation of 512 neurons conforming to SRM0 in an FPGA highlights (i) high precision of SRM0 emulation (mean squared error of membrane potential approximation: $4\times 10^{-12} - 1\times 10^{-10}$ ), (ii) low latency (eight clock cycles), and (iii) high efficiency in hardware usage (only 125b memory per neuron).

Expert system assessing threat level of attacks on a hybrid SSH honeynet

Currently, many systems connected to the internet are exposed to hundreds of mostly automated network attacks on a daily basis. These are mostly very simple attacks originating from botnets. However, sophisticated attacks conducted both by automated systems and directly by humans are becoming more common. In order to develop adequate countermeasures, the behaviour of attackers has to be analysed effectively. Honeypots, a sort of lures for the attacks, are used for that purpose. Configuration of honeypots vary depending on the type of attacks they focus on attracting. For simple, analogous attacks that sequentially repeat predefined commands, medium interaction honeypots are sufficient, while more sophisticated attacks require the use of high interactive honeypots. An essential part of the analysis is to differentiate between these types of attacks to make the overall analysis efficient, in terms of efficient use of hardware resources, and effective by providing the attacker with an appropriately emulated environment. This article first analyses the current situation followed by presenting a solution in the form of a system made up of a hybrid honeynet and an expert system. For now, it focuses only on the SSH protocol, as it is widely used for remote system access and is a popular target of attacks. The system has been tested on real data collected over a one-year period. The article also deals with making redirecting SSH connections as transparent as possible.

Hardware Resource Analysis in Distributed Training with Edge Devices

When training a deep learning model with distributed training, the hardware resource utilization of each device depends on the model structure and the number of devices used for training. Distributed training has recently been applied to edge computing. Since edge devices have hardware resource limitations such as memory, there is a need for training methods that use hardware resources efficiently. Previous research focused on reducing training time by optimizing the synchronization process between edge devices or by compressing the models. In this paper, we monitored hardware resource usage based on the number of layers and the batch size of the model during distributed training with edge devices. We analyzed memory usage and training time variability as the batch size and number of layers increased. Experimental results demonstrated that, the larger the batch size, the fewer synchronizations between devices, resulting in less accurate training. In the shallow model, training time increased as the number of devices used for training increased because the synchronization between devices took more time than the computation time of training. This paper finds that efficient use of hardware resources for distributed training requires selecting devices in the context of model complexity and that fewer layers and smaller batches are required for efficient hardware use.

Lambda response reflects the color and luminance information processing

This work uses the open source codes and PHP web programming to implement a resource management system with power saving method for virtual machines. We propose a system integrated with open source software, such as KVM and Libvirt, to construct a virtual cloud management platform. This system can detect the status of cloud resources via SNMP, calculate the operation efficiency of the overall system, allocate virtual machines through the live migration technology, and turn off extra machines in the cloud to save energy. According to our proposed power saving method, we have constructed a power efficient virtualization management platform in the cloud. Our objective is to provide enterprises or end users with power saving private cloud solutions. In this work we have also built a web page to allow users to easily access and control the cloud virtualization resources, i.e., users can manage virtual machines and monitor the status of resources via the web interface. From analysis of the experimental results of live migration of virtual machines, this work demonstrates that efficient use of hardware resources is realized by the power saving method, and the aim of power saving for cloud computing is achieved.

Virtual machine management system based on the power saving algorithm in cloud

This work uses the open source codes and PHP web programming to implement a resource management system with power saving method for virtual machines. We propose a system integrated with open source software, such as KVM and Libvirt, to construct a virtual cloud management platform. This system can detect the status of cloud resources via SNMP, calculate the operation efficiency of the overall system, allocate virtual machines through the live migration technology, and turn off extra machines in the cloud to save energy. According to our proposed power saving method, we have constructed a power efficient virtualization management platform in the cloud. Our objective is to provide enterprises or end users with power saving private cloud solutions. In this work we have also built a web page to allow users to easily access and control the cloud virtualization resources, i.e., users can manage virtual machines and monitor the status of resources via the web interface. From analysis of the experimental results of live migration of virtual machines, this work demonstrates that efficient use of hardware resources is realized by the power saving method, and the aim of power saving for cloud computing is achieved.

Optimized and Portable FPGA-Based Systolic Cell Architecture for Smith-Waterman-Based DNA Sequence Alignment

The alignment of DNA sequences is one of the important processes in the field of bioinformatics. The Smith–Waterman algorithm (SWA) performs optimally for aligning sequences but is computationally expensive. Field programmable gate array (FPGA) performs the best on parameters such as cost, speed-up, and ease of re-configurability to implement SWA. The performance of FPGA-based SWA is dependent on efficient cell-basic implementation-unit design. In this paper, we present an optimized systolic cell design while avoiding oversimplification, very large-scale integration (VLSI)-level design, and direct mapping of iterative equations such as previous cell designs. The proposed design makes efficient use of hardware resources and provides portability as the proposed design is not based on gate-level details. Our cell design implementing a linear gap penalty resulted in a performance improvement of 32× over a GPP platform and surpassed the hardware utilization of another implementation by a factor of 4.23.

Gem5v: a modified gem5 for simulating virtualized systems

Virtualization is growing in different areas: from powerful servers in data centers to students' laptops and even cell phones. It can provide a more efficient use of hardware resources. Virtualization enables multiple virtual machines to run side-by-side in an isolated environment on a physical hardware. Modern processors are enhanced with technologies like Intel-VT and AMD-V that speed up virtual machines. However, there is still room for improving support of hardware for virtualization workloads. Gem5 is an open-source full system simulator capable of simulating a Chip-Multiprocessor with its caches, interconnection network, memory controllers among others. In its current state, gem5 does not support virtualized workloads. In this paper, we present a modified version of gem5, named gem5v, that simulates the behavior of a virtualization layer and can simulate virtual machines. We test this simulator in different scenarios using Parsec, Splash, MapReduce (Phoenix), SPEC and EEMBC benchmarks and compare its measured runtime with real systems. Results show 1---9 % difference between the simulated system and two virtualization softwares on a real hardware, namely KVM and VMware ESX. The comparison of vCPU overhead in VMware ESX and gem5v shows between 0.1 and 9 % difference.

Battery Pack Modeling, Simulation, and Deployment on a Multicore Real Time Target

Battery Management System (BMS) design is a complex task requiring sophisticated models that mimic the electrochemical behavior of the battery cell under a variety of operating conditions. Equivalent circuits are well-suited for this task because they offer a balance between fidelity and simulation speed, their parameters reflect direct experimental observations, and they are scalable. Scalability is particularly important at the real time simulation stage, where a model of the battery pack runs on a real-time simulator that is physically connected to the peripheral hardware in charge of monitoring and control. With modern battery systems comprising hundreds of cells, it is important to employ a modeling and simulation approach that is capable of handling numerous simultaneous instances of the basic unit cell while maintaining real time performance. In previous publications we presented a technique for the creation of a battery cell model that contains the electrochemical fingerprints of a battery cell based on equivalent circuit model fitting to experimental data. In this work we extend our previous model to represent a battery pack, featuring cell creation, placement, and connection using automation scripts, thus facilitating the design of packs of arbitrary size and electrical topology. In addition, we present an assessment of model partitioning schemes for real time execution on multicore targets to ensure efficient use of hardware resources, a balanced computational load, and a study of the potential impact of the calculation latencies inherent to distributed systems on solver accuracy. Prior to C code generation for real time execution, a model profiler assesses the model partitioning and helps determine the multicore configuration that results in the lowest average turnaround time, the time elapsed between task start and finish.

The architecture of virtual machines

A virtual machine can support individual processes or a complete system depending on the abstraction level where virtualization occurs. Some VMs support flexible hardware usage and software isolation, while others translate from one instruction set to another. Virtualizing a system or component -such as a processor, memory, or an I/O device - at a given abstraction level maps its interface and visible resources onto the interface and resources of an underlying, possibly different, real system. Consequently, the real system appears as a different virtual system or even as multiple virtual systems. Interjecting virtualizing software between abstraction layers near the HW/SW interface forms a virtual machine that allows otherwise incompatible subsystems to work together. Further, replication by virtualization enables more flexible and efficient and efficient use of hardware resources.

Implementation of media processors

Conventional standard processors do not correspond well to the characteristics of multimedia signal processor algorithms. Therefore, special architectural approaches are necessary for multimedia processors to deliver the required high processing power with efficient use of hardware resources. Programmable approaches offer a high degree of flexibility. In order to attain multimedia signal processor performance, architectural strategies for programmable processors are based on parallelization and adaptation principles. The future multimedia signal processor implementation hinges upon an optimal trade-off between the two design spaces, which can be effectively addressed by a codesign approach.