Efficient Task Mapping Research Articles

NeuroMap: Efficient Task Mapping of Deep Neural Networks for Dynamic Thermal Management in High-Bandwidth Memory

High-bandwidth memory (HBM) offers breakthrough memory bandwidth through its vertically stacked memory architecture and through-silicon via (TSV)-based fast interconnect. However, the stacked architecture leads to high-power density causing thermal issues when running modern memory-hungry workloads such as deep neural networks (DNNs). Prior works on dynamic thermal management (DTM) of 3-D DRAM do not consider the physical structure of HBM and often lead to heavy DTM-induced performance penalty. We propose an application-aware efficient task mapping and migration-based DTM policy that maps DNN instances to cores through exploiting the channel layout of HBM and leveraging the significant temperature gradient across DRAM dies while making thermal decisions. We utilize the variation in the memory access behavior of DNN layers and attempt to minimize stalling due to thermal hotspots in the HBM stack. We also use application-aware dynamic voltage and frequency scaling (DVFS) and DRAM low-power states to further improve performance. Experimental results on workloads comprising seven popular DNNs show that NeuroMap results in an average execution time and memory energy reduction of 39% and 40%, respectively, over state-of-the-art DTM mechanisms.

Q‐scheduler: A temperature and energy‐aware deep Q‐learning technique to schedule tasks in real‐time multiprocessor embedded systems

Reducing energy consumption under processors' temperature constraints has recently become a pressing issue in real-time multiprocessor systems on chips (MPSoCs). The high temperature of processors affects the power and reliability of the MPSoC. Low energy consumption is necessary for real-time embedded systems, as most of them are portable devices. Efficient task mapping on processors has a significant impact on reducing energy consumption and the thermal profile of processors. Several state-of-the-art techniques have recently been proposed for this issue. This paper proposes Q-scheduler, a novel technique based on the deep Q-learning technology, to dispatch tasks between processors in a real-time MPSoC. Thousands of simulated tasks train Q-scheduler offline to reduce the system's power consumption under temperature constraints of processors. The trained Q-scheduler dispatches real tasks in a real-time MPSoC online while also being trained regularly online. Q-scheduler dispatches multiple tasks in the system simultaneously with a single process; the effectiveness of this ability is significant, especially in a harmonic real-time system. Experimental results illustrate that Q-scheduler reduces energy consumption and temperature of processors on average by 15% and 10%, respectively, compared to previous state-of-the-art techniques.

ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes

Parallel applications often rely on work stealing schedulers in combination with fine-grained tasking to achieve high performance and scalability. However, reducing the total energy consumption in the context of work stealing runtimes is still challenging, particularly when using asymmetric architectures with different types of CPU cores. A common approach for energy savings involves dynamic voltage and frequency scaling (DVFS) wherein throttling is carried out based on factors like task parallelism, stealing relations, and task criticality. This article makes the following observations: (i) leveraging DVFS on a per-task basis is impractical when using fine-grained tasking and in environments with cluster/chip-level DVFS; (ii) task moldability, wherein a single task can execute on multiple threads/cores via work-sharing, can help to reduce energy consumption; and (iii) mismatch between tasks and assigned resources (i.e., core type and number of cores) can detrimentally impact energy consumption. In this article, we propose EneRgy Aware SchedulEr (ERASE), an intra-application task scheduler on top of work stealing runtimes that aims to reduce the total energy consumption of parallel applications. It achieves energy savings by guiding scheduling decisions based on per-task energy consumption predictions of different resource configurations. In addition, ERASE is capable of adapting to both given static frequency settings and externally controlled DVFS. Overall, ERASE achieves up to 31% energy savings and improves performance by 44% on average, compared to the state-of-the-art DVFS-based schedulers.

A Cloud Computing-Based Modified Symbiotic Organisms Search Algorithm (AI) for Optimal Task Scheduling.

The search algorithm based on symbiotic organisms’ interactions is a relatively recent bio-inspired algorithm of the swarm intelligence field for solving numerical optimization problems. It is meant to optimize applications based on the simulation of the symbiotic relationship among the distinct species in the ecosystem. The task scheduling problem is NP complete, which makes it hard to obtain a correct solution, especially for large-scale tasks. This paper proposes a modified symbiotic organisms search-based scheduling algorithm for the efficient mapping of heterogeneous tasks to access cloud resources of different capacities. The significant contribution of this technique is the simplified representation of the algorithm’s mutualism process, which uses equity as a measure of relationship characteristics or efficiency of species in the current ecosystem to move to the next generation. These relational characteristics are achieved by replacing the original mutual vector, which uses an arithmetic mean to measure the mutual characteristics with a geometric mean that enhances the survival advantage of two distinct species. The modified symbiotic organisms search algorithm (G_SOS) aims to minimize the task execution time (makespan), cost, response time, and degree of imbalance, and improve the convergence speed for an optimal solution in an IaaS cloud. The performance of the proposed technique was evaluated using a CloudSim toolkit simulator, and the percentage of improvement of the proposed G_SOS over classical SOS and PSO-SA in terms of makespan minimization ranges between 0.61–20.08% and 1.92–25.68% over a large-scale task that spans between 100 to 1000 Million Instructions (MI). The solutions are found to be better than the existing standard (SOS) technique and PSO.

A Hybridized Bat Algorithm for effective Task

The recently developed distributed framework Cloud Computing (CC) offers versatile and dynamically scalable low-cost computing services. In CC environment Task Scheduling (TS) is the key issues to be tackled to boost system performance and increase cloud satisfaction for customers. Advanced programming techniques should be introduced to ensure an efficient cloud mapping of tasks to fulfil the complex necessities of end-users applications. Having regard to a timing problem, unrelated MTs are responsible to perform individual tasks, is the key motivation behind this study. There are many subtasks to a mission. Only after completion of its predecessor subtask can a successor subtask be started. The subtasks may be carried out in the same machine or in another machine independently. It is known in advance how long each machine is run. Due to the continuous processing of other work, each computer has known release time (i.e., the time available to perform current tasks). We also considered two variants of problems for two separate objective functions in this research paper. The first version of the problem takes note of minimising the overall finishing time target while the second version considers minimising the Making-Time goal. In this paper we proposed an algorithm for hybridised bat optimization for this multi-target TS. Unlike current algorithms, an optimum solution can be sought by using fewer iterations. We have compared to determine the performance of this enhanced Bat Algorithm with the existing systems. The experiment conclude that the proposed procedureacts well in comparison with other TS algorithms.

Evaluation of Static Mapping for Dynamic Space-Shared Multi-task Processing on FPGAs

Whilst FPGAs have been used in cloud ecosystems, it is still extremely challenging to achieve high compute density when mapping heterogeneous multi-tasks on shared resources at runtime. This work addresses this by treating the FPGA resource as a service and employing multi-task processing at the high level, design space exploration and static off-line partitioning in order to allow more efficient mapping of heterogeneous tasks onto the FPGA. In addition, a new, comprehensive runtime functional simulator is used to evaluate the effect of various spatial and temporal constraints on both the existing and new approaches when varying system design parameters. A comprehensive suite of real high performance computing tasks was implemented on a Nallatech 385 FPGA card and show that our approach can provide on average 2.9 × and 2.3 × higher system throughput for compute and mixed intensity tasks, while 0.2 × lower for memory intensive tasks due to external memory access latency and bandwidth limitations. The work has been extended by introducing a novel scheduling scheme to enhance temporal utilization of resources when using the proposed approach. Additional results for large queues of mixed intensity tasks (compute and memory) show that the proposed partitioning and scheduling approach can provide higher than 3 × system speedup over previous schemes.

Efficient Use of On-Chip Memories and Scheduling Techniques to Eliminate the Reconfiguration Overheads in Reconfigurable Systems

Modern embedded systems are packed with dedicated Field Programmable Gate Arrays (FPGAs) to accelerate the overall system performance. However, the FPGAs are susceptible to reconfiguration overheads. The reconfiguration overheads are mainly because of the configuration data being fetched from the off-chip memory at run-time and also due to the improper management of tasks during execution. To reduce these overheads, our proposed methodology mainly focuses on the prefetch heuristic, reuse technique, and the available memory hierarchy to provide an efficient mapping of tasks over the available memories. Our paper includes a new replacement policy which reduces the overall time and energy reconfiguration overheads for static systems in their subsequent iterations. It is evident from the result that most of the reconfiguration overheads are eliminated when the applications are managed and executed based on our methodology.

A smart protocol-level task mapping for energy efficient traffic on network-on-chip

Previous task mapping assumes that applications directly fetch data on remote nodes and build up their energy efficient mapping based on pattern of the NoC traffic. However, the data movement is actually managed by a cache coherence mechanism that executes a much more complicated protocol under application layer to guarantee data correction. Thus, we propose an energy efficient task mapping referring the protocol layer, rather than application layer, to precisely model protocol activities and energy dissipation. By a probabilistic description of cache accessing, we find a efficient method to convert application activities to energy consumption, generating an energy evaluation as a global optimization goal. We also propose a task mapping algorithm to minimize the energy consumption by referring activity intensity of the protocol. The experimental results show that the proposed energy model achieves a precision with less than 2% error and provides a credible quantitative criterion for energy optimization of cache coherence protocols. Comparing to application-layer optimization, our task mapping can obtain 20% energy saving and 15% latency reduction on average.

ImGA: an improved genetic algorithm for partitioned scheduling on heterogeneous multi-core systems

Efficient mapping of tasks onto heterogeneous multi-core systems is very challenging especially in the context of real-time applications. Assigning tasks to cores is an NP-hard problem and solving it requires the use of meta-heuristics. Relevantly, genetic algorithms have already proven to be one of the most powerful and widely used stochastic tools to solve this problem. Conventional genetic algorithms were initially defined as a general evolutionary algorithm based on blind operators with pseudo-random operations. It is commonly admitted that the use of these operators is quite poor for an efficient exploration of big problems. Likewise, since exhaustive exploration of the solution space is unrealistic, a potent option is often to guide the exploration process by hints, derived by problem structure. This guided exploration prioritizes fitter solutions to be part of next generations and avoids exploring unpromising configurations by transmitting a set of predefined criteria from parents to children. Consequently, genetic operators, such as initial population, crossover, mutation must incorporate specific domain knowledge to intelligently guide the exploration of the design space. In this paper, an improved genetic algorithm (ImGA) is proposed to enhance the conventional implementation of this evolutionary algorithm. In our experiments, we proved that ImGA leads to perceptible increase in the performance of the genetic algorithm and its convergence capabilities.

Task Scheduling in Heterogeneous Multiprocessor Environments – An Efficient ACO-Based Approach

In heterogeneous computing environments, finding optimized solutions continues to be one of the most important and yet, very challenging problems. Task scheduling in such environments is NP-hard, so efficient mapping of tasks to the processors remains one of the most critical issues to be tackled. For several types of applications, the task scheduling problem is crucial, and across the literature, a number of algorithms with several different approaches have been proposed. One such effective approach is known as Ant Colony Optimization (ACO). This popular optimization technique is inspired by the capabilities of ant colonies to find the shortest paths between their nests and food sources. Consequently, we propose an ACO-based algorithm, called rACS, as a solution to the task scheduling problem. Our algorithm utilizes pheromone and a priority-based heuristic, known as the upward rank value, as well as an insertion-based policy and a pheromone aging mechanism to guide the ants to high quality solutions. To evaluate the performance of our algorithm, we compared our algorithm with the ACS algorithm and the ACO-TMS algorithm using randomly generated directed acyclic graphs (DAGs). The simulation results indicated that our algorithm experienced comparable or even better performance, than the selected algorithms.

KAPow

In an FPGA system-on-chip design, it is often insufficient to merely assess the power consumption of the entire circuit by compile-time estimation or runtime power measurement. Instead, to make better decisions, one must understand the power consumed by each module in the system. In this work, we combine measurements of register-level switching activity and system-level power to build an adaptive online model that produces live breakdowns of power consumption within the design. Online model refinement avoids time-consuming characterization while also allowing the model to track long-term operating condition changes. Central to our method is an automated flow that selects signals predicted to be indicative of high power consumption, instrumenting them for monitoring. We named this technique KAPow, for ‘K’ounting Activity for Power estimation, which we show to be accurate and to have low overheads across a range of representative benchmarks. We also propose a strategy allowing for the identification and subsequent elimination of counters found to be of low significance at runtime, reducing algorithmic complexity without sacrificing significant accuracy. Finally, we demonstrate an application example in which a module-level power breakdown can be used to determine an efficient mapping of tasks to modules and reduce system-wide power consumption by up to 7%.

Defragmentation of Tasks in Many-Core Architecture

Many-cores can execute multiple multithreaded tasks in parallel. A task performs most efficiently when it is executed over a spatially connected and compact subset of cores so that performance loss due to communication overhead imposed by the task’s threads spread across the allocated cores is minimal. Over a span of time, unallocated cores can get scattered all over the many-core, creating fragments in the task mapping. These fragments can prevent efficient contiguous mapping of incoming new tasks leading to loss of performance. This problem can be alleviated by using a task defragmenter, which consolidates smaller fragments into larger fragments wherein the incoming tasks can be efficiently executed. Optimal defragmentation of a many-core is an NP-hard problem in the general case. Therefore, we simplify the original problem to a problem that can be solved optimally in polynomial time. In this work, we introduce a concept of exponentially separable mapping (ESM), which defines a set of task mapping constraints on a many-core. We prove that an ESM enforcing many-core can be defragmented optimally in polynomial time.

A Comparative Study of Task Scheduling and Load Balancing Techniques with MCT using ETC on Computational Grids

Objectives: In this paper various task scheduling algorithm along with load distribution techniques investigated to ensure efficient mapping of tasks to resources and for coherent resource utilization in heterogeneous environment. Statistical Analysis: A detailed comparative approach is conferred for different job scheduling and load balancing algorithm available in the literature. Considered parameters for comparisons are scheduling approaches, techniques, findings, benefits, pros and cons. This study facilitates to identify the efficient scheduling and load balancing approach which optimizes resource use, minimizes completion time as well as task waiting time and balanced load among resources. Findings: Make span time and flow time are two important parameters to compute and minimize job execution time. This paper explores an intense survey of minimization of task execution time with minimum make span time and flow time. Apart from this a joint review on job scheduling, load balancing and minimizing job completion time using Expected Time to Compute (ETC) matrix is presented. At the end of this paper a research model is proposed which is a novel and hybrid approach with a combination of the efficiency of scheduling and load balancing. Application: The Load Balancing (LB) is an important feature of the grid environment. The efficient LB algorithm assures cost effective resource usage by the provisioning of resources to users on demand schedule in pay-as-you-say-manner.

Mapping multiple applications onto 3D NoC-based MPSoCs supporting wireless links

Three-dimensional integrated circuits (3D ICs) are suitable alternatives to traditional two-dimensional (2D) ICs by leveraging its advantage of better performance and packaging; therefore, they have been highly considered by researchers. On the other hand, emerging network-on-chip (NoC) based many-core chips provides great potential for running multiple applications simultaneously. However, using this approach leads to the increase of the interference between applications, resulting in lowering the performance of each application. Hence, mapping tasks belonging to various applications onto the nodes of an architecture is a very important issue. In this study, based on partitioning concept, a novel methodology for mapping of multiple applications at run-time onto an irregular wireless 3D NoC-based multiprocessor system-on-chip (MPSoC) platform in which more than one task can be supported by each processing element (PE) was presented. In the second algorithm (enhanced irregular-partitioning best neighbor), according to the number of applications running simultaneously, the partitioning of network will be dynamically changed to minimize the communication overhead and congestion on the NoC that leads to more efficient task mapping. The simulation results reveal that the second proposed algorithm (enhanced IPBN) in comparison with NPBN (non-partitioning best neighbor) algorithm and our first proposed algorithm (basic IPBN) enhances the performance by decreasing the total execution time, average hop count, average channel load and energy consumption.

An efficient task mapping algorithm with power-aware optimization for network on chip

An online scheduling is proposed for NOC-based manycore systems.The task with heavy traffic is mapped to the core first.The tasks are re-mapped according to the run-time information.Communication-intensive scheduling gathers the tasks in different regions.A large portion of the communication latency and power consumption is reduced. More and more cores are integrated onto a single chip to improve the performance and reduce the power consumption of CPU without the increased frequency. The cores are connected by lines and organized as a network, which is called network on chip (NOC) as the promising paradigm of the processor design. However, it is still a challenge to enhance performance with lower power consumption. The core issue is how to map the tasks to the different cores to take full advantages of the on-chip network. In this paper, we proposed a novel mapping algorithm with power-aware optimization for NOC. The traffic of the tasks will be analyzed. The tasks of the same application with high communication with the others will be mapped to the on-chip network as neighborhoods. And then the tasks of different applications are mapped to the cores step by step. The mapping of the tasks and the cores is computed at run-time dynamically and implement online. The experimental results showed that this proposed algorithm can reduce the power consumption in communication and the performance enhanced.

Multiprocessor Real-Time Systems with Shared Resources: Utilization Bound and Mapping

In real-time systems, both scheduling theory and resource access protocols have been studied extensively. However, there is very limited research on scheduling algorithms for real-time systems with shared resources, where the problem becomes more prominent with the emergence of multicore processors. In this paper, focusing on partitioned-EDF scheduling and MSRP resource access protocol, we study the utilization bound and efficient task mapping schemes for a set of periodic real-time tasks that access shared resources in multiprocessor/multicore systems. Specifically, with synchronization overhead being considered, we illustrate the schedulability anomaly for such systems. We develop the first synchronization-cognizant utilization bound and further analyze its non-monotonicity where the bound can decrease when more processors are deployed. Then, we show that finding the optimal mapping for tasks with shared resources is NP-hard. Based on a novel approach that iteratively tightens the synchronization overhead, we propose two efficient synchronization-cognizant task mapping algorithms (SC-TMA) with the goal of achieving better schedulability and balanced workload on deployed processors. Finally, the proposed SC-TMA schemes are evaluated through extensive simulations with synthetic tasks. The results show that, the schedulability ratio and (average) system load under SC-TMA are close to that of an INLP (Integer Non-Linear Programming) based solution for small task systems. When compared to the existing task mapping algorithms, SC-TMA obtain much better schedulability ratio and lower/balanced workload on all processors.

Post-Silicon Energy Optimization on Voltage-Frequency Island Based 3-D Multi-Core SoCs

Technology scaling dramatically increases transistor integration capacity, enabling more and more cores to be integrated into a single chip. Parameter variability, however, leads to performance asymmetry among the cores, degrading the energy efficiency of the system. Recently, voltage/frequency island (VFI) based designs are widely exploited on a multi-core platform for system energy optimization under variations. In this paper, a post-silicon energy optimization scheme is proposed targeting VFI-based 3-D multi-core SoCs. Design constraints on VFI, difference of communication energies between horizontal and vertical directions and unique thermal feature of the 3-D chip are totally considered. An energy efficient task mapping and scheduling algorithm is proposed, which seamlessly combines with dynamic voltage/frequency scaling to minimize the system energy under deadline and thermal constraints. Experimental results demonstrate that the effectiveness of the proposed scheme.

A study on combinational effects of job and resource characteristics on energy consumption

By becoming more popular and complex, HPC systems like computational grids, clusters, clouds and the supporting data centers are now changed to remarkable energy consumers. A wide variety of researches, ranging from power-aware hardware design to developing optimized programs and to power-aware job scheduling, have been done hitherto in order to reduce their energy consumption. However, the success of these approaches highly depends to having a precise knowledge about power consumption behavior of the target system. In this paper, some neglected facts are shown about combinational effects of jobs' and resources' characteristics on energy consumption rate and define corresponding parameters which make these facts practically utilizable by formulating them as functions of job-machine characteristics. These facts are supported by the experimental analyses on real machines and analytical studies. The outcome of this paper can be exploited to have more energy efficient task mapping process in large-scale heterogeneous computational systems.

A survey of task mapping on production grids

Grids designed for computationally demanding scientific applications started experimental phases ten years ago and have been continuously delivering computing power to a wide range of applications for more than half of this time. The observation of their emergence and evolution reveals actual constraints and successful approaches to task mapping across administrative boundaries. Beyond differences in distributions, services, protocols, and standards, a common architecture is outlined. Application-agnostic infrastructures built for resource registration, identification, and access control dispatch delegation to grid sites. Efficient task mapping is managed by large, autonomous applications or collaborations that temporarily infiltrate resources for their own benefits.

Adaptive workflow scheduling for dynamic grid and cloud computing environment

SUMMARYEffective scheduling is a key concern for the execution of performance‐driven grid applications such as workflows. In this paper, we first define the workflow scheduling problem and describe the existing heuristic‐based and metaheuristic‐based workflow scheduling strategies in grids. Then, we propose a dynamic critical‐path‐based adaptive workflow scheduling algorithm for grids, which determines efficient mapping of workflow tasks to grid resources dynamically by calculating the critical path in the workflow task graph at every step. Using simulation, we compared the performance of the proposed approach with the existing approaches, discussed in this paper for different types and sizes of workflows. The results demonstrate that the heuristic‐based scheduling techniques can adapt to the dynamic nature of resource and avoid performance degradation in dynamically changing grid environments. Finally, we outline a hybrid heuristic combining the features of the proposed adaptive scheduling technique with metaheuristics for optimizing execution cost and time as well as meeting the users requirements to efficiently manage the dynamism and heterogeneity of the hybrid cloud environment. Copyright © 2013 John Wiley & Sons, Ltd.