Efficient Utilization Of Processors Research Articles

A Multiprocessor Simulation for Advanced Signal Processing Applications

This paper presents a multiprocessor simulation that executes an advanced signal processing algorithm i.e. beamforming for sensor arrays. The simulation model involves several desktop PCs. It demonstrates how an advanced signal processing technique can be implemented on a system that is based on multiple digital signal processors (DSPs) in the absence of actual hardware. It uses MATLAB, a DSP simulator, and an open source MATLAB based message passing interface (MPI). The simulation applies a frequency-domain beamformer to a linear sensor array and the results show efficient utilization of processors for real-time operation.

A Fully Pipelined Multishift QR Algorithm for Parallel Solution of Symmetric Tridiagonal Eigenproblems

In this paper, we propose a fully pipelined multishift QR algorithm to compute all the eigenvalues of a symmetric tridiagonal matrix on parallel machines. Existing approaches for parallelizing the tridiagonal QR algorithm, such as the conventional multishift QR algorithm and the deferred shift QR algorithm, have suffered from either inefficiency of processor utilization or deterioration of convergence properties. In contrast, our algorithm realizes both efficient processor utilization and improved convergence properties at the same time by adopting a new shifting strategy. Numerical experiments on a shared memory parallel machine (Fujitsu PrimePower HPC2500) with 32 processors show that our algorithm is up to 1.9 times faster than the conventional multishift algorithm and up to 1.7 times faster than the deferred shift algorithm.

Provably Efficient Online Nonclairvoyant Adaptive Scheduling

Multiprocessor scheduling in a shared multiprogramming environment can be structured in two levels, where a kernel-level job scheduler allots processors to jobs and a user-level thread scheduler maps the ready threads of a job onto the allotted processors. We present two provably-efficient two-level scheduling schemes called G-RAD and S-RAD respectively. Both schemes use the same job scheduler RAD for the processor allotments that ensures fair allocation under all levels of workload. In G-RAD, RAD is combined with a greedy thread scheduler suitable for centralized scheduling; in S-RAD, RAD is combined with a work-stealing thread scheduler more suitable for distributed settings. Both G-RAD and S-RAD are non-clairvoyant. Moreover, they provide effective control over the scheduling overhead and ensure efficient utilization of processors. We also analyze the competitiveness of both G-RAD and S-RAD with respect to an optimal clairvoyant scheduler. In terms of makespan, both schemes can achieve O(1)-competitiveness for any set of jobs with arbitrary release time. In terms of mean response time, both schemes are O(1)-competitive for arbitrary batched jobs. To the best of our knowledge, G-RAD and S-RAD are the first non-clairvoyant scheduling algorithms that guarantee provable efficiency, fairness and minimal overhead.

MMX-enabled Dolby Digital decoder

Software decoding of Dolby Digital (an adaptive transform-based coder using a frequency-linear, critically sampled filterbank) allows it to become a baseline capability on the personal computer (PC), with greater flexibility than a hardware approach. Intel's MMX technology provides instructions that can significantly speed up the execution of the Dolby Digital decoder, freeing up the processor to perform other tasks such as video decoding and/or audio enhancement. Intel's MMX instructions operate on 8, 16, and 32 bits. The smaller the data size, the more operations per instruction are performed. Using 16 bits of accuracy uniformly through a Dolby Digital decoder is insufficient to pass the test suite. The challenge was to obtain both good execution speed and good audio quality. Although 32-bit floating-point numbers could be used throughout the data path and only use MMX technology for bit manipulation, this would not be the most processor-efficient method. To this end, we used 16-bit SIMD (single-instruction, multiple data) operations during much of the decoder, but performed 8- and 32-bit SIMD operations on certain sections. While we discuss a particular use of MMX technology, the MMX instruction set is general purpose in nature. We provide a description of MMX technology and then describe the major functional blocks of a Dolby Digital decoder and the special techniques used that take advantage of MMX technology. We also include a description of precision enhancements that were implemented to maintain accuracy and a description of other performance enhancements that were made. We conclude with results in terms of efficient processor utilization, numerical accuracy, and audio quality.

Generation, Optimization, and Evaluation of Multithreaded Code

The recent advent of multithreaded architectures holds many promises: the exploitation of intrathread locality and the latency tolerance of multithreaded synchronization can result in a more efficient processor utilization and higher scalability. The challenge for a code generation scheme is to make effective use of the underlying hardware by generating large threads with a large degree of internal locality without limiting the program level parallelism or increasing latency. Top-down code generation, where threads are created directly from the compiler's intermediate form, is effective at creating a relatively large thread. However, having only a limited view of the code at any one time limits the quality of threads generated. These top-down generated threads can therefore be optimized by global, bottom-up optimization techniques. In this paper, we introduce the Pebbles multithreaded model of computation and analyze a code generation scheme whereby top-down code generation is combined with bottom-up optimizations. We evaluate the effectiveness of this scheme in terms of overall performance and specific thread characteristics such as size, length, instruction level parallelism, number of inputs, and synchronization costs.

Parallel computation of multiple biological sequence comparisons

A parallel implementation of an efficient method for comparison of multiple DNA sequences is presented. The method is described in terms of a conceptual tree data structure for the sequences to be compared. The parallel algorithm shows efficient utilization of processors on an Encore Multimax computer in a sample comparison of 11 sequences totaling over 4000 bases. Timing data show the strong influence of computer system details on this parallel program. Also presented is a graphics program for displaying multiple sequence comparison output data. The display is capable of representing large volumes of multiple sequence comparison data in a single plot. The program has several additional features that allow closer examination of subsets of sequences. A display of matches from the sample comparison reflects the known structure of these sequences.