Efficient Memory Management Scheme Research Articles

Towards High Performance and Efficient Memory Deduplication via Mixed Pages

Large pages are widely supported in modern hardware and OSes to reduce the overhead of TLB misses. However, memory deduplication can be inefficient with large pages, leading to low memory utilization. To simultaneously enjoy the benefits of high performance by accessing memory with large pages (e.g., 2 MB pages) and high deduplication rate by managing memory with base pages (e.g., 4 KB pages), we propose <u>Smart</u> <u>M</u> emory <u>D</u> eduplciation (SmartMD), which is an adaptive and efficient memory management scheme via mixed pages. Specifically, we propose lightweight schemes to periodically monitor pages’ access frequency and repetition rate, and present an adaptive conversion scheme to selectively split or reconstruct large pages. We further optimize SmartMD by developing SmartMD <inline-formula><tex-math notation="LaTeX">$^{+}$</tex-math></inline-formula> , which dynamically adjusts the page scanning cycle by monitoring the TLB miss cost, and reconstructs the split large pages in an on-demand way so as to reduce the CPU overhead of SmartMD. We further implement a prototype system and conduct extensive experiments with various workloads under different system settings. Experiment results show that SmartMD and SmartMD <inline-formula><tex-math notation="LaTeX">$^{+}$</tex-math></inline-formula> can simultaneously achieve high access performance similar to systems using large pages, and achieve a deduplication rate similar to that applying aggressive deduplication scheme (i.e., KSM) on base pages.

Memory management scheme for cost-effective disk-on-modules in consumer electronics devices

A disk-on-module (DOM) is a NAND flash memory-based device with legacy I/O interface which does not require any special device driver due to the presence of flash translation layer (FTL). FTL is an intermediate software layer which makes DOMs look like conventional hard disk drives. Since DOMs are usually used in mass-market consumer electronics devices, they are extremely cost sensitive; hence FTL should be able to run in a severely resource-constrained environment. In this paper, we propose TinyFTL, a new FTL which employs an efficient memory management scheme for DOMs with a very small amount of memory. TinyFTL divides the mapping information into multiple levels and caches only recently-accessed mapping information in memory. According to experimental evaluation, TinyFTL shows the performance comparable to or better than the existing FTLs with only 4.3- 6.2% of memory requirement (12 KB) for 16 GB NAND flash memory.

PPL: A whole-image processing language

This paper presents the design and implementation of the picture processing language (PPL) that extends the syntax and semantics of traditional image processing libraries. PPL provides a rich set of features to support the development of imaging systems. A main aspect is that many of these features treat a whole-image as an individual operand. An efficient memory management scheme is included that allows “in-place operation” with high memory efficiency. The PPL compiler together with an interpreter can work in two modes. The PPL compiler can convert the source code into C files that can be used as macros within a client program. The program can also be executed at run-time by an interpreter. The dual-execution modes make it possible to be used by both imaging researchers and equipment developers. The extended set of PPL instructions can communicate with digital sensors and 3D displays, and store image data into databases across the Internet. The wavelet-based reverse prediction algorithm can speed up the image loading process approximately three times faster than JPEG. The application programming interface (API) of PPL provides all the building blocks for programmers.

Efficient memory management for concurrent programs that use message passing

We present an efficient memory management scheme for concurrent programming languages where communication occurs by using message passing with copying semantics. The runtime system is built around process-local heaps, which frees the memory manager from redundant synchronization in a multi-threaded implementation and allows the memory reclamation of process-local heaps to be a private business and to often take place without ever triggering garbage collection. The allocator is guided by a static analysis which speculatively allocates data possibly used as messages in a shared memory area. To respect the (soft) real-time requirements of the language, we develop and present in detail a generational, incremental garbage collection scheme tailored to the characteristics of this runtime system. The incremental collector imposes no overhead on the mutator, requires no costly barrier mechanisms, has a relatively small space overhead, and can be scheduled on the basis of either a time or a work quantum. We have implemented these schemes in the context of an industrial-strength implementation of a concurrent functional language used to develop large-scale, highly concurrent, telecommunication applications. Our measurements across a range of applications indicate that the incremental collector imposes only very small overhead on the total runtime and can achieve very short pause times (1 ms or less) while being able to sustain a high degree of mutator utilization.

Efficient evolutionary optimization through the use of a cultural algorithm

This paper introduces a cultural algorithm that uses domain knowledge to improve the performance of an evolutionary programming technique adopted for constrained optimization. The proposed approach extracts domain knowledge during the evolutionary process and builds a map of the feasible region to guide the search more efficiently. Additionally, in order to have a more efficient memory management scheme, the current implementation uses 2 n -trees to store this map of the feasible region. Results indicate that the approach is able to produce very competitive results with respect to other optimization techniques at a considerably lower computational cost.

A Viterbi Decoder with Efficient Memory Management

This paper proposes a new architecture for a Viterbi decoder with an efficient memory management scheme. The trace-back operation is eliminated in the architecture and the memory storing intermediate decision information can be removed. The elimination of the trace-back operation also reduces the number of operation cycles needed to determine decision bits. The memory size of the proposed scheme is reduced to 1/(5 ×constraint length) of that of the register exchange scheme, and the throughput is increased up to twice that of the trace-back scheme. A Viterbi decoder complying with the IS-95 reverse link specification is designed to verify the proposed architecture. The decoder has a code rate of 1/3, a constraint length of 9, and a trace-forward depth of 45.

Memory Management Issues in Sparse Multifrontal Methods On Multiprocessors

This article addresses the problems of memory man agement in a parallel sparse matrix factorization based on a multifrontal approach. We describe how we have adapted and modified the ideas of Duff and Reid used in a sequential symmetric multifrontal method to de sign an efficient memory management scheme for parallel sparse matrix factorization. With our solution, using the minimum size of the working area to run the multifrontal method on a multiprocessor, we can ex ploit only a part of the parallelism of the method. If we slightly increase the size of the working space, then most of the potential parallelism of the method can be exploited. We have designed a flexible memory man agement scheme which adapts well to a variation in the size of the working area and/or the number of pro cessors. General parallel applications can always be represented in terms of a computational graph, which is effectively the underlying structure of a parallel mul tifrontal method. Therefore, we believe that the tech niques presented here are useful when designing an efficient memory management scheme for a wider range of parallel applications.