Efficient Hardware Implementation Research Articles

Multilayer Neural Network Hardware Designs for Faster Convolutional Processing

The demand for efficient hardware implementations of convolutional neural networks (CNNs) has surged with the proliferation of deep learning applications in various domains such as computer vision, natural language processing, and autonomous systems. Convolutional layers, being the fundamental building blocks of CNNs, are computationally intensive, requiring optimized hardware architectures for real-time inference tasks. This paper presents novel hardware designs targeting faster convolutional processing within multilayer neural networks. We propose a multi-faceted approach that leverages parallelism, pipelining, and hardware acceleration techniques to enhance the efficiency of convolution operations. Our design optimally exploits the inherent data-level and model-level parallelism present in CNNs to achieve high throughput while minimizing latency.

Process-in-Memory realized by nonvolatile Task-Scheduling and Resource-Sharing XNOR-Net hardware Accelerator architectures

Due to the success of artificial intelligence systems in solving complex problems, these systems have been investigated in many applications. There is an increasing demand for these systems in many new applications. The XNOR-Net, a binary neural network, is a promising candidate for implementing these systems in devices with limited power and hardware resources. Efficient hardware implementation of XNOR-Nets is critical and has been widely investigated in recent research. In this paper, a resource-sharing gate and architecture and a task-scheduling gate and architecture have been proposed. To reduce power consumption, the proposed nonvolatile logic-in-memory gates are designed based on the magnetic tunnel junction (MTJ) and carbon nanotube field-effect transistor (CNTFET) devices. Using the proposed resource-sharing gate for hardware implementation of XNOR-Net minimizes the number of flip-flops, power consumption, PDP, and area by at least 75%, 75%, 60%, and 42%, respectively, as compared to its state-of-the-art counterparts. Also, using the proposed task-scheduling design to implement the XNOR-Net on 2, 4, and 8 datasets, the power consumption is reduced by at least 24%, 54%, and 65%, respectively, compared to its state-of-the-art counterparts.

Gated Attention Coding for Training High-Performance and Efficient Spiking Neural Networks

Spiking neural networks (SNNs) are emerging as an energy-efficient alternative to traditional artificial neural networks (ANNs) due to their unique spike-based event-driven nature. Coding is crucial in SNNs as it converts external input stimuli into spatio-temporal feature sequences. However, most existing deep SNNs rely on direct coding that generates powerless spike representation and lacks the temporal dynamics inherent in human vision. Hence, we introduce Gated Attention Coding (GAC), a plug-and-play module that leverages the multi-dimensional gated attention unit to efficiently encode inputs into powerful representations before feeding them into the SNN architecture. GAC functions as a preprocessing layer that does not disrupt the spike-driven nature of the SNN, making it amenable to efficient neuromorphic hardware implementation with minimal modifications. Through an observer model theoretical analysis, we demonstrate GAC's attention mechanism improves temporal dynamics and coding efficiency. Experiments on CIFAR10/100 and ImageNet datasets demonstrate that GAC achieves state-of-the-art accuracy with remarkable efficiency. Notably, we improve top-1 accuracy by 3.10% on CIFAR100 with only 6-time steps and 1.07% on ImageNet while reducing energy usage to 66.9% of the previous works. To our best knowledge, it is the first time to explore the attention-based dynamic coding scheme in deep SNNs, with exceptional effectiveness and efficiency on large-scale datasets. Code is available at https://github.com/bollossom/GAC.

Toward Optimized In‐Memory Reinforcement Learning: Leveraging 1/f Noise of Synaptic Ferroelectric Field‐Effect‐Transistors for Efficient Exploration

Reinforcement learning (RL), exhibiting outstanding performance in various fields, requires large amounts of data for high performance. While exploration techniques address this requirement, conventional exploration methods have limitations: complexity of hardware implementation and significant hardware burden. Herein, in‐memory RL systems leveraging intrinsic 1/f noise of synaptic ferroelectric field‐effect‐transistors (FeFETs) for efficient exploration are proposed. The electrical characteristics of fabricated FeFETs with low‐power operation capability verify their suitability for neuromorphic systems. The proposed system achieves comparable performance to the conventional exploration method without additional circuits. The intrinsic 1/f noise of the FeFETs facilitates efficient exploration and offers significant advantages: efficiency in hardware implementation and simplicity in adjusting the 1/f noise level for optimal performance. This approach effectively addresses the challenges of conventional exploration methods. The operation mechanism of the exploration method utilizing the 1/f noise is systematically analyzed. The proposed in‐memory RL system demonstrates robustness and reliability to the device‐to‐device variation and the initial conductance distribution. This work provides further insights into the exploration methods of RL, paving the way for advanced in‐memory RL systems.

Investigating the Performance of Gammatone Filters and Their Applicability to Design Cochlear Implant Processing System

Commercially available cochlear implants are designed to aid profoundly deaf people in understanding speech and environmental sounds. A typical cochlear implant uses a bank of bandpass filters to decompose an audio signal into a set of dynamic signals. These filters’ critical center frequencies f0 imitate the human cochlea’s vibration patterns caused by audio signals. Gammatone filters (GTFs), with two unique characteristics: (a) an appropriate “pseudo resonant” frequency transfer function, mimicking the human cochlea, and (b) realizing efficient hardware implementation, could demonstrate them as unique candidates for cochlear implant design. Although GTFs have recently attracted considerable attention from researchers, a comprehensive exposition of GTFs is still absent in the literature. This paper starts by enumerating the impulse response of GTFs. Then, the magnitude spectrum, |H(f)|, and bandwidth, more specifically, the equivalent rectangular bandwidth (ERB) of GTFs, are derived. The simulation results suggested that optimally chosen filter parameters, e.g., critical center frequencies,f0; temporal decay parameter, b; and order of the filter, n, can minimize the interference of the filter bank frequencies and very likely model the filter bandwidth (ERB), independent of f0b. Finally, these optimized filters are applied to delineate a filter bank for a cochlear implant design based on the Clarion processor model.

Tailor : Altering Skip Connections for Resource-Efficient Inference

Deep neural networks use skip connections to improve training convergence. However, these skip connections are costly in hardware, requiring extra buffers and increasing on- and off-chip memory utilization and bandwidth requirements. In this article, we show that skip connections can be optimized for hardware when tackled with a hardware-software codesign approach. We argue that while a network’s skip connections are needed for the network to learn, they can later be removed or shortened to provide a more hardware-efficient implementation with minimal to no accuracy loss. We introduce Tailor , a codesign tool whose hardware-aware training algorithm gradually removes or shortens a fully trained network’s skip connections to lower the hardware cost. Tailor improves resource utilization by up to 34% for block random access memories (BRAMs), 13% for flip-flops (FFs), and 16% for look-up tables (LUTs) for on-chip, dataflow-style architectures. Tailor increases performance by 30% and reduces memory bandwidth by 45% for a two-dimensional processing element array architecture.

Coupled Ferroelectric-Photonic Memory in a Retinomorphic Hardware for In-Sensor Computing.

The development of all-in-one devices for artificial visual systems offers an attractive solution in terms of energy efficiency and real-time processing speed. In recent years, the proliferation of smart sensors in the growth of Internet-of-Things (IoT) has led to the increasing importance of in-sensor computing technology, which places computational power at the edge of the data-flow architecture. In this study, a prototype visual sensor inspired by the human retina is proposed, which integrates ferroelectricity and photosensitivity in two-dimensional (2D) α-In2Se3 material. This device mimics the functions of photoreceptors and amacrine cells in the retina, performing optical reception and memory computation functions through the use of electrical switching polarization in the channel. The gate-tunable linearity of excitatory and inhibitory functions in photon-induced short-term plasticity enables to encode and classify 12000 images in the Mixed National Institute of Standards and Technology (MNIST) dataset with remarkable accuracy, achieving ≈94%. Additionally, in-sensor convolution image processing through a network of phototransistors, with five convolutional kernels electrically pre-programmed into the transistors is demonstrated. The convoluted photocurrent matrices undergo straightforward arithmetic calculations to produce edge and feature-enhanced scenarios. The findings demonstrate the potential of ferroelectric α-In2Se3 for highly compact and efficient retinomorphic hardware implementation, regardless of ambipolar transport in the channel.

Divide-and-conquer-based RDO-free CU Partitioning for 8K Video Compression

8K (7689×4320) ultra-high definition (UHD) videos are growing popular with the improvement of human visual experience demand. Therefore, the compression of 8K UHD videos has become a top priority in the third-generation audio video coding standard (AVS3). However, as an important part of the coding standard promotion, the real-time hardware implementation for AVS3-based 8K UHD video intra coding is severely hindered, especially in the coding unit (CU) partition stage. To break through the limitation, this article proposes a divide-and-conquer-based rate-distortion-optimization-free (RDO-free) CU partitioning algorithm for efficient hardware implementation. Aimed at the complex CU partition in AVS3, we separately design a lightweight optimization for original partitioning rules to improve division efficiency and a decision tree-based RDO-free CU decision framework to eliminate the latency caused by the waiting for rate-distortion cost calculation in RDO strategy. Afterward, a divide-and-conquer-based hardware-friendly gradient difference calculating approach is devised to accelerate the learning feature extracting speed. To ensure that the proposed algorithm is sufficient to support the real-time CU partition for 8K videos, we also develop a hardware architecture based on FPGA. Experimental results illustrate that the software coding performance of our algorithm is significantly ahead of the efficient implementation uAVS3e for AVS3 and the reference software HM-16.20 for High Efficiency Video Coding (HEVC), even though there is 9.96% loss on BD-Rate Y. Considering its importance for the hardware implementation of AVS3-based 8K real-time encoder, the coding loss is acceptable. Moreover, the hardware simulation results on VU440 FPGA with Vivado 2019 show that our algorithm can support 61.12 frames per second (fps) CU partition for 8K UHD videos with only 0.00%, 0.00%, 1.01%, and 7.78% consumption of BRAM_18K, DSP48E, FF, and LUT, respectively. Additionally, with dual-path parallelism, 122.24 fps also can be implemented with controllable resource utilization, which achieves the state-of-the-art performance.

A novel coupled ergodic sequential logic-based cochlear model: nonlinear hearing characteristics of two-tone responses and efficient hardware implementation

A novel coupled ergodic sequential logic-based cochlear model: nonlinear hearing characteristics of two-tone responses and efficient hardware implementation

A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

Dynamic Probabilistic Pruning: A General Framework for Hardware-Constrained Pruning at Different Granularities.

Unstructured neural network pruning algorithms have achieved impressive compression ratios. However, the resulting-typically irregular-sparse matrices hamper efficient hardware implementations, leading to additional memory usage and complex control logic that diminishes the benefits of unstructured pruning. This has spurred structured coarse-grained pruning solutions that prune entire feature maps or even layers, enabling efficient implementation at the expense of reduced flexibility. Here, we propose a flexible new pruning mechanism that facilitates pruning at different granularities (weights, kernels, and feature maps) while retaining efficient memory organization (e.g., pruning exactly k -out-of- n weights for every output neuron or pruning exactly k -out-of- n kernels for every feature map). We refer to this algorithm as dynamic probabilistic pruning (DPP). DPP leverages the Gumbel-softmax relaxation for differentiable k -out-of- n sampling, facilitating end-to-end optimization. We show that DPP achieves competitive compression ratios and classification accuracy when pruning common deep learning models trained on different benchmark datasets for image classification. Relevantly, the dynamic masking of DPP facilitates for joint optimization of pruning and weight quantization in order to even further compress the network, which we show as well. Finally, we propose novel information-theoretic metrics that show the confidence and pruning diversity of pruning masks within a layer.

FMCW Radar Sensors with Improved Range Precision by Reusing the Neural Network.

This paper addresses the challenge of enhancing range precision in radar sensors through supervised learning. However, when the range precision surpasses the range resolution, it leads to a rapid increase in the number of labels, resulting in elevated learning costs. The removal of background noise in indoor environments is also crucial. In response, this study proposes a methodology aiming to increase range precision while mitigating the issue of a growing number of labels in supervised learning. Neural networks learned for a specific section are reused to minimize learning costs and maximize computational efficiency. Formulas and experiments confirmed that identical fractional multiple patterns in the frequency domain can be applied to analyze patterns in other FFT bin positions (representing different target positions). In conclusion, the results suggest that neural networks trained with the same data can be repurposed, enabling efficient hardware implementation.

The Doubly Linked Tree of Singly Linked Rings: Providing Hard Real-Time Database Operations on an FPGA

We present a hardware data structure specifically designed for FPGAs that enables the execution of the hard real-time database CRUD operations using a hybrid data structure that combines trees and rings. While the number of rows and columns has to be limited for hard real-time execution, the actual content can be of any size. Our structure restricts full navigational freedom to every but the leaf layer, thus keeping the memory overhead for the data stored in the leaves low. Although its nodes differ in function, all have exactly the same size and structure, reducing the number of cascaded decisions required in the database operations. This enables fast and efficient hardware implementation on FPGAs. In addition to the usual comparison with known data structures, we also analyze the tradeoff between the memory consumption of our approach and a simplified version that is doubly linked in all layers.

ALICA: A Multi-S-Box Lightweight Cryptographic Algorithm Based on Generalized Feistel Structure

With the development of science and technology, IoT devices have already become ubiquitous in the public eye. Through the perception layer, the collected data are displayed or transmitted to the server backend for analysis. Due to the increasing integration of IoT devices into people’s daily lives, privacy issues, such as data leaks, have received more attention. Most sensor nodes, such as temperature and pressure sensors in marine environments, have low computing power, storage capacity, and significant underlying heterogeneity, making it challenging to implement a standardized data security protection solution. Data security in the nodes is seriously challenged as a result. It is of great significance to design a lightweight block cipher for the Internet of Things (IoT) environment, which can ensure the security of node information. A new lightweight block cipher algorithm called ALICA is proposed in this paper, which is well-suited for the low computing power and heterogeneous device environment at the lower layers. A generalized Feistel structure and a linear structure with XOR and shift operations are used to achieve ease of software implementation. Two different S-boxes are used to create the nonlinear structure of the password, thereby enhancing the robust security of the cipher. In addition, the cipher adopts a design approach that prioritizes software efficiency while also considering hardware implementation efficiency. This makes it more suitable for low computing power, storage capacity, and resource-limited IoT sensor nodes at the lower layers.

A Low Latency and Compact GCD Design Using an Intelligent Seed-Selection Scheme of LL-PRNG

Stochastic computing has shown great promise for a variety of applications, including image processing circuits, due to its design simplicity and low power consumption. This work proposes a hardware efficient and low latency implementation of Greatest Common Divisor (GCD) circuit. It uses a Low Latency Parallel Random Number Generator (LL-PRNG) architecture with an intelligently chosen seed value that eliminates the use of correlators and decorrelators in the circuit, reducing the hardware overhead to a great extent. The proposed approach is compared with the conventional LFSR based design showing reasonable accuracy while the latency in computation greatly reduced. The circuit is evaluated for blind image deconvolution employing GCD and has shown encouraging results.

Efficient Hardware Implementation of Elliptic-Curve Diffie–Hellman Ephemeral on Curve25519

Hardware architecture optimized for implementing the elliptic-curve Diffie–Hellman ephemeral (ECDHE) on 256-bit Montgomery elliptic curves presents unique challenges, particularly for resource-constrained IoT and mobile devices. This work aims to provide an efficient hardware implementation of ECDHE on Curve25519, including a dedicated finite state machine (FSM) designed to handle point multiplication and ECDHE operations, utilizing constant-time algorithms and a unified memory block for resource management. Additionally, we introduce an optimized modular computation unit that covers modular addition, subtraction, multiplication, and inversion. Our proposed hardware architecture enhances the efficiency of ECDHE operations while maintaining low resource utilization, considerably reduced latency, and low power consumption. Synthesized on the Xilinx Artix-7 platform, our design boasts 64,000 Slices and a clock speed of 102 MHz, and it computes an ECDHE scalar multiplication operation in 1.1 ms, consuming 117 mW. The proposed hardware design can be applied to various platforms, including mobile devices and IoT systems.

Echo state network implementation for chaotic time series prediction

The implementation of an Echo State Neural Network (ESNN) for chaotic time series prediction is introduced. First, the ESNN is simulated using floating-point arithmetic and afterwards fixed-point arithmetic. The synthesis of the ESNN is done in a field-programmable gate array (FPGA), in which the activation function of the neurons’ outputs is a hyperbolic tangent one, and is approximated with a new design of quadratic order b-splines and four integer multipliers. The FPGA implementation of the ESNN is applied to predict four chaotic time series associated to the Lorenz, Chua, Lü, and Rossler chaotic oscillators. The experimental results show that with 50 hidden neurons, the fixed-point arithmetic is good enough when using 15 or 16 bits in the fractional part: using more bits does not reduce the mean-squared error prediction. The neurons are limited to four inputs in the hidden layer to achieve a more efficient hardware implementation, guaranteeing a prediction of more than 10 steps ahead.

Hardware architecture of Dillon’s APN permutation for different primitive polynomials

Cryptographically strong functions used as S-boxes in block cyphers are fundamental for the cypher’s security. Their representation as lookup tables is possible for functions of small dimension. For larger dimensions, this is infeasible, especially if resources are limited. An alternative is representing the function as a polynomial over a finite field, and constructing a circuit evaluating this polynomial. We study how the choice of primitive polynomial affects the efficiency of hardware implementations. We take Dillon’s permutation on 6 bits (the only known permutation in even dimension from the cryptographically optimal Almost Perfect Nonlinear functions) as a relevant example, and present hardware architectures, polynomial representations and hardware theoretical complexities for all primitive polynomials of degree six. To compare the efficiency, we report on results obtained from FPGA (Field Programmable Gate Array) implementations. To the best of our knowledge, no similar study has been given in the literature. We observe that using the primitive trinomial y6+y+1 reduces the number of 2-input XOR gates up to 11.7% and the number of XOR gates × Delay metrics up to 13.2% with respect to the worst-case implementation. Therefore, the choice of primitive polynomial can profoundly impact the efficiency of such an implementation, and should be carefully considered.

Efficiency estimation and hardware implementation of solar PV module system assisted by using surface plasmon resonance sensor

This article presents a multi-mode approach for controlling and optimizing the efficiency of solar photovoltaic systems, as well as for analyzing the response output of optical sensing systems. Solar energy has been detected efficiently in this paper using a surface plasmon chip. Initially, the dual axis tracking system was designed and manufactured according to the standard procedure outlined in the literature. The primary factors affecting the efficiency of a photovoltaic panel are proper site heating and panel cleaning. As a result, the proposed system is aimed at increasing the efficiency of photovoltaic panels by addressing the aforementioned issues. Dual axis tracking ensures that the irradiance is always perpendicular to the photovoltaic panel. Additionally, the cooling system mitigates losses caused by panel heating, and the cleaning system increases the PV panel's efficiency. The solar photovoltaic system's output is analyzed using an optical sensing system equipped with a surface plasmon resonance (SPR) sensor. To monitor and control the performance of a proposed prototype solar photovoltaic system using the Resbri Pi3 controller. The proposed system's efficiency is calculated experimentally and presented to confirm the prototype's efficiency. The result is analyzed in the optical domain by the SPR sensor chip.

Neuromorphic computing with hybrid CNN–Stochastic Reservoir for time series WiFi based human activity recognition

Wi-Fi Channel State Information (CSI) based human activity recognition (HAR) which using channel disturbances caused by signal reflection is a novel way of environment sensing and motion recognition. The collected channels characteristics are heavily influenced by the environment, human activity patterns and subject’s weight and height. These signal variations reflected from body components are mainly affected by static multipath effects comprises random noise and behave differently in individuals, and thus an active field of research. To reach further for achieving automated real-time classification, lower computational cost and easy adaptability to hardware are necessary. In this work, a CSI-based HAR with hybrid framework, Convolutional Neural Network (CNN)-Stochastic Reservoir (SR) (CNN-SR) has been proposed, enabling a subject adaptable and more efficient hardware implementation with minimal computational complexity. A subcarrier correlation matrix is first computed and portrayed in image without preprocessing based on the reflection of the raw CSI signal induced by human activities at regular intervals, allowing visual observation of whole pattern changes. The time-based features are subsequently extracted through CNN and these feature arrays are then feed into SR which based on stochastic spiking neural network (SSNN) in simple cycle reservoir architecture for template matching. SR offers attractive power savings over typical von Neumann systems, by doing stochastic computations. The proposed method has also been demonstrated that is capable for HAR based on partially captured signals. The signal pattern of each segment can be observed in a single sight and then employed for person-to-person template recognition. This enables HAR with minimal computational complexity and solving the inter-person variability concerns. The results demonstrate that the proposed CNN-SR achieves impressive performance in recognizing human activities and surpasses existing models with an average accuracy of 93.49%.