Efficient Hardware Architecture Research Articles

A survey of graph convolutional networks (GCNs) in FPGA-based accelerators

AbstractThis survey overviews recent Graph Convolutional Networks (GCN) advancements, highlighting their growing significance across various tasks and applications. It underscores the need for efficient hardware architectures to support the widespread adoption and development of GCNs, particularly focusing on platforms like FPGAs known for their performance and energy efficiency. This survey also outlines the challenges in deploying GCNs on hardware accelerators and discusses recent efforts to enhance efficiency. It encompasses a detailed review of the mathematical background of GCNs behind inference and training, a comprehensive review of recent works and architectures, and a discussion on performance considerations and future directions.

Fault-Tolerant Operation of Bosonic Qubits with Discrete-Variable Ancillae

Fault-tolerant quantum computation with bosonic qubits often necessitates the use of noisy discrete-variable ancillae. In this work, we establish a comprehensive and practical fault-tolerance framework for such a hybrid system and synthesize it with fault-tolerant protocols by combining bosonic quantum error correction (QEC) and advanced quantum control techniques. We introduce essential building blocks of error-corrected gadgets by leveraging ancilla-assisted bosonic operations using a generalized variant of path-independent quantum control. Using these building blocks, we construct a universal set of error-corrected gadgets that tolerate a single-photon loss and an arbitrary ancilla fault for four-legged cat qubits. Notably, our construction requires only dispersive coupling between bosonic modes and ancillae, as well as beam-splitter coupling between bosonic modes, both of which have been experimentally demonstrated with strong strengths and high accuracy. Moreover, each error-corrected bosonic qubit is comprised of only a single bosonic mode and a three-level ancilla, featuring the hardware efficiency of bosonic QEC in the full fault-tolerant setting. We numerically demonstrate the feasibility of our schemes using current experimental parameters in the circuit-QED platform. Finally, we present a hardware-efficient architecture for fault-tolerant quantum computing by concatenating the four-legged cat qubits with an outer qubit code utilizing only beam-splitter couplings. Our estimates suggest that the overall noise threshold can be reached using existing hardware. These developed fault-tolerant schemes extend beyond their applicability to four-legged cat qubits and can be adapted for other rotation-symmetrical codes, offering a promising avenue toward scalable and robust quantum computation with bosonic qubits. Published by the American Physical Society 2024

Quantized CNN-based efficient hardware architecture for real-time hand gesture recognition

Nowadays, Convolutional Neural Networks (CNN) have been widely adopted for vision-based hand gesture recognition. Several existing CNN architectures designed for gesture classification perform well with high accuracy but require a high memory footprint and processing when deployed on low-power embedded devices. To address this issue, we present a quantized CNN-based efficient framework for meeting real-life hand gesture recognition challenges. The proposed quantized CNN is designed and implemented using the FINN-based pipelined streaming architecture on an FPGA. Moreover, hardware-based optimizations are used to minimize the resources needed and to achieve fast memory access. Experimental results demonstrate that the developed recognition system achieves an average accuracy of 92% on the numeral database of Indian Sign Language (ISL). Additionally, our optimized design attains an inference latency of 0.85ms for real-time single gesture prediction on the PYNQ Zynq Ultrascale (ZU) FPGA, consuming only 3.63 W of power. The proposed design achieves a better trade-off between hardware resource utilization and speed performance, over previous designs.

A Low Complexity Cooperative Spectrum Sensor for Cognitive –Radio Network Based on Approximate Computing

With the rapid growth of new wireless technologies, the issue of spectrum scarcity is becoming more prominent due to the limited availability of radio spectrum. Unutilized spectrum bands designated for primary users are known as spectrum holes or white spaces. Assigning these white spaces to secondary users can enhance spectrum utilization. Dynamic spectrum access is crucial for sharing licensed spectrum with secondary users, as opposed to static allocation policies which impede effective spectrum utilization. Spectrum sensing aims to detect licensed users in the spectrum to prevent interference from secondary users. Approximate computing has emerged as a strategy to enhance efficiency by leveraging the fault resilience of various applications. It introduces trade-offs in design optimizations, allowing for significant reductions in VLSI circuit area and energy consumption. A cooperative spectrum-sensing (CSS) algorithm based on approximate computing for cooperative cognitive-radio networks is proposed to reduce computational complexity for efficient hardware design while maintaining detection performance. The hardware-efficient architecture of the cooperative spectrum sensor (CSR) based on the CSS algorithm, combined with resource-sharing architectural optimization, outperforms existing implementations by occupying less area, achieving shorter sensing times, and displaying superior hardware efficiency. Keywords—Approximate Computing, Cooperative Spectrum Sensor(CSR), very-large scale integration(VLSI)

9.1 µW keyword spotting processor based on optimized MFCC and small‐footprint TENet in 28‐nm CMOS

AbstractThis letter proposes a low‐power keyword spotting (KWS) architecture based on a modified temporal efficient neural network (TENet) and a simplified mel‐frequency cepstrum coefficient (MFCC) algorithm. The optimized MFCC algorithm reduces the computational load by 82% for multiplications and 66% for additions. An efficient hardware architecture and data flow for TENet have been designed, resulting in a 3.1× reduction in the operating cycle compared to similar work. The parameter count and computational load are reduced by 3.7× and 2.8×, respectively, and the accuracy reaches 95.36% for ten keywords in the Google Speech Command Dataset (GSCD). Operating at a frequency of 16 KHz for MFCC and 100 KHz for NN accelerator on a 28 nm process, the power consumption overhead is 9.1 µW.

CNC: A lightweight architecture for Binary Ring-LWE based PQC

In lattice-based cryptography, Ring Learning with Errors (RLWE) is a computationally hard cryptographic problem, comprising three basic mechanisms i.e., key generation, encryption, and decryption. Binary Ring Learning with Error (BRLWE), a new variant of RLWE has been proposed recently to reduce the key size and computational complexity compared to previous RLWE-based schemes. Based on this BRLWE scheme, efficient hardware architectures have been obtained in recent works for lightweight applications. The key operation involved in this scheme is AB+C , where A and C are integer polynomials and B is a binary polynomial. This paper proposes an efficient hardware architecture for BRLWE-based scheme targeted for lightweight applications. The architecture computes the arithmetic operation AB+C, which includes polynomial multiplication and addition over the polynomial ring Zq/(xn+1). The proposed architecture is applied in two conditions, fixed and variable values of q. Experimental results show the architecture proposed has 50% less Area-Delay Product (ADP) and 20% less Power-Delay Product (PDP) compared to the recently reported work for n=256.

An FPGA‐based tool for supporting the design, modeling, and evaluation of hybrid object recognition systems on computer engineering courses

AbstractThe field of computer vision is characterized by computationally intensive algorithms and techniques with strict real‐time requirements. Field programmable gate arrays (FPGAs) are based on a concurrent paradigm which allows the design of efficient hardware architectures and has positioned FPGAs as an ideal device for implementing compute‐intensive applications. For this reason, FPGA technology has had a great impact in areas such as computer vision, where one of the main objectives for researchers working in this field is to create efficient automatic object recognition systems. Therefore, the need to provide undergraduates with the necessary skills to design FPGA‐based object recognition systems is evident. With this aim in mind, it is essential that specialization courses related to the design of these systems include the required resources for the student to apply the theoretical knowledge in solving practical problems. In this article, we present a development tool designed to help students, teachers, and researchers during the design‐modeling‐implementation process of object recognition systems based on FPGAs. The proposed tool operates under a modular approach as this facilitates the working on any of the phases of a recognition system and it is considered as a hybrid because the other phases can be developed using a software language. An empirical evaluation involving undergraduates enrolled in a Computer Engineering program was conducted to create a hardware architecture for the DAISY descriptor that uses the homogeneous features of objects immersed in images to produce an efficient representation. By considering similar descriptors such as Scale‐Invariant Feature Transform (SIFT) and Histogram of Oriented Gradients (HOG), DAISY is computed by convolving orientation maps instead of using weighted sums of gradient norms, which offers the same kind of invariance at a lower computational cost for the dense case. The results obtained during such an evaluation indicated that students consider this FPGA‐based tool to be an alternative to receiving practical training on designing systems for solving problems related to the area of object recognition.

Enhancing Real-time Simultaneous Localization and Mapping with FPGA-based EKF-SLAM's Hardware Architecture

Simultaneous Localization and Mapping enable a mobile robot that is exploring an uncharted environment to localize itself and calculate its path within the map. In the context of green technologies and applications, there is a growing need for efficient SLAM solutions that not only provide accurate localization and mapping but also minimize power consumption. EKF-SLAM is a SLAM solution based on the Extended Kalman Filter, it is well known In the domain of robotics for its ability to handle non-linear models, its ability to handle noise related to the sensors, and its extremely high degree of precision. To guarantee real-time performance, the EKF-SLAM implementation requires a high-performance hardware architecture. In light of this challenge, researchers are thinking about using parallel processing platforms like FPGAs, which can provide the required level of performance and meet strict constraints on physics, computing capacity, and electrical power. This study describes a hardware architecture's implementation design for EKF-SLAM on an FPGA platform. The entire design is built on the Cyclone 2 FPGA, which has a maximum speed of 114 MHz and 18577 LUTs, creating a highly efficient hardware architecture.

An efficient hardware architecture of integer motion estimation based on early termination and data reuse for Versatile video coding

The integer motion estimation (IME) involves high computational complexity and large amount of computation data due to the variable block sizes, and it is one of the most critical bottlenecks in video coding. The traditional algorithm for integer motion estimation loses search accuracy when simplifying the motion search process, or it becomes complex to pursue search accuracy, which is not conducive to video encoding and transmission. This paper presents a data reuse algorithm based on search window division, block splitting, the arrangement of search points in the Test Zone (TZ) search algorithm and block division. which divides pixel blocks of different sizes into several 8x8 pixel blocks and then reuses the overlapping 8x8 pixel blocks between adjacent search points of the Test Zone (TZ) search algorithm to reduce hardware resource consumption. By comparing the Sum of Absolute Differences (SAD) values of left and top pixel blocks with current pixel block, the integer motion estimation (IME) can be terminated in advance, reducing the computation complexity of integer motion estimation by over 70 %. Furthermore, the paper also presents a hardware architecture based on the data reuse algorithm, which can process 7680 × 4320@60fps videos at an operating clock frequency of 182.99 MHz, with lower resource consumption compared to similar hardware designs.

Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

In this article, a low-complexity VLSI architecture based on a radix-4 hyperbolic COordinate Rotion DIgital Computer (CORDIC) is proposed to compute the N{{rm th}} root and N{{rm th}} power of a fixed-point number. The most recent techniques use the radix-2 CORDIC algorithm to compute the root and power. The high computation latency of radix-2 CORDIC is the primary concern for the designers. N{{rm th}} root and N{{rm th}} power computations are divided into three phases, and each phase is performed by a different class of the proposed modified radix-4 CORDIC algorithms in the proposed architecture. Although radix-4 CORDIC can converge faster with fewer recurrences, it demands more hardware resources and computational steps due to its intricate angle selection logic and variable scale factor. We have employed the modified radix-4 hyperbolic vectoring (R4HV) CORDIC to compute logarithms, radix-4 linear vectoring (R4LV) to perform division, and the modified scaling-free radix-4 hyperbolic rotation (R4HR) CORDIC to compute exponential. The criteria to select the amount of rotation in R4HV CORDIC is complicated and depends on the coordinates X^j and Y^j of the rotating vector. In the proposed modified R4HV CORDIC, we have derived the simple selection criteria based on the fact that the inputs to R4HV CORDIC are related. The proposed criteria only depend on the coordinate Y^j that reduces the hardware complexity of the R4HV CORDIC. The R4HR CORDIC shows the complex scale factor, and compensation of such scale factor necessitates the complex hardware. The complexity of R4HR CORDIC is reduced by pre-computing the scale factor for initial iterations and by employing scaling-free rotations for later iterations. Quantitative hardware analysis suggests better hardware utilization than the recent approaches. The proposed architecture is implemented on a Virtex-6 FPGA, and FPGA implementation demonstrates 19% less hardware utilization with better error performance than the approach with the radix-2 CORDIC algorithm.

CRAFT: Criticality-Aware Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks

Deep Neural Networks (DNNs) have emerged as the most effective programming paradigm for computer vision and natural language processing applications. With the rapid development of DNNs, efficient hardware architectures for deploying DNN-based applications on edge devices have been extensively studied. Emerging Non-Volatile Memories (NVMs), with their better scalability, non-volatility and good read performance, are found to be promising candidates for deploying DNNs. However, despite the promise, emerging NVMs often suffer from reliability issues such as stuck-at faults, which decrease the chip yield/memory lifetime and severely impact the accuracy of DNNs. A stuck-at cell can be read but not reprogrammed, thus, stuck-at faults in NVMs may or may not result in errors depending on the data to be stored. By reducing the number of errors caused by stuck-at faults, the reliability of a DNN-based system can be enhanced. This paper proposes CRAFT, i.e., Criticality-Aware Fault-Tolerance Enhancement Techniques to enhance the reliability of NVM-based DNNs in the presence of stuck-at faults. A data block remapping technique is used to reduce the impact of stuck-at faults on DNNs accuracy. Additionally, by performing bit-level criticality analysis on various DNNs, the critical-bit positions in network parameters that can significantly impact the accuracy are identified. Based on this analysis, we propose an encoding method which effectively swaps the critical bit positions with that of non-critical bits when more errors (due to stuck-at faults) are present in the critical bits.

A New ACD-OMP Accelerator With Clustered Computing Look-Ahead

The orthogonal matching pursuit (OMP) has been widely explored to realize real-time compressed sensing (CS) reconstruction. The matrix pseudo-inverse of the least squares (LSs) is the most computationally complex operation in the OMP. Among various algorithms to realize this complex operation, the alternative Cholesky decomposition (ACD) algorithm performs the best. However, it typically involves a very long computation time due to its iterative procedure. To accelerate the ACD-OMP algorithm, a novel method called clustered computing look-ahead (CCL) is proposed. Inspired by the famous parallel carry look-ahead adder (CLA), CCL adds a propagation matrix to decouple the data dependency in ACD and then uses a clustering operator to transform the iterative computation of ACD into a pipelined and parallelized computation. This brief also proposes an efficient hardware architecture of the CCL-based ACD-OMP algorithm for CS reconstruction. The proposed algorithm is implemented on field programmable gate array (FPGA). For sparse signals with the same sparsity and length, the proposed implementation is 1.96 times faster than state-of-the-art work.

Design and implementation of hardware-efficient architecture for saturation-based image dehazing algorithm

Design and implementation of hardware-efficient architecture for saturation-based image dehazing algorithm

A temporally and spatially local spike-based backpropagation algorithm to enable training in hardware

Spiking neural networks (SNNs) have emerged as a hardware efficient architecture for classification tasks. The challenge of spike-based encoding has been the lack of a universal training mechanism performed entirely using spikes. There have been several attempts to adopt the powerful backpropagation (BP) technique used in non-spiking artificial neural networks (ANNs): (1) SNNs can be trained by externally computed numerical gradients. (2) A major advancement towards native spike-based learning has been the use of approximate BP using spike-time dependent plasticity with phased forward/backward passes. However, the transfer of information between such phases for gradient and weight update calculation necessitates external memory and computational access. This is a challenge for standard neuromorphic hardware implementations. In this paper, we propose a stochastic SNN based back-prop (SSNN-BP) algorithm that utilizes a composite neuron to simultaneously compute the forward pass activations and backward pass gradients explicitly with spikes. Although signed gradient values are a challenge for spike-based representation, we tackle this by splitting the gradient signal into positive and negative streams. The composite neuron encodes information in the form of stochastic spike-trains and converts BP weight updates into temporally and spatially local spike coincidence updates compatible with hardware-friendly resistive processing units. Furthermore, we characterize the quantization effect of discrete spike-based weight update to show that our method approaches BP ANN baseline with sufficiently long spike-trains. Finally, we show that the well-performing softmax cross-entropy loss function can be implemented through inhibitory lateral connections enforcing a winner take all rule. Our SNN with a two-layer network shows excellent generalization through comparable performance to ANNs with equivalent architecture and regularization parameters on static image datasets like MNIST, Fashion-MNIST, Extended MNIST, and temporally encoded image datasets like Neuromorphic MNIST datasets. Thus, SSNN-BP enables BP compatible with purely spike-based neuromorphic hardware.

Configurable Encryption and Decryption Architectures for CKKS-Based Homomorphic Encryption.

With the increasing number of edge devices connecting to the cloud for storage and analysis, concerns about security and data privacy have become more prominent. Homomorphic encryption (HE) provides a promising solution by not only preserving data privacy but also enabling meaningful computations on encrypted data; while considerable efforts have been devoted to accelerating expensive homomorphic evaluation in the cloud, little attention has been paid to optimizing encryption and decryption (ENC-DEC) operations on the edge. In this paper, we propose efficient hardware architectures for CKKS-based ENC-DEC accelerators to facilitate computations on the client side. The proposed architectures are configurable to support a wide range of polynomial sizes with multiplicative depths (up to 30 levels) at a 128-bit security guarantee. We evaluate the hardware designs on the Xilinx XCU250 FPGA platform and achieve an average encryption time 23.7× faster than that of the well-known SEAL HE library. By reducing time complexity and improving the hardware utilization of cryptographic algorithms, our configurable CKKS-supported ENC-DEC hardware designs have the potential to greatly accelerate cryptographic processes on the client side in the post-quantum era.

Accelerated FPGA-Based Vector Directional Filter for Real-Time Color Image Denoising with Enhanced Performance

This paper presents an accelerated implementation of the Vector Directional Filter (VDF) on a Field Programmable Gate Array (FPGA) for real-time denoising of color images. The VDF effectively suppresses noise while preserving edges and fine details, making it ideal for a range of applications such as satellite and multispectral biomedical imaging. However, the filter's high computational complexity poses challenges for real-time processing. Existing solutions either fail to meet real-time execution requirements or compromise image quality through hardware implementation approximations. To overcome these challenges, we first model the VDF using C/C++ programming, and subsequently design an efficient floating-point hardware architecture employing the High-Level Synthesis (HLS) flow. Optimal directives are selected using the Xilinx Vivado HLS tool. The VDF architecture is then integrated as a coprocessor with the Cortex-A53 hardcore processor in the XCZU9EG FPGA. To enhance data bandwidth between software and hardware components, three Direct Memory Access (DMAs) units are utilized to transfer three image lines in parallel. Furthermore, internal memory is implemented on the XCZU9EG FPGA, providing increased flexibility for managing the restored image. The VDF Software/Hardware (SW/HW) design's robustness and accuracy are validated through experimental studies on the ZCU102 board. Our design accelerates the filtering process by 21 times, maintaining visual quality and effectively removing noise from color images compared to the VDF SW design. Additionally, our solution outperforms existing approaches in terms of filtered image quality and processing time, showing a 24% improvement in the worst-case scenario.

Soft Decision Decoding with Cyclic Information Set and the Decoder Architecture for Cyclic Codes

The soft decision decoding algorithm for cyclic codes, especially the maximum likelihood (ML) decoding algorithm, can obtain significant performance superior to that of algebraic decoding, but the complexity is much higher. To deal with this problem, an improved soft decision decoding algorithm based on a cyclic information set and its efficient implementation architecture are proposed. This algorithm employs the property of the cyclic codes to generate a series of cyclic information sequences by circularly shifting, constructing the cyclic information set. Then, a limited number of candidate information sequences are efficiently generated using an iterative computation method, and the candidate codewords are generated using the very concise encoding method of the cyclic codes. Furthermore, the efficient hardware architecture based on systolic arrays is also proposed to generate candidate information sequences and to select the optimal candidate codewords. An emulation platform is constructed to verify the error correction performance and to determine the optimal decoder parameters. Emulation results indicate that, with appropriate parameter selection, the proposed decoding algorithm can achieve a bit error rate approaching the ML performance while maintaining low complexity.

Silicon Photonic Phase-Diverse Receiver Enabling Transmission of >Net 250 Gbps/λ Over 40 km for High-Speed and Low-Cost Short-Reach Optical Communications

The fast growth of data traffic in short-reach optical communications drives the demand for high-speed and low-cost optical modules. Here we demonstrate a silicon photonic (SiP) phase-diverse receiver based on our recently proposed asymmetric self-coherent detection (ASCD) scheme with Mach-Zehnder interferometers (MZI). The SiP MZI-ASCD receiver has a hardware-efficient architecture and recovers complex double-sideband signals via the beatings between a signal portion and a delayed signal portion from an asymmetric MZI using only 2 single-ended photodiodes and 2 analog-to-digital converters. The removal of the local oscillator in the direct detection receiver enables low-cost uncooled lasers, whereas the phase diversity closes the gap with coherent detection in terms of electrical spectral efficiency (ESE). Using a SiP MZI-ASCD receiver with a 15 ps delay, we detect a 60 Gbaud single-polarization 16-QAM signal transmitted over 40 km of single-mode fiber (SMF) below 20% overhead (OH) SD-FEC threshold of 2×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> with a net bit rate of 200 Gbps and a record net ESE of 5.86 b/s/Hz per wavelength per polarization. Using a SiP MZI-ASCD receiver with a different delay of 7.5 ps, transmission of single-polarization 16-QAM DSB signal up to 80 Gbaud over 40 km is achieved below 24% OH SD-FEC threshold of 4.5×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> with a record net bit rate of 258 Gbps and a net ESE of 5.31 b/s/Hz per wavelength per polarization.

An Area-Efficient Accelerator for Non-Maximum Suppression

Non-maximum suppression (NMS) is an essential part of the post-processing of object detectors. Most object detection models require NMS algorithms to filter overlapping candidate boxes belonging to the same object and reserve the box that best represents the object as the object representative box. However, the hardware for the standard NMS algorithm has some disadvantages, such as high complexity (especially when box numbers are significant), high latency, large area, and high power consumption. To solve these problems, we propose an efficient parallel hardware architecture, which uses a new sorting circuit with a ping-pong buffer and a new retention mechanism of the candidate box for the new NMS algorithm called distance over side-NMS (DoS-NMS). This architecture uses a PE group with a voting mechanism to simplify the algorithm for reducing the latency and area. Additionally, the PE group computes the DoS (non-intersection over union) of the candidate box and multiple object representatives in parallel, significantly reducing algorithm complexity and memory access cost. Experiments indicated that the algorithm runs on the chip with area of 0.75mm2, power consumption of 68.41 mW, and normalized area efficiency that is 3.72 and 4.84 times higher than the two state-of-the-art methods, respectively.

Hardware Architecture of a QAM Receiver for Short-Range Optical Communications

Short-reach optical fiber communications systems aim to achieve high throughput, in the order of tens of Gbps. The implementation of these high-speed systems requires parallel processing, which makes low-complexity designs of their subsystems a key to the successful large-scale deployment of this technology. Half-Cycle Nyquist Subcarrier Modulation (HC-SCM) was originally suggested for these systems with the goal of using as much bandwidth as possible and, therefore, achieving high communication rates. Recently, Oversampled Subcarrier Modulation (OVS-SCM) was proposed as an alternative more computational efficient than HC-SCM and also with a better spectral efficiency. This paper proposes a hardware-efficient architecture for an OVS-SCM receiver, which takes into account the inherent parallel processing of these systems. This receiver takes 16 samples in parallel from a 5 GSa/s analog-to-digital converter with a 3.2 GHz 3 dB bandwidth. Design solutions for the frame detection block, the mixer, the resampler, the fractional interpolator, the matched filter and the timing estimator are presented. Our results show that, compared to the HC-SCM receiver, this proposal reduces the computational load of the downconverter stages by 90%. FPGA implementation results are given to demonstrate that our proposal can be implemented in state-of-the-art devices.