Efficient Field Programmable Gate Array Research Articles

End-to-end codesign of Hessian-aware quantized neural networks for FPGAs

We develop an end-to-end workflow for the training and implementation of co-designed neural networks (NNs) for efficient field-programmable gate array (FPGA) hardware. Our approach leverages Hessian-aware quantization (HAWQ) of NNs, the Quantized Open Neural Network Exchange (QONNX) intermediate representation, and the hls4ml tool flow for transpiling NNs into FPGA firmware. This makes efficient NN implementations in hardware accessible to nonexperts, in a single open-sourced workflow that can be deployed for real-time machine-learning applications in a wide range of scientific and industrial settings. We demonstrate the workflow in a particle physics application involving trigger decisions that must operate at the 40 MHz collision rate of the CERN Large Hadron Collider (LHC). Given the high collision rate, all data processing must be implemented on FPGA hardware within the strict area and latency requirements. Based on these constraints, we implement an optimized mixed-precision NN classifier for high-momentum particle jets in simulated LHC proton-proton collisions.

Rapid Prototyping and Hardware-In-the-Loop Verification of Enhanced Sliding Mode Control of an Asynchronous Machine Using a Xilinx System Generator and an FPGA-Zynq Board

This article describes rapid prototyping using the Xilinx system generator (XSG) of a direct field oriented control (DFOC) strategy based on improved super twisting sliding mode controllers (ISTSMCs) of an asynchronous machine to succeed a hardware implementation on a field programmable gate array (FPGA) board. The main goal is to enhance regulation loops governing rotor speed, rotor flux, and stator current components within the classical DFOC structure. These ISTSMCs replace integral proportional controllers, resulting in improved system dynamics, faster speed and torque responses, and heightened robustness against load and rotor resistance variations, surpassing other control methods. Additionally, the article aims to implement this DFOC-ISTSMC method on an FPGA board to reduce control system sampling time and loop delays, leveraging the FPGA’s parallel processing capabilities. The hardware architecture is designed using XSG in the MATLAB/Simulink environment, enabling effective simulation, testing, discrete algorithm creation, and VHDL code generation for FPGA implementation via the hardware-in-the-loop (HIL) process. Assessment involves digital simulation studies and HIL processes using XSG with a Xilinx FPGA Zynq 7000 under MATLAB/Simulink, demonstrating improved system performance, reduced time delays, and efficient FPGA utilization. This approach validates the effectiveness of the proposed DFOC-ISTSMC algorithm in enhancing control strategy for asynchronous machines.

Boosting general-purpose stream processing with reconfigurable hardware

AbstractReconfigurable devices such as field-programmable gate arrays (FPGAs) offer flexible solutions to workload acceleration with high energy efficiency. Despite such a potential advantage, they often reveal hard to program by application programmers. High-level synthesis languages have been developed to provide higher-level abstractions, allowing the developers to define the FPGA behavior using an imperative programming approach based on C/C++ languages. However, such approaches still leave the developer with the responsibility to harness the low-level optimizations required to develop efficient FPGA programs. Along this line, this paper introduces , a framework helping programmers to develop FPGA-accelerated data stream processing (DSP) applications. The approach provides a high-level Python API to develop the data-flow graph of operators, which is automatically translated into an efficient Vitis source code targeting Xilinx devices. The execution of the bitstreams implementing two benchmark applications showcases the efficiency of using FPGAs for DSP workloads. In general, provides, with a reasonable time-to-solution, higher performance compared with state-of-the-art DSP frameworks.

Ferroelectric FET-based context-switching FPGA enabling dynamic reconfiguration for adaptive deep learning machines.

Field programmable gate array (FPGA) is widely used in the acceleration of deep learning applications because of its reconfigurability, flexibility, and fast time-to-market. However, conventional FPGA suffers from the trade-off between chip area and reconfiguration latency, making efficient FPGA accelerations that require switching between multiple configurations still elusive. Here, we propose a ferroelectric field-effect transistor (FeFET)-based context-switching FPGA supporting dynamic reconfiguration to break this trade-off, enabling loading of arbitrary configuration without interrupting the active configuration execution. Leveraging the intrinsic structure and nonvolatility of FeFETs, compact FPGA primitives are proposed and experimentally verified. The evaluation results show our design shows a 63.0%/74.7% reduction in a look-up table (LUT)/connection block (CB) area and 82.7%/53.6% reduction in CB/switch box power consumption with a minimal penalty in the critical path delay (9.6%). Besides, our design yields significant time savings by 78.7 and 20.3% on average for context-switching and dynamic reconfiguration applications, respectively.

A new design of a digital filter for an efficient field programmable gate array using quantum dot technology

Digital filtering algorithms are most frequently used to implement generic-based Field-programmable gate arrays (FPGAs) chips, which are used for higher sampling rates. In the filtering structure, delay and occupied areas play a vital role. Since the existing structures suffered from shortcomings such as high delay and high occupied area, implementing a high-performance digital filter circuit with high speed and low occupied area based on unique technology can significantly improve the performance of whole FPGA structures. One of the best technologies to implement this vital structure to solve these shortcomings is quantum-dot cellular automata (QCA) technology. This paper presents several new efficient full adders for digital filter applications based on quantum technology, including a multiplier, AND gate, and accumulator. The QCADesigner 2.0.3 tool is used to create and validate the suggested designs. According to the results, all designed circuits have simple structures with few quantum cells, low area, and low latency.

A compact and efficient AES-32GF for encryption in small IoT devices

The phenomenal growth of resource constrained devices in IoT set ups has motivated the researchers to develop solutions for securing information flow. In this paper, we present a compact and efficient field programmable gate array (FPGA) implementation of AES with 32-bit data-path named, AES-32GF. The implementation is carried out on different Xilinx FPGAs. In FPGAs, utilization of slices and look up tables (LUTs) reflect on the compactness of the design. Numerical results show that lesser resources are required with smaller data path in comparison with the original standard. With the help of data path compression and Galois field implementation of the s-box resource consumption is minimized. S-box is the most resource consuming component in the AES structure. In our implementation, Artix-7 series FPGA for the same. It results in significant resource savings. In comparison to unrolled AES-128 architecture, it achieves 87 % resource savings. With 595 slices and 2.004 Gbps throughput, AES-32GF cipher achieves an efficiency of 3.37 Mbps/slice. It outperforms other designs in terms of efficiency.•A compact and efficient FPGA implementation of AES with 32-bit data-path has been proposed.•The proposed design utilizes data path compression and Galois field implementation of the s-box to minimize resource consumption.•With 595 slices and 2.004 Gbps throughput, AES-32GF cipher achieves an efficiency of 3.37 Mbps/slice.

Quantum AI simulator using a hybrid CPU–FPGA approach

The quantum kernel method has attracted considerable attention in the field of quantum machine learning. However, exploring the applicability of quantum kernels in more realistic settings has been hindered by the number of physical qubits current noisy quantum computers have, thereby limiting the number of features encoded for quantum kernels. Hence, there is a need for an efficient, application-specific simulator for quantum computing by using classical technology. Here we focus on quantum kernels empirically designed for image classification and demonstrate a field programmable gate arrays (FPGA) implementation. We show that the quantum kernel estimation by our heterogeneous CPU–FPGA computing is 470 times faster than that by a conventional CPU implementation. The co-design of our application-specific quantum kernel and its efficient FPGA implementation enabled us to perform one of the largest numerical simulations of a gate-based quantum kernel in terms of features, up to 780-dimensional features. We apply our quantum kernel to classification tasks using the Fashion-MNIST dataset and show that our quantum kernel is comparable to Gaussian kernels with the optimized hyperparameter.

Fast Adaptive Spectrum Sensing Using Hardware Optimized, Cell Averaging Estimation for Cognitive Radio and Radar Applications

This article describes a technique that enables real-time spectrum sharing by rapidly sensing the spectrum and selecting available frequencies that a system may use for operation. Hardware optimized, cell averaging estimation (HO-CAE) is a method that uses a snapshot of the spectral environment to calculate a dynamic decision threshold that can be used by the fast spectrum sensing (FSS) algorithm to detect available spectrum. This energy detection technique is adaptive as it calculates a new threshold for each spectrum snapshot. A statistical derivation of HO-CAE will be provided with an analysis of probability of false alarm and probability of detection performance for noise only cases and in the presence of a 5 G downlink signal. Efficient field programmable gate array (FPGA) implementations of HO-CAE and FSS that enable real-time operation are presented.

CCSDS 131.2-B-1 Serial Concatenated Convolutional Turbo Decoder Architecture for Efficient FPGA Implementation

Most of the turbo encoding schemes at standards are parallel-based, so different architectures for efficient implementation are common in the literature. However, a serial turbo decoder is not that common. This scheme is used in CCSDS 131.2-B-1 standard, which is attracting much of attention recently due to its higher performance for satellite communications. In this paper, an efficient architecture for the decoder is proposed and analyzed. It is intended to show an architecture that can be modeled in a circuit description language (such as VHDL and Verilog) in such a way that it can be easily implemented on a Field Programmable Gate Array (FPGA). This work describes in detail this architecture explaining the encoding operations that are performed at the transmitter and then, how to undo them at the receiver. The proposed algorithm works by using independent components to divide the tasks and to obtain a pipeline architecture to improve the efficiency. The results of simulating and implementing the proposed architecture on a Xilinx Zynq UltraScale+ RFSoC ZCU28DR board with XCZU28DR-2FFVG1517E RFSoC are shown. The final results presented demonstrate how the hardware operations give equivalent results to the software simulation and do not consume board resources aggressively as usually the turbodecoder does.

An efficient field programmable gate arrays based real‐time implementation of smooth variable structure filter to estimate the state of charge of Li‐ion battery in electric vehicle application

The computational efficiency is a challenging task in the real-time implementation of battery State of Charge (SoC) estimation algorithms in Electric Vehicle (EV) application. This study proposes for the first time a pure hardware architecture of a Smooth Variable Structure Filter (SVSF) to estimate the SoC of a lithium-ion battery in an EV. The proposed embedded architecture is implemented on a Xilinx Zynq-7000 field programmable gate arrays board without using any soft-core, and validated with real-time tests carried out on a 20 Ah NMC battery with nominal voltage about 3.65 V. The whole embedded architecture of the SVSF needs a reduced execution time in the range of 921 ns, and it consumes only 466 mW. The average estimation errors of the SoC and battery voltage at different temperatures are kept within 4.95% and 2.35% respectively. The successful convergence of the algorithm and the accurate results obtained in different circumstances, prove the practicability and computational efficiency of the proposed hardware architecture.

Demystifying the Soft and Hardened Memory Systems of Modern FPGAs for Software Programmers through Microbenchmarking

Both modern datacenter and embedded Field Programmable Gate Arrays (FPGAs) provide great opportunities for high-performance and high-energy-efficiency computing. With the growing public availability of FPGAs from major cloud service providers such as AWS, Alibaba, and Nimbix, as well as uniform hardware accelerator development tools (such as Xilinx Vitis and Intel oneAPI) for software programmers, hardware and software developers can now easily access FPGA platforms. However, it is nontrivial to develop efficient FPGA accelerators, especially for software programmers who use high-level synthesis (HLS). The major goal of this article is to figure out how to efficiently access the memory system of modern datacenter and embedded FPGAs in HLS-based accelerator designs. This is especially important for memory-bound applications; for example, a naive accelerator design only utilizes less than 5% of the available off-chip memory bandwidth. To achieve our goal, we first identify a comprehensive set of factors that affect the memory bandwidth, including (1) the clock frequency of the accelerator design, (2) the number of concurrent memory access ports, (3) the data width of each port, (4) the maximum burst access length for each port, and (5) the size of consecutive data accesses. Then, we carefully design a set of HLS-based microbenchmarks to quantitatively evaluate the performance of the memory systems of datacenter FPGAs (Xilinx Alveo U200 and U280) and embedded FPGA (Xilinx ZCU104) when changing those affecting factors, and we provide insights into efficient memory access in HLS-based accelerator designs. Comparing between the typically used soft and hardened memory systems, respectively, found on datacenter and embedded FPGAs, we further summarize their unique features and discuss the effective approaches to leverage these systems. To demonstrate the usefulness of our insights, we also conduct two case studies to accelerate the widely used K-nearest neighbors (KNN) and sparse matrix-vector multiplication (SpMV) algorithms on datacenter FPGAs with a soft (and thus more flexible) memory system. Compared to the baseline designs, optimized designs leveraging our insights achieve about \( 3.5\times \) and \( 8.5\times \) speedups for the KNN and SpMV accelerators. Our final optimized KNN and SpMV designs on a Xilinx Alveo U200 FPGA fully utilize its off-chip memory bandwidth, and achieve about \( 5.6\times \) and \( 3.4\times \) speedups over the 24-core CPU implementations.

Resources and Power Efficient FPGA Accelerators for Real-Time Image Classification.

A plethora of image and video-related applications involve complex processes that impose the need for hardware accelerators to achieve real-time performance. Among these, notable applications include the Machine Learning (ML) tasks using Convolutional Neural Networks (CNNs) that detect objects in image frames. Aiming at contributing to the CNN accelerator solutions, the current paper focuses on the design of Field-Programmable Gate Arrays (FPGAs) for CNNs of limited feature space to improve performance, power consumption and resource utilization. The proposed design approach targets the designs that can utilize the logic and memory resources of a single FPGA device and benefit mainly the edge, mobile and on-board satellite (OBC) computing; especially their image-processing- related applications. This work exploits the proposed approach to develop an FPGA accelerator for vessel detection on a Xilinx Virtex 7 XC7VX485T FPGA device (Advanced Micro Devices, Inc, Santa Clara, CA, USA). The resulting architecture operates on RGB images of size or sliding windows; it is trained for the “Ships in Satellite Imagery” and by achieving frequency 270 MHz, completing the inference in 0.687 ms and consuming 5 watts, it validates the approach.

An efficient packet parser architecture for software-defined 5G networks

Software-defined networks (SDN) has emerged with the capability to program in order to enhance flexibility, management, and testing of new ideas in the next generation of networks by removing current network limitations. Network virtualization and functionalization are critical elements supporting the delivery of future network services, especially in 5G networks. With the integration of virtualization and functionalization, network resources can be provisioned on-demand, and network service functions can be composed and chained dynamically to cater to various requirements. 5G networks are expected to rely heavily on SDN, which has been widely applied in core network design. To have a software-defined 5G network, not only is new spectrum and interface needed from SDN, but also a programmable and efficient hardware infrastructure is required. Admittedly, hardware components and infrastructure play an important role in supporting 5G networks. In other words, the software-defined 5G network data plane must have the required flexibility and programmability to support upcoming needs and technologies. Technological solutions need to respond to actual requests in infrastructure. Packet parsers in the data plane of software-defined 5G networks are one of the most important components because of the variation in the type of network headers and protocols. Each SDN switch needs to identify headers for processing input packets in the data plane, where the packet parser operates. Multiple implementations of packet parsers have been done on different substrates that occupy large hardware resources and areas on chip. However, they are not suitable for software-defined 5G networks. Certain architectures have been presented for packet parsing, aimed at accelerating the process of header parsing, however no attention has been paid toward reducing the area and the volume of the needed hardware resources and programmability in the data plane. This paper presents a new and efficient architecture for packet parsers on Field Programmable Gate Arrays (FPGA), called Efficient FPGA Packet Parser (EFPP) in a designed software-defined 5G network. This architecture emphasizes the removal of Ternary Content Addressable Memory (TCAM) to decrease hardware resources and efficiency in the data plane. Moreover, this architecture uses the chip’s processing speed and reconfiguration capabilities to support new protocols and network headers while maintaining flexibilities on software-defined 5G networks. EFPP is applied to chips on FPGA Xilinx ZedBoard Zynq, and the resources consumed around 7.5% LookUp Table, 1.9% Flip-Flops, and 5.8% of the memory. EFPP was also more area efficient. According to our results, EFPP would reduce the area and volume of hardware compared to other peer works.

Field Programmable Gate Array based elliptic curve Menezes‐Qu‐Vanstone key agreement protocol realization using Physical Unclonable Function and true random number generator primitives

The trust, authenticity and integrity of Internet-of-Things (IoT) systems are heavily reliant on Physical Unclonable Functions (PUFs) and True random number generators (TRNGs). The PUF and TRNG produce device intrinsic digital signatures and random binary sequences, which are used for cryptographic key generation, key agreement/exchange, device authentication, cloning prevention etc. This article reports an efficient Field Programmable Gate Array (FPGA)-based realization of elliptic curve Menezes-Qu-Vanstone (ECMQV)-authenticated key agreement protocol using PUF and TRNG with very competitive area-throughput trade-offs. The key agreement protocols, which establish a shared secret key between two IoT devices, make use of PUF and TRNG primitives for the long- and short-term secret keys generation while the elliptic curve is employed for public key generated from the corresponding secret key. The performance of the protocol is investigated on FPGAs. The authors' implementation of the ECMQV protocol takes 1.802 ms using 18852 slices on Artix-7 FPGA.

A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the Look-Up Table (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.

An efficient field programmable gate array based hardware architecture for efficient motion estimation with parallel implemented genetic algorithm

SummaryThe main idea of this article is to propose a hardware design of block matching (BM) algorithm for an efficient motion estimation (ME) strategy in a field programmable gate array platform based on a parallel implemented genetic algorithm (GA). Easiness and the effectiveness of the BM algorithm while implementing have a major drawback of low quality and computationally cost expensive during the process of ME. Therefore, here in this article, we suggest GA based BM for a quick and cost‐effective computation of motion vectors, without negotiating the quality factor. The ME carried out for various video sequences is implemented by using Xilinx ISE Design Suite 14.1. Delay, time, area, power, PSNR, MSE, SNR, SSIM, and NRMSE are the metrics used for analyzing the performance, and the simulation outcome shows that this parallel implemented BM architecture design shows an exotic improvement in time, quality and in utilization of power on estimating the motion than that of the conventional designs.

Efficient FPGA Implementation of a Dual-Frequency GNSS Receiver with Robust Inter-Frequency Aiding.

Multiple frequency global navigation satellite system (GNSS) has become more complex due to the existence of extra channels. Typically, auxiliary methods are used to synchronize the second signals at other bands by aiding the acquired channel parameters. However, there are critical limitations because the reception of GNSS signals is subject to uncertainties due to noise carrier injection or circuit interference. The relationship between the two Doppler frequencies can be affected by uncertainties. Therefore, we aimed to implement an efficient dual-frequency field-programmable gate array (FPGA), performing a direct aid tracking method for the secondary channel to achieve resource efficiency and inner aid robustness. A robust estimator that directly links two loops in the two bands is proposed. In this scheme, (1) a robust estimator able to cope with uncertainty; (2) a primary tracking scheme to obtain the error boundary, and (3) a tracked bit-boundary for the initial code phase of the second channel are used. Based on experiments on the FPGA, the robust channel link can achieve direct aid tracking, and 31.02% of the original hardware resources from the aided acquisition module were released satisfactorily.

An Efficient FPGA-Based Hardware Accelerator for Convex Optimization-Based SVM Classifier for Machine Learning on Embedded Platforms

Machine learning is becoming the cornerstones of smart and autonomous systems. Machine learning algorithms can be categorized into supervised learning (classification) and unsupervised learning (clustering). Among many classification algorithms, the Support Vector Machine (SVM) classifier is one of the most commonly used machine learning algorithms. By incorporating convex optimization techniques into the SVM classifier, we can further enhance the accuracy and classification process of the SVM by finding the optimal solution. Many machine learning algorithms, including SVM classification, are compute-intensive and data-intensive, requiring significant processing power. Furthermore, many machine learning algorithms have found their way into portable and embedded devices, which have stringent requirements. In this research work, we introduce a novel, unique, and efficient Field Programmable Gate Array (FPGA)-based hardware accelerator for a convex optimization-based SVM classifier for embedded platforms, considering the constraints associated with these platforms and the requirements of the applications running on these devices. We incorporate suitable mathematical kernels and decomposition methods to systematically solve the convex optimization for machine learning applications with a large volume of data. Our proposed architectures are generic, parameterized, and scalable; hence, without changing internal architectures, our designs can be used to process different datasets with varying sizes, can be executed on different platforms, and can be utilized for various machine learning applications. We also introduce system-level architectures and techniques to facilitate real-time processing. Experiments are performed using two different benchmark datasets to evaluate the feasibility and efficiency of our hardware architecture, in terms of timing, speedup, area, and accuracy. Our embedded hardware design achieves up to 79 times speedup compared to its embedded software counterpart, and can also achieve up to 100% classification accuracy.

Efficient FPGA-Based Real-Time Implementation of Model Predictive Control for Single-Phase Direct Matrix Converter

Finite control set model predictive control (FCS-MPC) is an optimal control strategy that solves user-defined objective functions to determine the best control action for the next time interval. Real-time implementations of model predictive control techniques are quite challenging for certain topologies due to computation complexities. In this paper, key aspects of achieving robust, reliable, and efficient field programmable gate arrays (FPGAs) based model predictive control are presented for single-phase direct matrix topology. The effectiveness of FPGA-based model predictive control is validated experimentally using an ALTERA Cyclone IV FPGA. Experimental results show that an effective load current control performance is obtained by taking advantage of pipelining capability of the FPGA device. The tradeoff between control bandwidth, FPGA resources, and hardware utilization is discussed.

Automatic offloading method of loop statements of software to FPGA

With Moore's law coming to an end, using hardware other than central processing units (CPUs), such as more energy efficient field-programmable gate arrays (FPGAs), has recently been increasing. However, when using heterogeneous hardware other than CPUs, barriers of technical skills, such as in using Open Computing Language (OpenCL), are high. Therefore, I previously proposed environment-adaptive software that enables automatic conversion, configuration, and high-performance operation of once-written code according to the hardware to be placed. Offloading of some applications to graphics processing units (GPUs) was automated previously. In this paper, I proposed an automatic offloading method of appropriate target loop statements of applications as the first step in offloading to FPGAs. I evaluated the effectiveness of the proposed method by applied it to multiple applications.