Efficient Debugging Research Articles

Backward Responsibility in Transition Systems Using General Power Indices

To improve reliability and the understanding of AI systems, there is increasing interest in the use of formal methods, e.g. model checking. Model checking tools produce a counterexample when a model does not satisfy a property. Understanding these counterexamples is critical for efficient debugging, as it allows the developer to focus on the parts of the program that caused the issue. To this end, we present a new technique that ascribes a responsibility value to each state in a transition system that does not satisfy a given safety property. The value is higher if the non-deterministic choices in a state have more power to change the outcome, given the behaviour observed in the counterexample. For this, we employ a concept from cooperative game theory – namely general power indices, such as the Shapley value – to compute the responsibility of the states. We present an optimistic and pessimistic version of responsibility that differ in how they treat the states that do not lie on the counterexample. We give a characterisation of optimistic responsibility that leads to an efficient algorithm for it and show computational hardness of the pessimistic version. We also present a tool to compute responsibility and show how a stochastic algorithm can be used to approximate responsibility in larger models. These methods can be deployed in the design phase, at runtime and at inspection time to gain insights on causal relations within the behavior of AI systems.

RevTPL: The Reversible Temporal Process Language

Reversible debuggers help programmers to find the causes of misbehaviours in concurrent programs more quickly, by executing a program backwards from the point where a misbehaviour was observed, and looking for the bug(s) that caused it. Reversible debuggers can be founded on the well-studied theory of causal-consistent reversibility, which only allows one to undo an action provided that its consequences, if any, are undone beforehand. Causal-consistent reversibility yields more efficient debugging by reducing the number of states to be explored when looking backwards. Till now, causal-consistent reversibility has never considered time, which is a key aspect in real-world applications. Here, we study the interplay between reversibility and time in concurrent systems via a process algebra. The Temporal Process Language (TPL) by Hennessy and Regan is a well-understood extension of CCS with discrete-time and a timeout operator. We define revTPL, a reversible extension of TPL, and we show that it satisfies the properties expected from a causal-consistent reversible calculus. We show that, alternatively, revTPL can be interpreted as an extension of reversible CCS with time.

Udon: Efficient Debugging of User-Defined Functions in Big Data Systems with Line-by-Line Control

Many big data systems are written in languages such as C, C++, Java, and Scala to process large amounts of data efficiently, while data analysts often use Python to conduct data wrangling, statistical analysis, and machine learning. User-defined functions (UDFs) are commonly used in these systems to bridge the gap between the two ecosystems. In this paper, we propose Udon, a novel debugger to support fine-grained debugging of UDFs. Udon encapsulates the modern line-by-line debugging primitives, such as the ability to set breakpoints, perform code inspections, and make code modifications while executing a UDF on a single tuple. It includes a novel debug-aware UDF execution model to ensure the responsiveness of the operator during debugging. It utilizes advanced state-transfer techniques to satisfy breakpoint conditions that span across multiple UDFs. It incorporates various optimization techniques to reduce the runtime overhead. We conduct experiments with multiple UDF workloads on various datasets and show its high efficiency and scalability.

FPGA Implementation of Vending Machine

This paper aims to create a coin processing system-based vending machine that can handle input coin values and dispense or return change as required, utilizing a single-state machine designed with the Mealy state machine model. To implement this design VHDL is used, which is a hardware description language capable of producing efficient and reliable system development. Xilinx VIVADO 2017.4 software tool is used to simulate and test the system, allowing for efficient debugging of FPGA designs. The system is deployed on a Nexys 4 DDR FPGA Board development board, enabling practical and robust implementation. This particular design offers great versatility, making it suitable for a wide range of applications, such as vending machines, parking meters, and other automated systems that require coin processing. The Mealy state machine model proves to be an efficient and reliable approach to coin processing, and the use of VHDL and FPGA board ensures a practical and effective implementation of the design.

F4Tele: FSO for data center network management and packet telemetry

The proliferation of bandwidth-hungry applications and services forces datacenter (DC) administrators to optimize the utilization of available resources. Precisely, the network share of management traffic (NMT) has grown significantly because DC networks are becoming more sophisticated and require a massive amount of data for efficient debugging and troubleshooting. Accordingly, we use free space optics communication (FSO) with wavelength division multiplexing (WDM) technology to build a flexible yet high-performance logical network responsible for NMT. The FSO-WDM can provide reconfigurable multi-terabit topology over indirect line-of-sight (LoS) links. Due to space and processing capacity reasons, we cannot offer direct connections from every NMT source to the network management cluster. Alternatively, the NMT sources are grouped together as each group is serviced for a duration of time matches its average arrival-rate. Since the NMT sources showed different arrival-rates, the hotspot racks are allocated with longer service time. The evaluation results show that F4Tele carried out a throughput 72% of the expensive solution (benchmark).

A Secured Data Prevention Method in Cloud Computing Process

This paper proposes protecting data by using data security and it is considered tointroducealteration, inspection, intrusion, and footage. Cloud computing may be a kind of online based computing that grants approaches of PC and various devices depending on resources and necessary information. It is an ideal that empowers entirely on the prevention and control of configurable computing resources. Now a days security is a major problem in developing cloud computing so efficient debugging of cloud computing is a successful model by security in cloud presentations. The present work is a part of cryptography in cloud computing for getting better information safety. Here we approach another security for cryptography to get secured information at cloud data centres.

Combinational Hybrid Signal Selection With Updated Reachability Lists for Post-Silicon Debug

Good knowledge of internal circuit states are crucial for efficient post-silicon debug. Due to the area, power, routing, and bandwidth limitations trace buffer-based design for debug hardware provides execution traces of a limited number of state elements which are then usually expanded through signal restoration. In this paper, we propose to record combinational execution traces and show that combined with signal restoration better knowledge of internal circuit states are obtained. Our experiment with benchmark circuits show that restoration quality in terms of state restoration ratio is improved up to 48% on average. Extending the solution space by, including combinational gates drastically increases signal selection runtime. Using hybrid signal selection methods, we also provide good tradeoff between restoration quality and runtime. By dynamically updating some metrics in state-of-the-art hybrid selection method, we achieve 65% reduction in runtime with only 2% penalty in solution quality. Using the proposed signal selection algorithms, designers can better explore the circuit states and achieve more efficient post-silicon debug.

P4DB: On-the-Fly Debugging for Programmable Data Planes

While extending network programmability to a more considerable extent, P4 raises the difficulty of detecting and locating bugs, e.g., P4 program bugs and missed table rules, in runtime. These runtime bugs, without prompt disposal, can ruin the functionality and performance of networks. Unfortunately, the absence of efficient debugging tools makes runtime bug troubleshooting intricate for operators. This paper is devoted to on-the-fly debugging of runtime bugs for programmable data planes. We propose P4DB, a general debugging platform that empowers operators to debug P4 programs in three levels of visibility with rich primitives. By P4DB, operators can use the watch primitive to quickly narrow the debugging scope from the network level or the device level to the table level, then use the break and next primitives to decompose match-action tables and finely locate bugs. We implement a prototype of P4DB and evaluate the prototype on two widely-used P4 targets. On the software target, P4DB merely introduces a small throughput penalty (1.3% to 13.8%) and a little delay increase (0.6% to 11.9%). Notably, P4DB almost introduces no performance overhead on Tofino, the hardware P4 target.

ErosLab: A modelling tool for soil tests

The focus of this paper is ErosLab, a useful tool for the development, analysis and application of constitutive models developed to solve the modelling problems inherent in soil tests. The ErosLab is programmed in the way of admixture programming with C#, MATLAB and FORTRAN, offering a powerful environment for various kinds of modelling soil tests. The proposed tool has six important features: (1) a mechanical calculator; (2) the ability to cover various kinds of soil tests; (3) a number of soil models with a user extension interface; (4) multiple methods of loading control; (5) comprehensive and efficient debugging; and (6) visualisation with graphical displays. Furthermore, the entire graphical user interface and usage instructions for the tool are briefly illustrated in simple and practical terms. Finally, three case studies are presented in which ErosLab was used, to highlight its performance in modelling tests for different soils.

Efficient Simulation of SoC based on Design Checkpointing for Efficient Debugging

Efficient Simulation of SoC based on Design Checkpointing for Efficient Debugging

Managing Trace Summaries to Minimize Stalls During Postsilicon Validation

On-chip trace buffers are increasingly being used for at-speed debug during postsilicon validation. The limited size of these buffers results in their frequent overflowing. In scenarios when such overflowing is not desirable, the chip is stalled, and the state data recorded in these buffers are transferred off-chip. Such frequent stalling significantly impedes efficient debugging. We propose a novel scheme to minimize the number of such stalls using a portion of the trace buffer to also store summaries of trace messages. We describe an overlapped trace buffer architecture that uses a reduced number of ports to capture tapered summaries where both detailed and summary versions of traces are stored simultaneously. We propose a simple hardware structure to generate two kinds of trace summaries— spatial and temporal —as specified by the validation engineer. We introduce a storage specification language that allows the validation engineer to unambiguously specify the information to be captured in these summaries to the debug hardware. We demonstrate that our proposal significantly reduces the number of stalls for off-chip transfer of captured traces in four bug scenarios that are representative of different classes of bugs encountered during postsilicon validation.

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Design methodology for on-chip-based processor debugger

Due to the increased complexity of modern embedded systems and time-to-market constraints, a debugger with efficient debugging functions is becoming increasingly necessary, and it plays an important role in the development of application systems. Accordingly, the implementation of efficient debug functionalities must a critical process in the design of a new processor. Since deeply embedded processor cores in a core-based system chip allow only restricted access for debugging its internal status, most recent processors employ the on-chip-based debug method that embeds special logic-supporting debug capabilities. In this paper, we propose an on-chip debug support logic that can be embedded into the processor core to support debug functions. Moreover, we describe an overall implementation method of the on-chip-based processor debugger based on the on-chip debug support logic, which includes a source-level debugger and an interface block. We designed an on-chip debug support logic, and embedded it into a target processor core. We used the GNU Project debugger (GDB) as the source-level debugger of the target processor core. An interface block that uses the remote debugging features of GDB was also developed and that includes a software module and a hardware board. We discuss all major design steps for implementing this on-chip-based processor debugger. We have successfully applied the proposed implementation method to develop the processor debugger for two new 32-bit RISC processors. In addition, we introduce another use of the on-chip-based processor debugger in the design of a processor-based system chip, which can facilitate simulation-based functional verification.

Software Reliability Growth Model with Efficient Debugging Involving Time Dependent Fault Content Function

ABSTARCT The paper presents NHPP software reliability growth model exhibiting efficient debugging phenomenon. In efficient debugging, cumulative faults corrected more than the faults responsible for software failures. Proposed model incorporates time dependent exponential fault content function and I/D pattern of learning process. Parameters are estimated by LSE and goodness of fit is performed. Determination of MSE and indicates model is fit better to given dataset. Finally software reliability has been analyzed.

Light-weight kernel instrumentation framework using dynamic binary translation

Mobile platforms such as Android and iOS, which are based on typical operating systems, have been widely adopted in various computing devices from smart phones even to smart TVs. Along with this, the necessity of kernel instrumentation framework has also grown up for efficient development and debugging of a kernel itself and its components. Although the existing approaches are providing some information about the kernel state including physical register value and primitive memory map, it is hard for the developers to understand and exploit the information. Moreover, the excessive analysis overhead in the existing approach makes them impractical to be used in real systems. Meanwhile, there have been a few studies on analyzing the user-level applications using dynamic binary translation and they are now widely used. In this paper, by extending this idea of dynamic binary translation for user-level applications to the kernel, we propose a new dynamic kernel instrumentation framework. Our framework focuses on the modules such as device drivers, rather than the kernel itself, since the modules comprise a large portion of OS development. Because of the frequent execution of kernel modules, the dynamic kernel instrumentation framework should guarantee the quality of the translated target code. However, costly optimizations to achieve high execution performance are rather harmful to the overall performance. Therefore, in order to improve performance of both translations, we suggest light-weight translator based on pseudo-machine instruction representation and tabular-base translation instead of typical intermediate representation. We implement our framework on Linux system, and our experimental evaluations show that it could quite effectively instrument the target with nominal overhead.

SOC HW/SW co‐verification based debugging technique

PurposeIncreasingly complex and sophisticated VLSI design, coupled with shrinking design cycles, requires shorter verification time and efficient debug method. Logic simulation provides SoC verification with full controllability and observability, but it suffers from very slow simulation speed for complex design. Using hardware emulation such as FPGA can have higher simulation speed. However, it is very hard to debug due to its poor visibility. SOC HW/SW co‐verification technique seems to draw a balance, but Design Under Test (DUT) still resides in FPGA and remains hard for debugging. The purpose of this paper is to study a run‐time RTL debugging methodology for a FPGA‐based co‐verification system.Design/methodology/approachThe debugging tools are embedded in HDL simulator using Verilog VPI callback, so signals of testbench and internal nodes of DUT can be observed in a single waveform and updated as simulation runs, making debugging more efficient. The proposed debugging method connects internal nodes directly to a PCI‐extended bus, instead of inserting extra scan‐chain logic, so the overhead for area is reduced.FindingsThis method provides internal nodes probing on an event‐driven co‐verification platform and achieves full observability for DUT. The experiment shows that, compared with a similar method, the area overhead for debug logic is reduced by 30‐50 per cent and compile time is shortened by 40‐70 per cent.Originality/valueThe proposed debugging technique achieves 100 per cent observability and can be applied to both RTL and gate‐level verification. The debugging tool is embedded into HDL simulator using Verilog VPI callback, so DUT signals are displayed together with testbench signals in the same waveform viewer. New value of DUT signal is read from FPGA whenever it changes, which allows run‐time debug.

Calibrating disaggregate economic models of agricultural production and water management

This paper describes calibration methods for models of agricultural production and water use in which economic variables can directly interact with hydrologic network models or other biophysical system models. We also describe and demonstrate the use of systematic calibration checks at different stages for efficient debugging of models. The central model is the California Statewide Agricultural Production Model (SWAP), a Positive Mathematical Programming (PMP) model of California irrigated agriculture. We outline the six step calibration procedure and demonstrate the model with an empirical policy analysis. Two new techniques are included compared with most previous PMP-based models: exponential PMP cost functions and Constant Elasticity of Substitution (CES) regional production functions. We then demonstrate the use of this type of disaggregated production model for policy analysis by evaluating potential water transfers under drought conditions. The analysis links regional production functions with a water supply network. The results show that a more flexible water market allocation can reduce revenue losses from drought up to 30%. These results highlight the potential of self-calibrated models in policy analysis. While the empirical application is for a California agricultural and environmental water system, the approach is general and applicable to many other situations and locations.

On-Chip Debug Architecture for Multicore Processor

Because of the intrinsic lack of internal-system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on-chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run-stop-type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG-based scanning operation. We apply this on-chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.

On-Chip Debug Architecture for Multicore Processor

Because of the intrinsic lack of internal-system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on-chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run-stop-type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG-based scanning operation. We apply this on-chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.

Efficient Debugging of Large Algorithmic Modelica Applications

AbstractModelica models often contain functions with algorithmic code. The fraction of algorithmic code is increasing since Modelica, in addition to equation-based modeling, is also used for embedded system control code and symbolic model transformations in compilers using the MetaModelica language extension. Thus, debugging of algorithmic Modelica code is becoming increasingly relevant.Our earlier work in debuggers for the algorithmic subset of Modelica used trace-based techniques which are very portable but turned out to have too much overhead for very large applications.The new debugger is the first Modelica debugger that can operate without trace information. Instead it communicates with a low-level C-language symbolic debugger, the Gnu debugger GDB, to directly extract information from a running executable, set and remove breakpoints, etc. This is made possible by the new bootstrapped OpenModelica compiler which keeps track of a detailed mapping from the high level Modelica code down to the generated C code compiled to machine code.The debugger is operational, supports browsing of both standard Modelica data structures and tree/list data structures, and operates efficiently on large applications such as the OpenModelica compiler with more than 100 000 lines of code.