Efficient Binary Decision Diagrams Research Articles

Reliability analysis of smart home sensor systems subject to competing failures

ZigBee and Bluetooth devices (particularly sensors) abound in smart home sensor systems (SHSSs), and they can only be connected to the network through gateways. Therefore, there exists functional dependence between these sensors and the corresponding gateway, where the failure of the gateway makes the connected sensors inaccessible or isolated. Two kinds of sensor failures can be distinguished in the SHSS: local failure that only affects the sensor itself (e.g., hardware failures) and propagated failure that affects other components and even causes the entire SHSS to fail (e.g., jamming attacks). Competitions exist between the gateway failure and propagated failures from the connected sensors in the time domain. Particularly, if the gateway fails before the propagated failures from the connected sensors, the propagated failures can be isolated and no longer affect other devices in the system; otherwise, the SHSS may fail due to the failure propagation effect. To address the influence of such competing failures, this paper proposes a new combinatorial method based on improved binary decision diagrams (BDDs) to analyze the reliability of SHSSs with competing failures. As compared to the existing method that involves generation of multiple reduced fault trees and their conversions to BDDs, the proposed method eliminates the process through an efficient BDD reduction technique. The efficiency and accuracy of the proposed method are discussed through an example SHSS.

Using Extended Logical Primitives for Efficient BDD Building

Binary Decision Diagrams (BDDs) have been used to represent logic models in a variety of research contexts, such as software product lines, circuit testing, and plasma confinement, among others. Although BDDs have proven to be very useful, the main problem with this technique is that synthesizing BDDs can be a frustratingly slow or even unsuccessful process, due to its heuristic nature. We present an extension of propositional logic to tackle one recurring phenomenon in logic modeling, namely groups of variables related by an exclusive-or relationship, and also consider two other extensions: one in which at least n variables in a group are true and another one for in which at most n variables are true. We add XOR, atLeast-n and atMost-n primitives to logic formulas in order to reduce the size of the input and also present algorithms to efficiently incorporate these constructions into the building of BDDs. We prove, among other results, that the number of nodes created during the process for XOR groups is reduced from quadratic to linear for the affected clauses. the XOR primitive is tested against eight logical models, two from industry and six from Kconfig-based open-source projects. Results range from no negative effects in models without XOR relations to performance gains well into two orders of magnitude on models with an abundance of this kind of relationship.

Reliability Analysis of IoT Networks with Community Structures

Network infrastructure and connectivity in the Internet of Things (IoT) applications are becoming increasingly complex and heterogeneous, opening up many challenges including reliability. Many real-world networks exhibit community structure, where the networked devices can be easily grouped into sets with dense internal connections but sparse connections between different sets. Examples of such community-structured networks can be found in diverse IoT applications such as smart grids, smart cities, and military systems. Due to these critical applications, reliability analysis is of great significance for robust and safe design and operation of IoT networks. In this paper, we present an efficient binary decision diagram (BDD)-based approach to analyze the reliability of an IoT network with community structure and subject to random link failures. As efficiency of the BDD-based approach heavily depends on the ordering of input variables, we make novel contributions by proposing efficient ordering heuristics for individual communities and the whole IoT network composed of multiple communities. Performance of the proposed ordering heuristics for IoT networks with either linear interconnection pattern or random interconnection pattern is investigated. As demonstrated through comprehensive experiments, the proposed ordering heuristics provide significantly better performance in model complexity than the traditional ordering heuristics.

Performability Analysis of k-to-l-Out-of-n Computing Systems Using Binary Decision Diagrams

Modern computing systems typically utilize a large number of computing nodes to perform coordinated computations in parallel or simultaneously. They can exhibit multiple performance states or levels due to statuses or failures of their consistent nodes. Performability analysis is concerned with assessing the probability that the computing system performs at a particular performance level. In the context of performability analysis, these computing systems can be modeled using k -to- l -out-of- n structures. This paper proposes new analytical methods based on binary decision diagrams (BDD) for the performability analysis of large computing systems with unrepairable computing nodes. A new and efficient BDD algorithm that makes full uses of the special k -to- l -out-of- n structure is first proposed for systems with computing node having identical computing powers. New simplification rules are further proposed to generate compact and canonical BDD models for systems with heterogeneous computing nodes characterized by different computing powers. Ordering heuristic is also explored to further reduce the size of BDD models. Examples are provided to illustrate the proposed BDD-based performability analysis methodology as well as its efficiency in analyzing large-scale computing systems.

An efficient algorithm for finding attractors in synchronous Boolean networks with biochemical applications

Self-organized systems, genetic regulatory systems and other living systems can be modeled as synchronous Boolean networks with stable states, which are also called state-cycle attractors (SCAs). This paper summarizes three classes of SCAs and presents a new efficient binary decision diagram based algorithm to find all SCAs of synchronous Boolean networks. After comparison with the tool BooleNet, empirical experiments with biochemical systems demonstrated the feasibility and efficiency of our approach.

NEW RESULTS TO BDD TRUNCATION METHOD FOR EFFICIENT TOP EVENT PROBABILITY CALCULATION

A Binary Decision Diagram (BDD) is a graph-based data structure that calculates an exact top event probability (TEP). It has been a very difficult task to develop an efficient BDD algorithm that can solve a large problem since its memory consumption is very high. Recently, in order to solve a large reliability problem within limited computational resources, Jung presented an efficient method to maintain a small BDD size by a BDD truncation during a BDD calculation. In this paper, it is first identified that Jung’s BDD truncation algorithm can be improved for a more practical use. Then, a more efficient truncation algorithm is proposed in this paper, which can generate truncated BDD with smaller size and approximate TEP with smaller truncation error. Empirical results showed this new algorithm uses slightly less running time and slightly more storage usage than Jung’s algorithm. It was also found, that designing a truncation algorithm with ideal features for every possible fault tree is very difficult, if not impossible. The so-called ideal features of this paper would be that with the decrease of truncation limits, the size of truncated BDD converges to the size of exact BDD, but should never be larger than exact BDD.

Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic

Synthesis of reversible and quantum logic has become an intensely studied topic in the last years. However, most synthesis methods are limited, since they rely on a truth table representation of the function to be synthesized. BDD-based synthesis offers an alternative. Here, reversible or quantum circuits are derived from a function given as Binary Decision Diagram (BDD) by substituting all nodes of the BDD with a cascade of Toffoli or elementary quantum gates, respectively. As a result, the application of the approach is not limited by the truth table of the function but by the (quite more efficient) BDD representation. Furthermore, many optimization techniques for BDDs exist which can be exploited.In this work, we evaluate the effect of three optimization methods for BDDs (namely shared nodes, complement edges, and advanced orderings) on the resulting reversible and quantum circuits. We describe in detail the adjustments, which have to be done to support these optimizations for synthesis, and discuss possible improvements and drawbacks. In a case study, the effects are experimentally evaluated. The results showed, that applying these optimization techniques leads to significant smaller circuits (with respect to number of gates and lines) in most of the cases.

FAST BDD TRUNCATION METHOD FOR EFFICIENT TOP EVENT PROBABILITY CALCULATION

A Binary Decision Diagram (BDD) is a graph-based data structure that calculates an exact top event probability (TEP). It has been a very difficult task to develop an efficient BDD algorithm that can solve a large problem since it is highly memory consuming. In order to solve a large reliability problem within limited computational resources, many attempts have been made, such as static and dynamic variable ordering schemes, to minimize BDD size. Additional effort was the development of a ZBDD (Zero-suppressed BDD) algorithm to calculate an approximate TEP. The present method is the first successful application of a BDD truncation. The new method is an efficient method to maintain a small BDD size by a BDD truncation during a BDD calculation. The benchmark tests demonstrate the efficiency of the developed method. The TEP rapidly converges to an exact value according to a lowered truncation limit.

Optimality and condensing of information flow through linear refinement

Detecting information flows inside a program is useful to check non-interference or independence of program variables, an important aspect of software security. In this paper we present a new abstract domain C expressing constancy of program variables. We then apply Giacobazzi and Scozzari’s linear refinement to build a domain C → C which contains all input/output dependences between the constancy of program variables. We show that C → C is optimal, in the sense that it cannot be further linearly refined, and condensing, in the sense that a compositional, input-independent static analysis over C → C has the same precision as a non-compositional, input-driven analysis. Moreover, we show that C → C has a natural representation in terms of Boolean formulas, which is important since it allows one to use the efficient binary decision diagrams in its implementation. We then prove that C → C coincides with Genaim, Giacobazzi and Mastroeni’s IF domain for information flows and with Amtoft and Banerjee’s Independ domain for independence. This lets us extend to IF and Independ the properties that we proved for C → C : optimality, condensing and representation in terms of Boolean formulas. As a secondary result, it lets us conclude that IF and Independ are actually the same abstract domain, although completely different static analyses have been based on them.

Reliability Evaluation of Distributed Computer Systems Subject to Imperfect Coverage and Dependent Common-Cause Failures

Imperfect coverage (IPC) occurs when a malicious component failure causes extensive damage due to inadequate fault detection, fault location or fault recovery. Common-cause failures (CCF) are multiple dependent component failures within a system due to a shared root cause. Both imperfect coverage and common-cause failures can exist in distributed computer systems and can contribute significantly to the overall system unreliability. Moreover they can complicate the reliability analysis. In this study, we propose an efficient approach to the reliability analysis of distributed computer systems (DCS) with both IPC and CCF. The proposed methodology is to decouple the effects of IPC and CCF from the combinatorics of the solution. The resulting approach is applicable to the computationally efficient binary decision diagrams (BDD) based method for the reliability analysis of DCS. We provide a concrete analysis of an example DCS to illustrate the application and advantages of our approach. Due to the consideration of IPC and CCF, our approach can evaluate a wider class of DCS as compared with existing approaches. Due to the nature of the BDD and the separation of IPC and CCF from the solution combinatorics, our approach has high computational efficiency and is easy to implement, which means that it can be easily applied to the accurate reliability analysis of large-scale DCS subject to IPC and CCF. The DCS without IPC or CCF appear to be special cases of our approach.

Cloning-based context-sensitive pointer alias analysis using binary decision diagrams

This paper presents the first scalable context-sensitive, inclusion-based pointer alias analysis for Java programs. Our approach to context sensitivity is to create a clone of a method for every context of interest, and run a context-insensitive algorithm over the expanded call graph to get context-sensitive results. For precision, we generate a clone for every acyclic path through a program's call graph, treating methods in a strongly connected component as a single node. Normally, this formulation is hopelessly intractable as a call graph often has 10 14 acyclic paths or more. We show that these exponential relations can be computed efficiently using binary decision diagrams (BDDs). Key to the scalability of the technique is a context numbering scheme that exposes the commonalities across contexts. We applied our algorithm to the most popular applications available on Sourceforge, and found that the largest programs, with hundreds of thousands of Java bytecodes, can be analyzed in under 20 minutes.This paper shows that pointer analysis, and many other queries and algorithms, can be described succinctly and declaratively using Datalog, a logic programming language. We have developed a system called bddbddb that automatically translates Datalog programs into highly efficient BDD implementations. We used this approach to develop a variety of context-sensitive algorithms including side effect analysis, type analysis, and escape analysis.

A fast BDD algorithm for large coherent fault trees analysis

Abstract Although a binary decision diagram (BDD) algorithm has been tried to solve large fault trees until quite recently, they are not efficiently solved in a short time since the size of a BDD structure exponentially increases according to the number of variables. Furthermore, the truncation of If–Then–Else (ITE) connectives by the probability or size limit and the subsuming to delete subsets could not be directly applied to the intermediate BDD structure under construction. This is the motivation for this work. This paper presents an efficient BDD algorithm for large coherent systems (coherent BDD algorithm) by which the truncation and subsuming could be performed in the progress of the construction of the BDD structure. A set of new formulae developed in this study for AND or OR operation between two ITE connectives of a coherent system makes it possible to delete subsets and truncate ITE connectives with a probability or size limit in the intermediate BDD structure under construction. By means of the truncation and subsuming in every step of the calculation, large fault trees for coherent systems (coherent fault trees) are efficiently solved in a short time using less memory. Furthermore, the coherent BDD algorithm from the aspect of the size of a BDD structure is much less sensitive to variable ordering than the conventional BDD algorithm.

MODELING AND CONTROLLER SYNTHESIS FOR RESOURCE BOOKING PROBLEMS USING BDDS

Mixed Process algebra and Petri Nets (MPPN) combine Petri net constructs and Process algebra. The modeling language implies a compact representation of complex systems. For general resource booking problems MPPN is used for routing specifications and modeling of resources. These models are formally converted into ordinary Petri nets. The Petri net representations are easily converted into efficient Binary Decision Diagram (BDD). The BDDs are then used used for controller synthesis. It is shown that in specific cases very few boolean variables are required in the BDD representation based on MPPN. This is crucial in order to calculate a controller efficiently.

Programming Combinations of Deduction and BDD-based Symbolic Calculation

AbstractA generalisation of Milner's ‘LCF approach’ is described. This allows algorithms based on binary decision diagrams (BDDs) to be programmed as derived proof rules in a calculus of representation judgements. The derivation of representation judgements becomes an LCF-style proof by defining an abstract type for judgements analogous to the LCF type of theorems. The primitive inference rules for representation judgements correspond to the operations provided by an efficient BDD package coded in C (BuDDy). Proof can combine traditional inference with steps inferring representation judgements. The resulting system provides a platform to support a tight and principled integration of theorem proving and model checking. The methods are illustrated by using them to solve all instances of a generalised Missionaries and Cannibals problem.

High‐performance Multiplexer‐based Logic Synthesis Using Pass‐transistor Logic

An automatic logic/circuit synthesizer is developed which takes several Boolean functions as input and generates netlist output with basic composing cells from the pass‐transistor cell library containing only two types of cells: 2‐to‐1 multiplexers and inverters. The synthesis procedure first constructs efficient binary decision diagrams (BDDs) for these Boolean functions considering both multi‐function sharing and minimum width. Each node in the BDD trees is realized by using a 2‐to‐1 multiplexer (MUX) of proper driving capability designed pass‐transistor logic. The inverters are then inserted all along the MUX paths in order to improve the speed performance and to alleviate the voltage‐drop problem. Several methods are proposed to reduce the critical path delay in the multiplexer‐chains for generation of faster circuits. Compared to the recently proposed pass‐transistor‐based top‐down design, our synthesizer has better speed and area performance due to the reduced number of cascaded inverters.