Effective Work Function Modulation Research Articles

Highly Efficient Nonfullerene Organic Solar Cells with Nickel Oxide Hole‐Transporting Layer: Using Dipole‐Induced Energy‐Level Modification

To date, poly(3,4‐ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) is the most commonly used hole‐transporting material (HTM) for nonfullerene acceptor (NFA) organic solar cell (OSCs) due to its high hole conductivity and reproducibility. However, considering the significant breakthroughs made by novel donor and NFA combinations such as PM6 and Y6, the development of HTMs which can outperform PEDOT:PSS is very limited. Here, for the first time, high‐performance NFA OSCs based on simple and solution‐processed nickel oxide HTMs with high power conversion efficiency (PCE) and stability are reported. Two different kinds of hydroquinone sulfonic acid (HSA) salts, which have a permanent dipole moment, are added to NiO solution. Due to the interfacial dipole moment generated by these salts and effective work function modulation of NiO, efficient hole transportation at the interface between hole‐transporting layer and bulk heterojunction (BHJ) layer by minimizing the energetic barrier is promoted. As a result, using PM6 and the Y6‐BO‐4F‐based BHJ layer, the PCE of 14.19% with very high open‐circuit voltage of 0.86 V is achieved, which is comparable with that of PEDOT:PSS‐based OSCs. For 1200 h under ambient atmosphere, OSCs based on NiO containing HSA salts demonstrate enhanced ambient stability compared to that of PEDOT:PSS.

Dipole-induced modulation of effective work function of metal gate in junctionless FETs

In this work, a metal gate with a high effective work function (Weff) that is suitable for junctionless field-effect transistors (JLFETs) has been fabricated. Weff is modulated by inserting an Al interfacial layer with different thicknesses between the HfO2 dielectric layer and the Pt gate metal. Transmission electron microscopy together with capacitance–voltage (C–V) measurement is used to investigate the underlying mechanism of this phenomenon. It is suggested that the oxygen scavenging from HfO2 by the Al layer leads to the formation of interface dipoles, which effectively modulate Weff. By varying the Al layer thickness, it is found that Weff first increases and then decreases as the Al thickness increases above ∼2.5 nm, and the largest increase in Weff is about 0.56 eV. Based on these results, our work provides a useful method using interface dipoles to adjust Weff to the desired value for JLFETs, which is otherwise difficult to achieve using a single metal.

Effects of Annealing Temperature and Nitrogen Content on Effective Work Function of Tungsten Nitride

By varying annealing temperature (300°C–400°C) and nitrogen content (x = 0.33, 0.56) in the WNx films, the effective work function of WNx can modulate from 4.29 to 4.91 eV. WNx is deposited on SiO2/Si stacks by reactive sputtering. The effective work function increases with increasing annealing temperature and decreases with increasing nitrogen content. The effective work function modulation is due to the dipole formation at the WNx/SiO2 interface. Oxygen diffuses from SiO2 into WNx during annealing and forms the WNxOy near the interface. The dipole with the direction from WNxOy to WNx is formed because the group electronegativity of WNxOy near the WNx/SiO2 interface is larger than that of the WNx. The WNx with high nitrogen content can alleviate the oxidation and reduce dipole formation.

Plasma-assisted As implants for effective work function modulation of TiN/HfO2 gate stacks on germanium

The plasma assisted As doping (PLAD) technique is used to demonstrate multiple flatband voltages (multi-Vfb) on TiN/HfO2 Ge gate stacks for n-FinFET applications. Through detailed studies with varying doses, implant energies, and TiN cap thicknesses, we show that the PLAD As technique can be used to obtain effective work function (EWF) modulation from the near midgap to the conduction band edge (up to 280 meV) of Ge, a key technological requirement for multi-threshold voltage (VT) Ge n-FinFETs. Furthermore, there is no deterioration of key gate stack parameters such as gate leakage, effective oxide thickness, and gate/channel interface trap densities. From secondary ion mass spectroscopy data, we attribute the tuning of EWF to As accumulation and interfacial dipole formation at the TiN/HfO2 interface. The experimental observations are reinforced by ab initio simulations of near-interface As substitutions at the TiN/HfO2 interface. As substitution at N sites near the interface reduces the EWF, making it more suitable for n-MOS applications.

Effects of graphene intercalation on dielectric reliability of HfO2 and modulation of effective work function for Ni/Gr/c-HfO2 interfaces: first-principles study

We have investigated the effects of graphene intercalation on dielectric reliability of HfO2 for Ni/Gr/HfO2 interfaces, and the effects of graphene intercalation and interfacial atom vacancy on the effective work function (EWF) of Ni/Gr/HfO2 interfaces using first-principle calculation based on density functional theory. The calculated results indicate that graphene intercalation can improve dielectric reliability of HfO2 dielectric even for the interfaces having interfacial oxygen vacancy or a small amount carbon vacancy. Moreover, the calculated results indicate that, inserting graphene into Ni/HfO2 interface induces the EWF’s to decline, and controlling interfacial oxygen or carbon vacancy can effectively tune the EWF of Ni/Gr/HfO2 interface. Our work strongly suggests that the use of graphene synthesized into Ni/HfO2 interface is a very effective way to improve the interface quality, and controlling interfacial oxygen or carbon vacancy is also an attractive and promising way for modulating the EWF of Ni/Gr/HfO2 interfaces.

Data Retention Characterization of Gate-Injected Gold-Nanoparticle Non-Volatile Memory with Low-Damage CF₄-Plasma-Treated Blocking Oxide Layer.

Gold-nanoparticle (Au-NP) non-volatile memories (NVMs) with low-damage CF4 plasma treatment on the blocking oxide (BO) layer have been investigated to present the gate injection of the holes. These holes, injected from the Al gate with the positive gate bias, were explained by the bandgap engineering of the gradually-fluorinated BO layer and the effective work function modulation of the Al gate. The Si–F complex in the BO layer was analyzed by X-ray photoelectron spectroscopy (XPS), while the depth of fluorine incorporation was verified using a secondary ion mass spectrometer (SIMS). In addition, the valence band modification of the fluorinated BO layer was examined by ultraviolet photoelectron spectroscopy (UPS) to support the bandgap engineering. The reactive power of the CF4 plasma treatment on the BO layer was modified to increase the electric field of the BO layer and raise the effective work function of the Al gate, leading to the hole-injection from the gate. The injected holes are trapped at the interface between the gold-nanoparticles (Au-NPs) and the tunneling oxide (TO) layer, resulting in superior data retention properties such as an extremely low charge loss of 5.7% at 104 s and a nearly negligible increase in charge loss at 85 °C of the CF4-plasma-treated Au-NP NVMs, which can be applied in highly reliable consumer electronics.

Effective work function modulation of the bilayer metal gate stacks by the Hf-doped thin TiN interlayer prepared by the in-situ atomic layer doping technique

The in-situ atomic layer doping technique was used to precisely control the Hf incorporation into the thin TiN interlayer for tailoring the effective work function (EWF) of the Pt/TixHfyN bilayer metal gate stack. An analysis of the capacitance-voltage characteristics revealed the variation of the flatband voltage with the equivalent oxide thickness of the gate oxide, giving the EWF of the Pt/TixHfyN bilayer metal gate stack. Instead of the EWF (~5.7eV) of the single-layer Pt gate electrode, the EWF of the Pt/TixHfyN bilayer metal gate stacks is tunable with the range from 4.54eV to 5.17eV by the insertion of the thin TiN interlayer and the Hf incorporation. The result indicates that the in-situ atomic layer doping technique is an effective approach to modulating the electrical properties of metal gate in future MOS devices.

(Invited) Gate-All-Around Nanowire FETs vs. Triple-Gate FinFETs: On Gate Integrity and Device Characteristics

Triple-gate finFET manufacturing implementation has been successfully enabling continuance of CMOS scaling and Moore’s law [1], but it faces increased scaling challenges for sub-10nm nodes. Gate-all-around (GAA) nanowire (NW) FETs with the thin-body of the device, in a lateral or vertical configuration, fully wrapped around by the gate can be considered the ultimate scaling limit of finFETs [2-4]. They have the potential to offer superior short-channel electrostatics, and are thus regarded as one of the most promising candidates to further support the CMOS roadmap. In this work, we report a comprehensive evaluation of these two different device architectures from a device and circuit perspective, focusing on the key topics of gate stack integrity, leakage, reliability and noise performance and on the impact of the process options used. For simplicity, all devices were built on SOI substrates, with GAA lateral NWFETs obtained via a fins release process at replacement metal gate (RMG) module, which is high density compatible, and wherein diluted-HF was used to remove the BOX under the fins in areas previously covered by the dummy-gates [while the rest of the wafer is covered by the inter-layer dielectric level-zero oxide (ILD0)]. The gate stack used consists of: interfacial layer (IL)-SiO2/HfO2 followed by the effective work function (EWF)-metal (TiN or a TiAl-based stack) and W fill-metal. Examples of TEM images taken across a wire (GAA-NWFET) or a fin (triple-gate finFET) after full processing are shown in Fig.1 [4]. Intrinsic transistor performance (ITP) characteristics show that GAA-NWFETs clearly outperform finFETs when normalizing ION-IOFF per footprint. Furthermore, an evaluation of several doping strategies for both type of devices, using ion implantation (I/I), allowed a comparison of inversion-mode (IM) FETs built with conventional junctions or an extensionless (Extless) scheme [4,5] vs. junctionless (JL) transistors [4,6]. To note that the latter are particularly advantageous in their process simplicity (no junction formation requirements) and compatibility with lower thermal budget flows. Reliability wise, optimized JL and Extless can be very attractive options thanks to a lower oxide field (Eox) at operating conditions. This is indeed confirmed by the GAA-NWFETs in Fig.2. Control of the lateral BOX recess during the fins release process in the GAA flow, and hence of the lateral bottom-gate overlap, is important not only for parasitic reasons but also for reliability purposes. Indeed, TCAD predicts a higher Eox at the bottom-gate edges in case of excessive lateral BOX recess which can lead to degraded BTI behavior for GAA-NWFET vs. finFET. The impact is however considerably less for Extless and JL, increasing the robustness of these devices against process variations in the lateral BOX recess. JL devices were also seen to have improved on and off state hot carrier (HC) reliability behavior as compared to other IM GAA-NWFETs [7]. Interestingly, improved subthreshold slope (SS) values after HC stress were also measured in some JL GAA-NWFETs as a result of the improved electrostatic control and the generation and location of acceptor type of interface traps in the wires of slightly concave sidewalls shape. Low-frequency (LF) noise analysis results suggest to a first order no significant impact of the device architecture on the gate stack integrity in regards to traps/defects. In addition, in agreement with BTI and HC results, JL GAA-NWFETs also show reduced noise. These characteristics, together with the devices smaller IOFF values yielding ring oscillators with substantially lower power dissipation, indicate JL can be an attractive option for low power circuits. Improvements in noise, reliability and mobility performance were also obtained in GAA-NWFETs by introduction of a TiAl-based EWF-metal [4,8], in line with the results previously reported in [9] on finFETs using Al diffusion mechanisms for EWF modulation.

Room-Temperature Solution-Processed n-Doped Zirconium Oxide Cathode Buffer Layer for Efficient and Stable Organic and Hybrid Perovskite Solar Cells

In this study, we present a simple and effective method to improve the performance and stability of organic and hybrid perovskite solar cells by the incorporation of solution-processed cetyltrimethylammonium bromide (CTAB)-doped zirconium oxide (ZrOx) as cathode buffer layer (CBL). This novel n-doped ZrOx CBL possesses several remarkable features, including ease of fabrication without the need for thermal annealing or any other post-treatment, reasonable electrical conductivity (2.9 × 10–5 S cm–1), good ambient stability, effective work function modulation of Ag electrode, relative weak thickness-dependent performance property, and wide applicability in a variety of active layers. Compared with ZrOx CBL without CTAB dopant, CTAB-doped ZrOx can significantly improve the power conversion efficiency (PCE) from 0.57% to 2.48% in organic solar cells based on diketopyrrolopyrrole-thiophene-bezothiadazole low-bandgap polymer (PDPP-TBT):[6,6]-phenyl-C71-butyric acid methyl ester (PC71BM) blend. With this n-doped ...

Effective work function modulation by sacrificial gate aluminum diffusion on HfON-based 14 nm NMOS devices

Sacrificial gate first process efficiency to further increase effective work function (WFeff) towards P+ by metallic aluminum diffusion is demonstrated in this work by combining capacitance vs voltage (CV) measurements on beveled oxides with different spectroscopic techniques. Aluminum diffusion role on WFeff is evidenced and is found to be simultaneously dependent of as-deposited aluminum dose and annealing temperature.

Effective work function modulation of SWCNT–AZO NP hybrid electrodes in fully solution-processed flexible metal-oxide thin film transistors

Schematic diagram of an SWCNT–AZO NP hybrid electrode TFT and the optical image of the TFT with the SWCNT/AZO NP hybrid electrodes on a PI substrate.

Chemical tuning of band alignments for Cu/HfO2 interfaces

First-principles density functional theory is used to explore the possibility of tuning effective work function of high dielectric/metal gate stacks. Using HfO/Cu as an example, we demonstrate that the effective work function of the stack can be tuned in a range of 3.2 eV by incorporating a metallic monolayer at the interface. The calculations reveal that the interfacial charge transfer from the metallic monolayer to the oxide plays a key role in tuning the effective work function. The interfacial charge transfer not only depends on the ionic bonding between the O atoms and the metal monolayer, but it can also be affected by the metallic bonding between the gate Cu atoms and the metal monolayer. The weaker the metallic bonding, the stronger the interfacial dipole moment, and the greater the effective work function modulation. A linear correlation between the interfacial charge transfer and the valence band offset is observed which can be rationalized by an analogy to a parallel plate capacitor. We also find a correlation between interfacial atomic rearrangements and the interfacial charge transfer. The general chemical tuning trends established in this study could potentially provide a valuable guide for designing novel gate materials in conjunction with high-k dielectrics.

Role of point defects and HfO2/TiN interface stoichiometry on effective work function modulation in ultra-scaled complementary metal–oxide–semiconductor devices

We investigate the physical properties of a portion of the gate stack of an ultra-scaled complementary metal-oxide-semiconductor (CMOS) device. The effects of point defects, such as oxygen vacancy, oxygen, and aluminum interstitials at the HfO2/TiN interface, on the effective work function of TiN are explored using density functional theory. We compute the diffusion barriers of such point defects in the bulk TiN and across the HfO2/TiN interface. Diffusion of these point defects across the HfO2/TiN interface occurs during the device integration process. This results in variation of the effective work function and hence in the threshold voltage variation in the devices. Further, we simulate the effects of varying the HfO2/TiN interface stoichiometry on the effective work function modulation in these extremely-scaled CMOS devices. Our results show that the interface rich in nitrogen gives higher effective work function, whereas the interface rich in titanium gives lower effective work function, compared to a stoichiometric HfO2/TiN interface. This theoretical prediction is confirmed by the experiment, demonstrating over 700 meV modulation in the effective work function.

Interface dipole engineering in metal gate/high-k stacks

Although metal gate/high-k stacks are commonly used in metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the 45 nm technology node and beyond, there are still many challenges to be solved. Among the various technologies to tackle these problems, interface dipole engineering (IDE) is an effective method to improve the performance, particularly, modulating the effective work function (EWF) of metal gates. Because of the different electronegativity of the various atoms in the interfacial layer, a dipole layer with an electric filed can be formed altering the band alignment in the MOS stack. This paper reviews the interface dipole formation induced by different elements, recent progresses in metal gate/high-k MOS stacks with IDE on EWF modulation, and mechanism of IDE.

Effective work function control of metal inserted poly-Si electrodes on HfSiO dielectrics by in-situ oxygen treatment of metal surface

We fabricated novel poly-Si/TiN/HfSiO/SiO2 gate stacks by using an in-situ oxygen treatment process of a TiN electrode surface in order to suppress Si diffusion from poly-Si upper layer during post deposition annealing (PDA). The Si depth profile after PDA showed that no Si diffused into oxidized stacks due to the formation of TiON layers as a Si diffusion barrier. Furthermore, a high effective work function (EWF) of 4.94 eV was obtained from the oxidized stack even after PDA at 1000 °C. This high EWF is due not only to Si diffusion barrier formation but also to oxygen vacancy compensation by diffused-oxygen from the TiON layer. However, we observed significant growth of interfacial SiO2 after high temperature annealing. These results indicate a trade-off relationship between EWF control and equivalent oxide thickness (EOT) scaling, and imply that an additional method for EWF modulation is required for scaled high-k devices.

Impact of Si Diffusion Barrier Layer Formed on TiN Surface by In Situ Oxygen Treatment Process for Advanced Gate-First Metal/High-k Stacks

We investigated the formation of Si barrier layer by an in-situ oxygen treatment process of TiN electrode surface before poly-Si deposition. The Si depth profile after post deposition annealing (PDA) showed that no Si diffused into oxidized stacks due to the formation of TiON layers as a Si-diffusion barrier. Moreover, a high effective work function (EWF) of 4.94 eV was obtained from the oxidized stack even after PDA at 1000oC. However, we observed significant growth of interfacial SiO2 after high temperature annealing. These results indicate a trade-off relationship between EWF control and equivalent oxide thickness (EOT) scaling, and imply that an additional method for EWF modulation is required for scaled high-k devices.

The Role of Rare Earth Metals on Effective Work Function Modulation of Nickel Fully-Silicided Gate/High-k Dielectric Stacks for n-Channel Metal Oxide Semiconductor Device Applications

It was found that the structural properties with gadolinium (Gd) and europium (Eu) incorporation into nickel (Ni) fully silicided (FUSI) gate electrodes are markedly different and resulted in different degrees of effective work function modulation. It was found that Ni–Gd alloys tend to form stable compounds during silicidation and produced a Si-rich layer with amorphous/nanocystalline structure near the FUSI gate electrode/high-k dielectric interface. This compositional and structural change is the main mechanism responsible for effective work function modulation with Gd incorporation. However, in the case of Europium, Eu atoms tend to segregate outside the Ni-FUSI layer during silicidation and resulted in a uniform NixSiy layer with Eu pile-up layer at the FUSI gate electrode/high-k dielectric interface. This pile-up is believed to be the main cause of effective work function modulation with Eu incorporation. It was also found that the incorporation of Gd and Eu metals into Ni-FUSI gate can remotely scavenge the interfacial oxide layer resulting in lower equivalent oxide thickness (EOT) of the device.

The Role of Rare Earth Metals on Effective Work Function Modulation of Nickel Fully-Silicided Gate/High-kDielectric Stacks for n-Channel Metal Oxide Semiconductor Device Applications

The Role of Rare Earth Metals on Effective Work Function Modulation of Nickel Fully-Silicided Gate/High-<i>k</i>Dielectric Stacks for n-Channel Metal Oxide Semiconductor Device Applications

Impact of Thermally Induced Structural Changes on the Electrical Properties of TiN/HfLaSiO Gate Stacks

Thermally induced structural changes in TiN/Hf(La)SiO gate stacks were investigated by back-side X-ray photoelectron spectroscopy (XPS) and near edge X-ray absorption fine structure (NEXAFS). A distinct correlation between bottom oxide growth and an increase in equivalent oxide thickness (EOT) was confirmed under high-temperature annealing at over 850 °C regardless of La content. Back-side XPS also revealed that oxygen and nitrogen diffusion occurs, forming partially oxidized TiON layers at a metal/high-k interface under moderate annealing temperatures of approximately 600 °C, and that annealing at over 750 °C leads to the reduction of the oxide phase and produces a thinner inter-layer with a clear Ti–N bond feature. Moreover, with an increase in annealing temperature, a change in the local atomic configuration in the HfLaSiO dielectric layer was identified from oxygen K-edge spectra. This structural change induced by thermal reaction can be considered as a possible cause of the Vth instability of La-incorporated high-k gate stacks. On the basis of these findings on structural changes, the physical origins of the effective work function modulation of the gate stacks are discussed in detail.

Impact of Thermally Induced Structural Changes on the Electrical Properties of TiN/HfLaSiO Gate Stacks

Thermally induced structural changes in TiN/Hf(La)SiO gate stacks were investigated by back-side X-ray photoelectron spectroscopy (XPS) and near edge X-ray absorption fine structure (NEXAFS). A distinct correlation between bottom oxide growth and an increase in equivalent oxide thickness (EOT) was confirmed under high-temperature annealing at over 850 °C regardless of La content. Back-side XPS also revealed that oxygen and nitrogen diffusion occurs, forming partially oxidized TiON layers at a metal/high-k interface under moderate annealing temperatures of approximately 600 °C, and that annealing at over 750 °C leads to the reduction of the oxide phase and produces a thinner inter-layer with a clear Ti–N bond feature. Moreover, with an increase in annealing temperature, a change in the local atomic configuration in the HfLaSiO dielectric layer was identified from oxygen K-edge spectra. This structural change induced by thermal reaction can be considered as a possible cause of the Vth instability of La-incorporated high-k gate stacks. On the basis of these findings on structural changes, the physical origins of the effective work function modulation of the gate stacks are discussed in detail.