Effect Of Workfunction Variation Research Articles

Effect of Work-function Variation on Transfer Characteristics and Memory Performances for Gate-all-around JLFET based Capacitorless DRAM

In this study, we present variations in transfer characteristics and memory performances caused by work-function variation (WFV) in the metal gate of a one-transistor dynamic random-access memory cell based on a gate-all-around junctionless field-effect transistor (GAA-JLFET). To investigate the influence of WFV, we simulated 200 samples of GAA-JLFETs. The samples had different transfer characteristics depending on the metal grain granularity. In addition, we calculated and analyzed the mean and standard deviations for the transfer characteristics. Further, the memory performances were analyzed using two extreme cases with the highest and lowest threshold voltage (V<SUB>th</SUB>) as examples. When WFV was not considered, the current ratio was 108, and retention time was more than 10 ms. Meanwhile, when WFV was considered, the current ratio was 10² and 10⁴, and the retention time was reduced to 0.051 ms and 2.2 ms, respectively. These results showed that WFV affected not only the transfer characteristics in GAA-JLFET but also the memory performances; it could adversely affect the reliability of the memory device.

Novel Asymmetric Recessed-Gate/Source Architecture Advancement of Dual-Metal-Gate SiGe/Si Dopingless Nanowire-TFET for Low-Voltage Performance Optimization

A dopingless vertical Nanowire (NW) Tunnel Field Effect Transistor TFET structure has been designed using techniques such as Dual-Metal Gate (DMG), Heteromaterial Channel (HmC) and Heterodielectric Oxide (HdO) to enhance the device performance. The proposed device is investigated to acknowledge the device behavior for RF/Low-Noise applications. The essence of the reported work is to capture the effect of work function variation of DMG on device characteristics for noise enhancement/degradation. The vertical structure simplifies the implementation of charge-plasma technique for induced doping within the source/drain region enveloped by Gate-All-Around (GAA) architecture. Different work function combinations of gate metal1 (GM1) and gate metal2 (GM2) are used for calculations and compared to acquire optimized results. Other than Silicon, Silicon-Germanium compound (SixGe1-x) with composition factor (x) equals to 0.55 is used for HmC, whereas Zirconium Silicate is preferred for HdO. The characteristics analysis includes the negative drain bias variation that captures an interesting tunnel diode characteristics with peak current to valley current ratio of approx. 108. The proposed structure is modified to reduce the Gate-to-Source capacitive coupling and drain current enhancement. The proposed device is analyzed for Ambipolar-state, OFF-state and ON-state, which is required to understand the proper working of TFET devices.

Analysis of Work-Function Variation Effects in a Tunnel Field-Effect Transistor Depending on the Device Structure

Metal gate technology is one of the most important methods used to increase the low on-current of tunnel field-effect transistors (TFETs). However, metal gates have different work-functions for each grain during the deposition process, resulting in work-function variation (WFV) effects, which means that the electrical characteristics vary from device to device. The WFV of a planar TFET, double-gate (DG) TFET, and electron-hole bilayer TFET (EHBTFET) were examined by technology computer-aided design (TCAD) simulations to analyze the influences of device structure and to find strategies for suppressing the WFV effects in TFET. Comparing the WFV effects through the turn-on voltage (Vturn-on) distribution, the planar TFET showed the largest standard deviation (σVturn-on) of 20.1 mV, and it was reduced by −26.4% for the DG TFET and −80.1% for the EHBTFET. Based on the analyses regarding metal grain distribution and energy band diagrams, the WFV of TFETs was determined by the number of metal grains involved in the tunneling current. Therefore, the EHBTFET, which can determine the tunneling current by all of the metal grains where the main gate and the sub gate overlap, is considered to be a promising structure that can reduce the WFV effect of TFETs.

Compact Model Strategy of Metal-Gate Work-Function Variation for Ultrascaled FinFET and Vertical GAA FETs

In this paper, we develop an accurate compact model for work-function variation (WFV)-induced threshold voltage $({V}_{\textsf {th}})$ variations of various 5-nm candidates, in this case, Si SOI FinFETs, vertical gate-all-around nanowire FETs, and nanoplate FETs. Using the typical probability distribution function model to predict the effect of WFV, due to the ideal condition, an error occurs in ultrascaled devices. Therefore, to analyze the influence of WFV accurately, the error rate ( $\alpha $ ) is corrected by considering irregular grain patterns (Voronoi method). In addition, the total number of grains on the metal surface can be calculated while considering the effective grain size and gate area due to the structural characteristics of the device. Finally, the model is benchmarked against 3-D TCAD simulations to demonstrate excellent accuracy [1.53% error in $\sigma $ ( ${V} _{\textsf {th}}$ )]. Moreover, the accuracy is improved by more than 15 times compared with the existing analytical models. As a result, the proposed model based on binomial distribution is able to analyze the effect of WFV at a significantly lower computational cost than 3-D TCAD simulations.

Comparison of work function variation between FinFET and 3D stacked nanowire FET devices for 6-T SRAM reliability

In this work, work-function variation (WFV) on 5 nm node gate-all-around (GAA) silicon 3D stacked nanowire FET (NWFET) and FinFET devices are studied for 6-T SRAM cells through 3D technology computer-aided design (TCAD) simulation. The NWFET devices have strong immunity for the unprecedented short channel effects (SCEs) compared with the FinFET devices owing to increased gate controllability. However, due to the narrow gate area, the single NWFET is more vulnerable to WFV effects than FinFET devices. Our results show that the WFV effects on single NWFETs are larger than the FinFETs by 45–55%. In the case of standard SRAM bit cells (high density: 111 bit cell), the variation of read stability (read static noise margin) on single NWFETs are larger than the FinFETs by 65–75%. Therefore, to improve the performance and having immunity to WFV effects, it is important to analyze the degree of variability in 3D stacked device architectures without area penalty. Moreover, we investigated the WFV effects for an accurate guideline with regard to grain size (GS) and channel area of 3D stacked NWFET in 6-T SRAM bit cells.