Temperature Instability Effect Research Articles

Lookup table‐based negative‐bias temperature instability effect and leakage power co‐optimization using genetic algorithm approach

SummaryAs a result of continuous scaling of transistors, negative bias temperature instability (NBTI) has become a serious reliability concern which causes the device to degrade over its lifetime. Similarly, leakage power also remains a key issue in deep submicron technologies. Both NBTI‐related delay degradation and standby time leakage power depend strongly on the circuit's input patterns. The input vector control (IVC) technique can be used for mitigating both NBTI‐related delay degradation and leakage power. However, the input vectors with the least NBTI‐induced degradation may not be the same ones with the least leakage power in any circuit; therefore, co‐optimization is needed to minimize leakage and NBTI‐induced degradation. In this paper, a genetic algorithm (GA)‐based approach is presented to co‐optimize both NBTI‐related performance degradation and also leakage power. We are also presenting a trade‐off analysis by giving different weightage to the NBTI effect and leakage power. Simulation results applied on ISCAS'85 benchmark circuits illustrate that on average our proposed technique saves up to 21.85% and 17.68% circuit performance degradation and the leakage power, respectively.

Minimizing Measurement Error of Phase Noise of a Narrow-Band Laser Using a Fiber-Based Mach–Zehnder Interferometer with Polarization Maintenance

A device for measurements of phase noise with the use of the Mach–Zehnder interferometer is proposed, in which all fi ber components are made based on fiber with polarization state maintenance. This permits not using a basic radiation source in the device, and thereby reducing significantly the installation cost. Two interference signals from orthogonally polarized waves are formed in the device and are then divided by a polarizing demultiplexor that eliminates the effect of external noise on the measurement result. An algorithm for calculating phase noise is described and an estimate of the effect of temperature instability is presented. A comparison of the characteristics of phase noise between calculated and specified in modeling was performed in order to assess the operational capability of the installation and algorithm for signal processing.

A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging

Temporal unreliability due to aging, such as Negative-Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) effects etc., in the CMOS circuits may not appear just after the chip production, instead it becomes apparent when it is used under certain workload and environmental conditions over time. Identifying aged paths that may become critical to circuit performance, is a real challenge for many researchers and reliability engineers. In this work, firstly we identify a set of parameters that impact the circuit performance under aging and use them in the proposed algorithm which is substantially faster than commercially available SPICE simulator with an approx 94% accuracy in estimating path delays. Secondly, we explore the possibility of using the proposed methodology, instead of using time expensive SPICE and pessimistic static timing analysis (STA), to identify a set of speed-limiting paths under aging. Experimental results demonstrate the effectiveness of the proposed algorithm and the associated methodology in comparison to SPICE simulated results.

The effect of temperature instability on the threshold sensitivity of photodetectors based on AIII–BV photodiodes

The dependence of the sensitivity of photodetectors based on AIII–BV photodiodes on accidental variations of the temperature of its elements is analyzed. It is shown that the temperature drift of the bias level in input circuits of op-amps strongly contributes to the resulting photodetector noise up to frequencies on the order of 1 MHz. To reach the limiting sensitivities of the sensors, it is necessary to stabilize the temperature of not only the photodiode chip, but also the integrated circuit of the first amplifier stage. For most of applications, the required stabilization accuracy does not exceed ±0.1°C. As a result of the analysis, prototype high-sensitivity medium-wavelength (2–5 μm) sensors were developed that operate without forced cooling and have a detection threshold of tens of nanowatts at a detection bandwidth of 0–1 MHz.

Gate length dependence of hot carrier injection degradation in short channel silicon on insulator planar MOSFET

With the continued device scaling and the introduction of new device structures, MOSFET reliability phenomena arising from the hot carrier injection (HCI) stress have received extensive attention from both the academia and the industry community. In this work, the degradations of ultra-scaled silicon on insulator (SOI) MOSFETs under the HCI stress are investigated on devices of different gate lengths (L=30-150 nm). Our experimental data demonstrate that the time evolutions of the threshold voltage change (Vth) under the HCI stress for different gate length devices are the same, and the magnitude of Vth reduces for the shorter devices. The degradation of the device under the HCI stress should be due to both the channel hot carrier (CHC) effect and the bias temperature instability (BTI) effect. The distribution and magnitude of the electric field along the MOSFET's channel are analyzed. It is confirmed that besides the well-known CHC effect in the depletion region close to the drain side, a strong BTI effect co-exists in the channel close to the source side. This degradation mechanism is different from the conventional HCI stress. With the gate length decreasing, the contribution of the aforementioned BTI effect becomes larger, and it dominates in the degradation. One feature of the BTI effects is that the corresponding degradation is small when the gate length is short. This is consistent with our experimental result that the change of Vth is small for the device of short gate length under the accelerated HCI stress. The time evolution of Vth can be described by the equation Vth=A•tn, where A is a constant, t is the stress time, and n is the power law exponent obtained by the curve fitting. In this study, the power law exponent n of pMOSFET is larger than that of nMOSFET. This experimental fact can lead to the point that the BTI effect exists during the HCI stress because the BTI effect in ultra-scaled pMOSFETs is more significant than that in nMOSFETs. The stress-recover experiments of the HCI stress on MOSFTTs show larger recovery in device of shorter gate length. It is found that the ratio of the recovery to the total degradation in the 30 nm gate-length device is almost twice as large as that in the 150 nm device. The degradation from the CHC effect has no recovery, and the larger recovery in the shorter-channel device implies the larger component of the BTI degradation. Another intriguing fact is that our experimental result on SOI MOSFET is inconsistent with the recently reported result on FinFET. We argue that the reported stronger HCI degradation in FinFET may not be ascribed only to the stronger electric field in the shorter channel, but also to the fact that the FinFET' channel is three-dimensionally surrounded by the gate dielectric. This kind of three-dimensional structure significantly increases the chance for electrons or holes to be injected into the dielectric layer. Therefore the HCI reliability of planar SOI MOSFETs may be better than that of FinFETs at the same level of gate length. In conclusion, the BTI effect is an important source of the degradation during the HCI stress in ultra-short-channel device, and it is no more negligible in analyzing the underlying physical mechanism.

Dependence of the DC stress negative bias temperature instability effect on basic device parameters in pMOSFET

To analyze the dependence of the DC stress negative bias temperature instability (NBTI) effect on basic device paraments, such as the channel length, the gate oxide thickness, the doping concentration, we solve the hydrogen molecule drift-diffusion model of NBTI together with the semiconductor device equations. The results are compared with the existing experimental data and the basic laws and physics of devices, which is necessary for reliability studies of NBTI. The analysis results show that NBTI effect is not affected by the channel length change, but maily by the thickness of the gate oxide layer. Gate oxide thickness thinning and gate oxide layer electric field enhancement effect are consistent, which determines the device degradation in the manner of exponential law. With channel doping concentration increasing, NBTI effect will be reduced, which is because the device channel surface hole concentration is reduced, however with the doping concentration increases to such a value that the device source drain leakage current is very low (low leakage device), the MBTI effect is obviously enhanced. These are helpful for understanding NBTI and designing the high performance device.

High-Field Degradation of Poly-Si Gate p-MOS and n-MOS Devices With Nitrided Oxides

In this paper, the authors investigate polysilicon gate MOS capacitors and MOSFET devices with nitrided oxides. These devices are known to also show a strong negative bias temperature instability (NBTI) effect. The authors analyze the dependence of oxide-trap generation in p-channel and n-channel devices on negative and positive Fowler-Nordheim (FN) charge injection stress by application of various C-V and charge pumping (CP) measurement methods yielding information on traps at different oxide locations. In the case of p-channel devices, a strong evidence for a preexistent very high oxide-trap concentration near the gate already before stress application is obtained. This feature is accompanied by a fast degradation of the p-channel devices under a negative bias stress similar to NBTI degradation. The CP measurements, which, in contrast to classical methods, are able to distinguish between actually fast interface traps and the slower near-interface oxide traps (NIOTs), showed that in all devices, a stress polarity dependence of trap generation occurs only for NIOTs and not for interface traps

Amplification and temperature instability effects in a thermocouple with strongly temperature-dependent thermoelectric parameters

It is shown that the temperature dependence of the branches of a thermocouple can produce unstable operating regimes and steep performance curves.