EEPROM Tunnel Oxide Research Articles

Design of 32 kbit one-time programmable memory for microcontroller units

A 32 kbit OTP (one-time programmable) memory for MCUs (micro-controller units) used in remote controllers was designed. This OTP memory is used for program and data storage. It is required to apply 5.5 V to BL (bit-line) and 11 V to WL (word-line) for a OTP cell of 0.35 μm ETOX (EEPROM tunnel oxide) type by MagnaChip. We use 5 V transistors on column data paths to reduce the area of column data paths since they require small areas. In addition, we secure device reliability by using HV (high-voltage) transistors in the WL driver. Furthermore, we change from a static logic to a dynamic logic used for the WL driver in the core circuit. Also, we optimize the WD (write data) switch circuit. Thus, we can implement them with a small-area design. In addition, we implement the address predecoder with a small-area logic circuit. The area of the designed 32 kbit OTP with 5 V and HV devices is 674.725 μm×258.75 μm (=0.1745 mm2) and is 56.3% smaller than that using 3.3 V devices.

A new experimental method to extract EEPROM tunnel oxide trap density from threshold voltage distributions

To ensure the reliability of EEPROM devices, it is significant to monitor the evolution of the memory array threshold voltage (V T) distribution. In this work, impact of endurance and retention tests is evaluated on EEPROMs. Based on the extrinsic V T population evolution, the oxide tunnel trap concentration (Nit) is extracted using a 700 kbits EEPROM test chip. Data retention after Write/Erase (W/E) cycles is one of the most important reliability issues in EEPROM devices. The electric high-field stress induced during W/E cycles is mainly responsible for the degradation of the retention time because it creates intrinsic failures or traps in the EEPROM tunnel oxide. These traps serve as bridges for the trap to trap conduction current (I TAT) in the tunnel oxide. EEPROM data retention degradation due to this stress-induced leakage current (SILC) impacts directly the EEPROM V T distribution by creating extrinsic populations. To track accurately extrinsic cells' evolution (tail bits), representative of Nit parameter, an innovative experimental plan is proposed.

EEPROM tunnel oxide lifetime reliability prediction based on fast electrical stress tests

It is shown how floating gate memory cell behaviour during retention tests can be predicted relying on static electrical stress tests. Retention tests are usually performed at high or low temperature bake to provide warning of an impending failure of the capability of memory cells to store data. These tests are very useful to screen out defective cell populations but induce significant test time overhead. To overcome this limitation, a correlation between stress time and retention time is established to anticipate retention test results. Experimental results based on an EEPROM test chip are presented in order to show the correlation between retention tests and electrical stress tests.

A new technique to characterize endurance of EEPROM tunnel oxides

In this study, the critical parameters relevant to endurance of EEPROM memory cells are theoretically determined from cells geometrical design and programming pulses temporal shape. A new experimental technique is then proposed to realize realistic current pulsed stresses on dedicated large area cell test structures. The influence of the different relevant pulses parameters is finally experimentally studied and discussed.

Dynamic Fowler–Nordheim injection in EEPROM tunnel oxides at realistic time scales

The purpose of this work is to investigate the dynamic behaviour of Fowler–Nordeim injection through EEPROM tunnel oxides, in conditions representative of the standard device operation. An experimental procedure based on the acquisition of current transients induced by trapezoidal-shape short voltage pulses is presented. It is then used to evidence a rapid positive charging and to determine some of its properties. Implications regarding the device behaviour and modelling are finally discussed.

Model of leakage current induced by dynamic stress in thin EEPROM tunnel oxides

It has been currently observed that Fowler–Nordheim tunneling injection through thin SiO 2 oxide layers (5–10 nm) induces leakage currents called stress-induced leakage currents (SILC). These could contribute to data retention loss in EEPROM non-volatile memory devices. In this work, we have stressed 7 nm thick SiO 2 MOS capacitors with bipolar symmetrical pulses similar to write–erase cycles used for EEPROM cell programming. I( V), current–voltage data, have been analyzed to identify the induced conduction mechanisms after different stress levels. It has been shown that I( V) data present two zones. The first zone, for oxide electric fields greater than 7 MV cm −1, always remains governed by a classical Fowler–Nordheim effect. At smaller electric fields corresponding to the SILC domain, the current has been successfully modelled by a trap-assisted conduction mechanism. At largest injected charge levels, coulombic attractive traps generated in SiO 2 overlap inducing conduction enhancement that we have described by a two-traps model.

Heavy oxynitridation technology for forming highly reliable flash-type EEPROM tunnel oxide films

For the first time, it is demonstrated that in flash-type EEPROMs, the endurance properties are dramatically improved by heavy oxynitridation (RTONO) of the tunnel oxide. The layer composition evaluted by SIMS measurement indicates that large amounts of N atoms (>1020 atom/cm3) pile up at the SiO2/Si interface, and are distributed in the bulk SiO2. In addition, the RTONO film reduces the number of hydrogen atoms, which are the origin of electron traps. This oxynitridation causes a decrease of both electron and hole traps in the tunnel oxide, resulting in an improvement of the threshold voltage narrowing.

Novel N/sub 2/O-oxynitridation technology for forming highly reliable EEPROM tunnel oxide films

Ultrathin ( approximately=6 nm) oxynitrided SiO/sub 2/ (SiO/sub x/N/sub y/) films have been formed on Si