EEMBC Benchmarks Research Articles

Evaluation and Benefit of Imprecise Value Prediction for Certain Types of Instructions

Based on branch prediction, value prediction has emerged as a solution for problems caused by true data dependencies in pipelined processors. While branch predictors have binary outcomes (taken/not taken), value predictors face a challenging task as their outcomes can take any value. Because of that, coverage is reduced to enhance high accuracy and minimise costly recovery from misprediction. This paper evaluates value prediction, focusing on instruction execution with imprecisely predicted operands whose result can still be correct. Two analytical models are introduced to represent instruction execution with value prediction. One model focuses on correctly predicted operands, while the other allows for imprecisely predicted operands as long as the instruction results remain correct. A trace-driven simulator was developed for simulation purposes, implementing well-known predictors and some of the predictors presented at the latest Championship Value Prediction. The gem5 simulator was upgraded to generate program traces of SPEC and EEMBC benchmarks that were used in simulations. Based on the simulation result, proposed analytical models were compared to reveal the conditions under which a model with imprecisely predicted operands, but still correct results, achieved better execution time than a model with correctly predicted operands. Analysis revealed that the accuracy of the correct instruction result based on the predicted operand, even when the predicted operand is imprecise, is higher than the accuracy of the correctly predicted operand. The accuracy improvement ranges from 0.8% to 44%, depending on the specific predictor used.

Energy efficient IPC based dual compression for endurance enhancement of NVRAM as main memory in embedded devices

AbstractThe Non‐Volatile Random Access Memory (NVRAM) is recently identified as the most upcoming main memory technology in Embedded and Internet of Things (IoT) systems due to its appealing qualities like zero static power consumption and great memory cell density. On the other hand, most NVRAMs have low write endurance due to workload‐induced write variance, leading to more write activity at a few blocks of memory than the other blocks. Improving the endurance of NVRAM on embedded architectures is very critical due to the limited constraints of Embedded architectures. The main goal of this paper is to address the complexity of NVRAM designs, with a focus on embedded boards, and to create a prototype that enhances NVRAM endurance using a compression technique. Furthermore, this framework is not particular to a single NVRAM device. An Instruction Per Cycle based Dynamic Pattern Compression (IPC_DPC) model is developed to address NVRAM's high write latency and low endurance. The primary goal of the proposed IPC_DPC model is to minimize the energy utilization and latency of heavy workloads during the execution by pre‐determining the workload's instruction cycles. The IPC_DPC model initially divides the Low IPC and High IPC workloads and then compresses the workloads dynamically based on their IPC values compared to the threshold factor. As a result, IPC_DPC improves the compression ratio and reduces the write latencies associated with traditional compressors, significantly reducing the write activity and improving the lifetime of NVRAM. We implemented the proposed IPC_DPC model using GEM5 with a Raspberry Pi board and took IoMT, MiBench, and EEMBC benchmarks for evaluation. Compared to FPC, BDI, FNW, and DFPC models, the proposed IPC_DPC model is shown to be more efficient in terms of compression ratio (56.05%) and energy reduction (17%).

Improving ILP via Fused In-Order Superscalar and VLIW Instruction Dispatch Methods

In order to expand the computation capability of digital signal processing on a General Purpose Processor (GPP), we propose a fused microarchitecture that improves Instruction Level Parallelism (ILP) by supporting both in-order superscalar and very long instruction word (VLIW) dispatch methods in a single pipeline. This design is based on ARMv7-A&R Instruction Set Architecture (ISA). To provide a performance comparison, we first design an in-order superscalar processor, considering that ARM GPPs always adopt superscalar approaches. And then we expand VLIW dispatch method based on this processor, to realize the fused microarchitecture. The two designs are both evaluated on the Xilinx 7-series FPGA (XC7K325T-2FFG900C), using Xilinx Vivado design suite. The results show that, compared with the superscalar processor, the processor working under VLIW mode can improve the performance by 15% and 8%, respectively, when running EEMBC and DSPstone benchmarks. We also run the two benchmarks on ARM Cortex-A9 processor, which is integrated in the Zynq-7000 AP SoC device on Xilinx ZC706 evaluation board. The processor in VLIW mode shows 44% and 30% performance improvements than ARM Cortex-A9. The fused microarchitecture adopts a combined bimodal and PAp branch prediction method. This method achieves 93.7% prediction accuracy with limited hardware overhead.

Service-Oriented Architecture on FPGA-Based MPSoC

The integration of software services-oriented architecture (SOA) and hardware multiprocessor system-on-chip (MPSoC) has been pursued for several years. However, designing and implementing a service-oriented system for diverse applications on a single chip has posed significant challenges due to the heterogeneous architectures, programming interfaces, and software tool chains. To solve the problem, this paper proposes SoSoC, a service-oriented system-on-chip framework that integrates both embedded processors and software defined hardware accelerators s as computing services on a single chip. Modeling and realizing the SOA design principles, SoSoC provides well-defined programming interfaces for programmers to utilize diverse computing resources efficiently. Furthermore, SoSoC can provide task level parallelization and significant speedup to MPSoC chip design paradigms by providing out-of-order execution scheme with hardware accelerators. To evaluate the performance of SoSoC, we implemented a hardware prototype on Xilinx Virtex5 FPGA board with EEMBC benchmarks. Experimental results demonstrate that the service componentization over original version is less than 3 percent, while the speedup for typical software Benchmarks is up to 372x. To show the portability of SoSoC, we implement the convolutional neural network as a case study on both Xilinx Zynq and Altera DE5 FPGA boards. Results show the SoSoC outperforms state-of-the-art literature with great flexibility.

Gem5v: a modified gem5 for simulating virtualized systems

Virtualization is growing in different areas: from powerful servers in data centers to students' laptops and even cell phones. It can provide a more efficient use of hardware resources. Virtualization enables multiple virtual machines to run side-by-side in an isolated environment on a physical hardware. Modern processors are enhanced with technologies like Intel-VT and AMD-V that speed up virtual machines. However, there is still room for improving support of hardware for virtualization workloads. Gem5 is an open-source full system simulator capable of simulating a Chip-Multiprocessor with its caches, interconnection network, memory controllers among others. In its current state, gem5 does not support virtualized workloads. In this paper, we present a modified version of gem5, named gem5v, that simulates the behavior of a virtualization layer and can simulate virtual machines. We test this simulator in different scenarios using Parsec, Splash, MapReduce (Phoenix), SPEC and EEMBC benchmarks and compare its measured runtime with real systems. Results show 1---9 % difference between the simulated system and two virtualization softwares on a real hardware, namely KVM and VMware ESX. The comparison of vCPU overhead in VMware ESX and gem5v shows between 0.1 and 9 % difference.

Achieving spilling-friendly register file assignment for highly distributed register files

Distributed register file architectures divide registers into multiple sets, and it follows that the register files could be small. This can increase the frequency of spilling if register allocation encounters high register pressure, which will reduce the performance. That is, there is extra spilling to handle the pressure and results in performance decline. One of the factors that can produce high pressure is improper register file assignment. Register file assignment is a phase that assigns virtual registers to suitable register files and avoids communication costs. To reduce spilling in the phase of register file assignment, this paper proposes the SPIlling-FRiendly (SPIFR) method, which attempts to improve spilling by estimating the spilling cost from two aspects: assignment and spilling. We used MiBench and EEMBC benchmarks in experiments performed with the Open64-based compiler and a cycle-accurate instruction set simulator. The MiBench experimental results show that the SPIFR method improved the average cycle counts of the benchmarks by 6.0 %. For the kernels of the benchmarks, the method improved the average cycle counts by 20.5 % and reduced the average spilling ratio by 19.0 %. The results on the EEMBC benchmarks indicate that the method improved the cycle counts with the average speedup of 7.0 %, the speedup average of the kernel functions was 11.3 %, and the average reduction in the spilling ratio was 11.7 %, respectively. We conclude that the SPIFR method can reduce spilling and increase the performance.

Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays

Coarse-grained reconfigurable arrays (CGRAs) are a promising class of architectures conjugating flexibility and efficiency. Devising effective methodologies to map applications onto CGRAs is a challenging task, due to their parallel execution paradigm and constrained hardware resources. In order to handle complex applications, it is important to devise efficient strategies to partition a kernel into pieces that obey resource constraint and methodologies to schedule them on the underlying hardware. In this paper, we tackle these problems by proposing algorithms to address partitioning based on recursive searches over abstract trees. A novel scheduling strategy is also described that, leveraging differences in delays of various operations, is able to efficiently map operations on CGRA architectures. Experimental evidence on kernels derived from a diverse set of data flow graphs and EEMBC benchmarks demonstrate the efficacy of the described methods, which, when combined, achieve a higher runtime performance on a given mesh size than state-of-the-art approaches (as much as 38% for the benchmark applications considered).

GCC2Verilog Compiler Toolset for Complete Translation of C Programming Language into Verilog HDL

Reconfigurable computing using a field-programmable gate-array (FPGA) device has become a promising solution in system design because of its power efficiency and design flexibility. To bring the benefit of FPGA to many application programmers, there has been intensive research about automatic translation from high-level programming languages (HLL) such as C and C++ into hardware. However, the large gap of syntaxes and semantics between hardware and software programming makes the translation challenging. In this paper, we introduce a new approach for the translation by using the widely used GCC compiler. By simply adding a hardware description language (HDL) backend to the existing state-of-the-art compiler, we could minimize an effort to implement the translator while supporting full features of HLL in the HLL-to-HDL translation and providing high performance. Our translator, called GCC2Verilog, was implemented as the GCC's cross compiler targeting at FPGAs instead of microprocessor architectures. Our experiment shows that we could achieve a speedup of up to 34 times and 17 times on average with 4-port memory over PICO microprocessor execution in selected EEMBC benchmarks.

Instruction scheduling methods and phase ordering framework for VLIW DSP processors with distributed register files

Digital signal processors (DSPs) with very long instruction word (VLIW) data-path architectures are increasingly being deployed on embedded devices in video and other multimedia processing applications. To reduce the power consumption and design cost of VLIW DSP processors, distributed register files and multi-bank register architectures are being adopted to eliminate the amount of read/write ports associated with register files. This presents challenges for compilers attempting to generate efficient codes. In this paper we present an instruction scheduling method and phase ordering framework for such an architecture based on the well-known PALF scheme. The PALF scheme first performs bank partitioning followed by register allocation and then instruction scheduling. Our contribution includes the insertion of a pseudo instruction scheduler that performs bank assignment analysis before PALF assignment. We also enhance the PALF scheme by utilizing the program graph with cycle information generated by our pseudo scheduler. Finally, a ping-pong-aware scheduling policy is used in the scheduling phases to address the issue of limited temporal connectivities among register banks for DSP processors. Experiments were performed on an instruction set simulator for Parallel Architecture Core DSP processors based on the Open64 compiler infrastructure. Preliminary experiments with the EEMBC and MiBench benchmarks show that a compiler based on our proposed scheme for handling hardware constraints of VLIW scheduling on distributed register files exhibits performance superior to that of the PALF scheme.

Exploiting Thread-Level Parallelism in Lockstep Execution by Partially Duplicating a Single Pipeline

In most parallel loops of embedded applications, every iteration executes the exact same sequence of instructions while manipulating different data. This fact motivates a new compiler-hardware orchestrated execution framework in which all parallel threads share one fetch unit and one decode unit but have their own execution, memory, and write-back units. This resource sharing enables parallel threads to execute in lockstep with minimal hardware extension and compiler support. Our proposed architecture, called multithreaded lockstep execution processor (MLEP), is a compromise between the single-instruction multiple-data (SIMD) and symmetric multithreading/chip multiprocessor (SMT/CMP) solutions. The proposed approach is more favorable than a typical SIMD execution in terms of degree of parallelism, range of applicability, and code generation, and can save more power and chip area than the SMT/CMP approach without significant performance degradation. For the architecture verification, we extend a commercial 32-bit embedded core AE32000C and synthesize it on Xilinx FPGA. Compared to the original architecture, our approach is 13.5% faster with a 2-way MLEP and 33.7% faster with a 4-way MLEP in EEMBC benchmarks which are automatically parallelized by the Intel compiler. Keywords: ILP, TLP, SMT, CMP, MLEP.