Edge Delay Research Articles

Dead-Zone Free, Static Phase Offset Improvement Phase Detector for High Resolution and Low Jitter Delay-Locked Loop

This work presents a phase detector (PD) having dead-zone free and static phase offset improvement performance. The proposed phase detector inherits the low power consumption advantage of the conventional phase detector using two true-single-phase clocking (TSPC) DFFs. It also effectively reduces the static phase offset, even in the presence of inevitable charge pump current mismatch. And the dead-zone problem of conventional TSPC PD is overcome by using a falling edge delay inverter. The PD is implemented using a standard 180nm CMOS technology. The dimension of the PD’s layout is 11μm×16μm. Post-layout simulation shows that the power consumption is 53.8μW at 250MHz and 160μW at 800MHz. It achieves tiny static phase offset even if the charge pump has a 3.8% current mismatch.

Development of a High-Voltage Pulsed Electric Field Sterilization Power Supply Using a New Topology Circuit

Traditional thermal sterilization technology is easy to implement and safe, but it will destroy food nutrition and change food taste. Therefore, people began to turn their attention to non-thermal sterilization. High-voltage pulsed electric field sterilization technology is one of them; it has attracted much attention because of its high efficiency and little damage to food. Different types of loads will cause serious trailing of the pulse falling edge. In view of this situation, this paper proposes a new topology circuit that combines a solid-state switch with a half-bridge Marx generator. It can be used for high-voltage pulsed electric field sterilization. By improving the structure of the classical Marx circuit, the high-voltage pulse power supply of the new topology circuit has the characteristics of steep rising edge and short falling edge delay; does not require isolation inductance or isolation resistance, which solves the isolation problem between the DC charging power supply and the high-voltage terminal; and has a good voltage-clamping function and load adaptability. The working process of the topology circuit under resistive, capacitive and inductive loads and the voltage clamping effect when the solid-state switch does not work properly in the discharge process are analyzed in detail. The power supply is composed of an adjustable DC power supply, five-stage half-bridge Marx generator and control protection circuit. A field programmable gate array (FPGA) is used as the controller to generate control signals, and optical fiber isolation is used to provide control signals for the main loop. The power supply can output a high-voltage square wave pulse with a voltage amplitude of 10 kV, maximum pulse number of 1000 per second, maximum pulse width of 20 μs, pulse rise time of smaller than 300 ns and short pulse drop time, and the repeated voltage amplitude, frequency and pulse width are adjustable, which can meet the requirements of a high-voltage pulse sterilization experiment.

Joint content caching and fetching scheme with cooperative transmission in hierarchical networks

Concerned with the surge of content-centric applications, it is challenging to balance network traffic and cater to low-delay requirements. Hierarchical caching architecture of both edge network (EN) and core network (CN) emerges and leverages caching resources to reduce the delivery delay of contents. Most previous work takes an impractical assumption to treat the CN as a content provider, which neglects the collaboration by intermediate CN caches. Most importantly, it is still necessary to thoroughly study the tradeoff between CN delay and edge delay for files delivery so as to minimize the overall delivery delay across the network. In this paper, we consider a hierarchical caching network with distributed CN nodes and edge nodes, where cooperative transmission is enabled for edge nodes to transmit multi-files simultaneously. This poses a joint optimization problem of hierarchical file caching and fetching to minimize the overall delivery delay of requests. Since the problem is NP-hard, we decompose the original problem and design an iterative algorithm to address it. Numerical results validate that the proposed scheme can find a balanced solution between lowering edge delay by utilizing coordinated CN caching and lowering CN delay by solely relying on edge caching.

Two-layered blockchain-based admission control for secure UAV networks

The frequent replacement requirement of UAVs for recharging outputs an extreme number of messaging for admission control of end-users. There are many studies that try to optimize the network capacity in an energy-efficient manner. However, they do not consider the security of data and control channels, which is the urgent requirement of 5G. Blockchain handles secure systems. However, the high numbered transactions in blockchain may cause bottlenecks while considering computational delay and throughput of end-user. In UAVs, a high percentage of battery is consumed for computational tasks instead of communication tasks. Therefore, to handle security by considering the computational needs, this paper proposes a novel two-layered blockchain-based admission control in UAV networks. It has two layers named as side-chain for UAVs and off-chain for end-users building in a decentralized manner. In the former one, the data bearer of end-users is protected by the side-chain of each transaction which is signed by admitted end-users and UAVs. Here, each transaction includes a unique transaction id, nonce value, IMSI of the user, RNTI of UAV, signed data, and hash value. In the latter one, the off-chain is built by signing admission contracts between users in a decentralized manner and the Merkle tree is constructed for the off-chain where the root hash is only stored in a side-chain. Then, the number of transactions that should be validated is extremely decreased. Moreover, PoS is used for the validation of transactions where the validator is selected randomly instead of the competition requirement as in PoW. A novel blockchain-based admission control algorithm isolates readmission control of end-users to 5G core-side during UAV replacement. According to performance evaluation, the proposed approach serves end-users by 64.2% better QoS than the conventional one during UAV replacement. Moreover, it keeps edge delay in acceptable range by using Merkle tree and PoS.

Congestion Managed Multicast Routing in Wireless Mesh Network

To provide broad band connectivity to the mobile users and to build a self-structured network, where it is not possible to have wired network, “Wireless Mesh Networks” are the most vital suitable technology. Routing in Wireless Mesh Networks is a multi-objective nonlinear optimization problem with some constraints. We explore multicast routing for least-cost, delay-sensitive and congestion-sensitive in optimizing the routing in Wireless mesh networks (WMNs). In this work different parameters are associated like edge cost, edge delay and edge congestion. The aim is to create a tree traversing which the set of target nodes are spanned, so as to make the cost and congestion to be minimum with a bounded delay over the path between every pair of source and destination. Since searching optimal routing satisfying multi constraints concurrently is an NP complete problem, we have presented a competent estimated algorithm certified with experimental results, which shows that the performance of presented algorithm is nearly optimum.

Workflow offloading with privacy preservation in a cloud‐edge environment

AbstractOwing to the limited computing capability of edge cloudlets, use of cloud platforms to provide computation‐intensive services as an assistant should be studied. Offloading, among the key techniques in the cloud‐edge environment, is plagued by the serious problem of privacy disclosure. In addition, the edge does not have access control of terminals, and the controller working the edge that makes offloading decisions, must not be allowed access to any information regarding the contents of the terminal. Thus, this study introduced a system architecture wherein the data was separated from the control plane to minimize systemic risk and optimize the offloading process towards makespan and cost reduction. Traditional methods of privacy preservation are dependent on encryption of total or content awareness. Edge privacy preservation renders maintaining edge delay advantages a challenge because traditional architectures result in edges being engaged with data encryption and decryption. Moreover, in content applications such as video compression and intelligent collaborative applications, users are unaware of content considered private data, and the relative privacy sensitivity and security priority of tasks. The proposed solution avoids side‐channel attacks by eliminating the individual characteristics via risk‐free constraints under a certain amount of entropy at the security level. Further, a smart optimum approach based on MOEA/D was employed to strike the balance between privacy preservation and the cost/latency of activity. This reduces the burden on edge servers, enhances security based on a better offloading strategy, and protects against threats and attacks using a reasonable system architecture. Through experiments on different types of workflow parameters the validity and effectiveness of the offloading algorithm with privacy preservation was demonstrated.

Relationship between employees' career maturity and career planning of edge computing and cloud collaboration from the perspective of organizational behavior.

A new IoT (Internet of Things) analysis platform is designed based on edge computing and cloud collaboration from the perspective of organizational behavior, to fundamentally understand the relationship between enterprise career maturity and career planning, and meet the actual needs of enterprises. The performance of the proposed model is further determined according to the characteristic of the edge near data sources, with the help of factor analysis, and through the study and analysis of relevant enterprise data. The model is finally used to analyze the relationship between enterprise career maturity and career planning through simulation experiments. The research results prove that career maturity positively affects career planning, and vocational delay of gratification plays a mediating role in career maturity and career planning. Besides, the content of career choice in career maturity is influenced by mental acuity, result acuity and loyalty. The experimental results indicate that when the load at both ends of the edge and cloud exceeds 80%, the edge delay of the IoT analysis platform based on edge computing and cloud collaboration is 10s faster than that of other models. Meanwhile, the system slowdown is reduced by 36% while the stability is increased when the IoT analysis platform analyzes data. The results of the edge-cloud collaboration scheduling scheme are similar to all scheduling to the edge end, which saves 19% of the time compared with cloud computing to the cloud end. In Optical Character Recognition and Aeneas, compared with the single edge-cloud coordination mode, the model with the Nesterov Accelerated Gradient algorithm achieves the optimal performance. Specifically, the communication delay is reduced by about 25% on average, and the communication time decreased by 61% compared with cloud computing to the edge end. This work has significant reference value for analyzing the relationship between enterprise psychology, behavior, and career planning.

Price of Anarchy in Networks with Heterogeneous Latency Functions

We address the performance of selfish network routing in multicommodity flows where the latency or delay function on edges is dependent on the flow of individual commodities, rather than on the aggregate flow. An application of this study is the analysis of a network with differentiated traffic, that is, in transportation networks where there are multiple types of traffic and in networks where traffic is prioritized according to type classification. We consider the inefficiency of equilibrium in this model and provide price of anarchy bounds for networks with k (types of) commodities, where each link is associated with heterogeneous polynomial delays, that is, commodity i on edge e faces delay specified by a multivariate polynomial dependent on the individual flow of each commodity on the edge. We consider both atomic and nonatomic flows and show bounds on the price of anarchy that depend on the relative impact of each type of traffic on the edge delay when the delay functions are polynomials of degree θ, for example, [Formula: see text]. The price of anarchy is unbounded for arbitrary polynomials. For networks with decomposable delay functions where the delay is the same for all commodities using the edge, we show improved bounds on the price of anarchy, for both nonatomic and atomic flows. The results illustrate that the inefficiency of selfish routing worsens in the case of heterogeneous delays compared with the standard delay functions that do not consider type differentiation.

Road to 5G Reduced-Latency: A Software Defined Handover Model for eMBB Services

Recently, handover execution has still been damaging 5G latency requirement due to having three states in virtual evolved packet core (vEPC). Here, the desired end-to-end delay (e2eDelay) should be less than 4 m/sec without any mobility interruption on an enhanced mobile broadband (eMBB) service of vEPC. To handle this requirement, we need to focus on the Markov model of e2eDelay. It can be measured by the concatenation of edge and core delays in the downlink eMBB service from a remote source to a mobile user. Here, edge delay is directly affected by the core network via a decreased packet delivery ratio to edge under huge-traffic intensity background. Therefore, target eNodeB decision by considering only edge network can be misleading. To overcome this, we jointly consider edge and core delays, which are differently affected by each handover states: 1) preparation, 2) execution, and 3) completion. The joint consideration of edge and core can be only handled with a novel cost-effective software-defined ultra-dense network (SDUN) framework by dynamically removing state 2). It triggers handover via network-centric monitoring; and then, it predetermines optimal TeNB with a proposed optimization formula and shortest core path according to traffic intensities of OpenFlow switches. Here, SDUN controller is cost-efficient by the proposed parallel runnable algorithms: parallel edge delay optimization and parallel shortest delay path. In the performance evaluation SDUN is first emulated for a specific eMBB traffic, i.e., QUIC based HTTP/3 video content traffic with 1080p resolution, and second simulated in system-level on MATLAB. It meets 5G requirements as follows: SDUN decreases core delay 7.16 m/sec per a UE under huge-traffic intensity and keeps edge delay under 5G requirement with 20% more delivery ratio than conventional one. Moreover, the cost of SDUN controller is analyzed as O(k4log2(k)) and the cost efficiency is observed as the 50% increased scalability level with the acceptable 8% extra virtual memory usage.

Dynamic voltage‐sharing among series‐connected IGBTs during turning‐on process

An active clamping circuit for voltage sharing among series-connected insulated gate bipolar translators (IGBTs) during turning-on process is proposed at first, which detects the C-E voltage of the leading IGBT and generates gate pumping current to slow down the turning-on speed, and thus reduces the voltage difference between the IGBTs. Then, a turn-on edge regulation algorithm for the driving signal is proposed, which further reduces the voltage spike and turn-on power loss, and optimises the regulation speed. A time detection circuit is introduced to detect the pulse signal indicating the working time of the active clamping circuit for driving signal regulation. The turn-on edge regulation for each IGBT is determined by the feature that the rising edge of the detected pulse signal coincides with the corresponding IGBT turn-on edge delay. The experimental results prove the feasibility and effectiveness of the proposed method.

Multimedia Transmission in Food Network System Based on LD/R Path Algorithm

The characteristic of multi-media Transmission in food network system is analyzed and the technology requirements are studied. Parameters of performance are put forward to scaling QoS. The influencing factors are analyzed and solving methods are proposed. This study proposes LD/RPath algorithm LD/RPath estimates the dynamic data volume on service nodes and links through reasonable data volume approximation. And the data splitting technique is imported to convert the node delay into the edge delay. In the mean time, the reliability of nodes is considered so that the multimedia delivery problem is transformed into a conventional shortest path problem. The experimental simulation results show that the algorithm is a kind of high efficient and reliable algorithm spending smaller complexity achieving good path selection performance.

A Novel Dead-Time Control Method for Double End Converter

In order to achieve symmetry of the drive signal and suppress the magnetic bias, a novel dead-time control method for the double end converter is put forward in this paper, which can generate two independent and complementary PWM waveforms by configuring EPWM (Enhanced Pulse Width Modulator) module. The magnetic bias problems of the double end converter, principle of EPWM module and adjustment process of the dead-time control method are analyzed. Two different dead-times can de realized by setting the rising edge delay and falling edge delay of the corresponding registers in Dead-band (DB) module in one cycle to meet the requirement of drive signals. Experimental research on the novel dead-time control method is done on the push-pull forward circuit and the experiment results verify the feasibility of the proposed method.

A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator

A DLL based on a dual edge triggered phase detector (DET-PD) is proposed for a clock generator in low-power systems. The proposed DLL has a faster lock speed with the same loop dynamics compared to the conventional DLL based on a single-edge triggered phase detector (SET-PD). The proposed DET-PD solves the problem of a narrow capture range or low phase detector gain associated with the conventional DET-PD. In addition, the proposed duty cycle difference compensation circuit (DDC) prevents the increase in the phase offset when the two inputs to the DET-PD have different duty cycle. It also controls the DLL bandwidth to maintain the DLL jitter by controlling the negative edge delay difference tracking. Finally, the proposed duty cycle keeper (DCK) enlarges the duty cycle keeping range of the DLL output. The proposed DLL is fabricated using 0.18-μm process technology. It has an area of 0.035 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a power consumption of 19 mW at 800 MHz operation. Its lock speed is over 1.9 times faster than that of the DLL based on the SET-PD without degrading the jitter.

Stochastic selfish routing

We present a model for routing games in which edge delay functions are uncertain and users are risk-averse. We investigate how the uncertainty and risk-aversion transform the classical theory on routing games, including equilibria existence, characterization and price of anarchy.

Service-Oriented Reliable Multimedia Delivery Algorithm

针对普适环境中可靠的多媒体传输问题,提出了LD/RPath(lowest delay/reliability path)算法.LD/RPath算法通过合理的数据量近似来拟合服务节点和传输边上动态变化的数据量,引入节点分裂技术将节点时延转化为边时延,同时考虑了节点可靠性因素,并作为时延的系数.通过这样的处理,该传输问题可以转化为传统的最短路径问题来解决.实验结果表明,LD/Rpath能够达到较好的路径选择效果,且系统开销较低.;This paper proposes an efficient algorithm LD/RPath (lowest delay/reliability path) for service-oriented reliable multimedia delivery in a pervasive environment. LD/RPath estimates the dynamic data volume on service nodes and links through reasonable data volume approximation. And the data splitting technique is imported to convert the node delay into the edge delay. In the mean time, the reliability of nodes is considered as a coefficient of delay, so that the multimedia delivery problem is transformed into a conventional shortest path problem. Simulation results prove that LD/RPath achieves good path selection performance while imposing low overhead to the system.

On the convergence condition and convergence time of BGP

The Internet composes of thousands of Autonomous System (ASes). The Border Gateway Protocol (BGP) is the standard protocol for sharing inter-domain routing information. Unlike OSPF and IS–IS, BGP allows an AS to use a lot of attributes to express semantic rich routing policies that are consistent with its desired economic, business, performance, and security goals. However, the expressiveness could cause to delay convergence or even divergence in BGP. Recent work do not rigorously analyze the impact of the general routing policies on the convergence condition and convergence time of BGP, especially considering the widely used Multi-Exit Discriminator (MED) attribute. In this paper, we will fill this gap and give the rigorous analysis on the impact of the general routing policies on the convergence condition and convergence time of BGP, including MED attribute. We first introduce a timeless model to represent BGP with the general routing policies including the MED attribute. By incorporating the timeless model we derive a sufficient condition on these general routing policies for robust convergence of BGP. We then extend the timeless model to the real-time model by adding the edge delay. Finally, we find an upper bound on convergence time of BGP by incorporating the real-time model.

Fiber Bragg grating-based band edge delay line for radio frequency (RF) photonics applications

A fiber Bragg grating (FBG)-based delay line (or phase shifter) has been developed for microwave over fiber and phased array antenna (PAA) applications. The scheme uses band edge time delay of tunable fiber gratings to provide a continuously controllable microwave time delay or phase shift. Following the formulation and analysis of the device behavior, simulations of amplitude and phase responses are conducted. The results confirm the validity of theoretical predictions.

United stabilizing scheme for edge delay in optical burst switched networks

A novel scheme, namely united stabilizing scheme for edge delay, is introduced in optical burst switched networks. In the scheme, the limits of burst length and assembly time are both set according to certain qualifications. For executing the scheme, the conception for unit input bit rate is introduced to improve universality, and the assembly algorithm with a buffer safety space under the self-similar traffic model at each ingress edge router is proposed. Then, the components of burst and packet delay are concluded, and the equations that limits of burst length and assembly time should satisfy to stabilize the burst edge delay under different buffer offered loads are educed. The simulation results show that united stabilizing scheme stabilizes both burst and packet edge delay to a great extent when buffer offered load changes from 0.1 to 1, and the edge delay of burst and packet are near the limit values under larger offered load, respectively.

Multicast routing for multimedia communication

The authors present heuristics for multicast tree construction for communication that depends on: bounded end-to-end delay along the paths from source to each destination and minimum cost of the multicast tree, where edge cost and edge delay can be independent metrics. The problem of computing such a constrained multicast tree is NP-complete. It is shown that the heuristics demonstrate good average case behavior in terms of cost, as determined by simulations on a large number of graphs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A study on the delay time of a BiCMOS basic gate

AbstractTheoretical analysis and circuit simulation in regard to delay time for a BiCMOS basic gate have been accomplished. First, a basic gate is expressed in the form of an equivalent circuit for clarifying the influence of each device parameter for a bipolar transistor on delay time. Then analytical equations are obtained which are used to analyze the rising edge delay time. In these equations, conditions such as current dependency of fT in all current regions and the change in junction capacitances due to bias change are taken into consideration.Confirming the consistency between analytical and simulation results for the rising edge delay time, the analysis for the falling edge delay time was newly developed. This has been done considering a phenomenon wherein the driving capability for the MOS transistor in a BiCMOS basic gate decreases due to the voltage drop across a base resistor in a bipolar transistor. As a result, good consistency between analytical and simulation results has been achieved and a new analytical method for the falling edge delay time has been established. The base resistor influence on the falling edge delay time has also been clarified by a circuit simulation.