ECC Scheme Research Articles

A Real-Time Error Detection (RTD) Architecture and Its Use for Reliability and Post-Silicon Validation for F/F Based Memory Arrays

This work proposes in-situ Real-Time Error Detection (RTD): embedding hardware in a memory array for detecting a fault in the array when it occurs, rather than when it is read. RTD breaks the serialization between data access and error-detection and, thus, it can speed-up the access-time of arrays that use in-line error-correction. The approach can also reduce the time needed to root-cause array related bugs during post-silicon validation and product testing. The paper introduces a two-dimensional error-correction scheme based on RTD and, also, presents a proactive error-correction method that combines RTD with demand-scrubbing. The work describes how to build RTD into a memory array with flip-flops to track in real-time the column-parity. A comparison of the proposed two-dimensional ECC scheme, as compared to single-error-correction-double-error-detection, shows that the RTD design has comparable error-detection-and-correction strength and, depending on the array dimensions and configuration, RTD reduces access time by 4% to 26% at an area and power overhead (negative is a reduction) between -7% to 33% and -42% to 86% respectively.

An Efficient Blockchain Based Data Access with Modified Hierarchical Attribute Access Structure with CP-ABE Using ECC Scheme for Patient Health Record

Secure patient health record (PHR) information exchange via cloud computing is a considerable security risk to user privacy. The fundamental reason of this issue is cloud computing’s reliance on trustworthy third parties to share data across it. To exchange data securely, many conventional cryptographic algorithms employ various keying approaches. However, relying on a trusted third party compromises the privacy of consumers’ data. To offer secure communication without the involvement of a third party, a distributed blockchain based (DBC) ciphertext–policy attribute-based encryption (CP-ABE) approach is employed in this study. Because of bilinear paring and simple scalar multiplication factors, the proposed CP-ABE system is entirely dependent on elliptic curve cryptography to reduce complexity. Furthermore, the data requester provides dynamic attributes, and a user-centric access policy is created, allowing multiple authorities to manage the attributes and provide data access. Data confidentiality, data authentication, user authentication, and tamper-proof data are all guaranteed by the suggested method. The DBC-CP-ABE method is used to provide user-centric access policies and effective key management.

A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme

Circuit and design techniques are presented for enhancing the performance and reliability of a 3-D-stacked high bandwidth memory-2 extension (HBM2E). A data-bus window extension technique is implemented to cope with reduced clock cycle time ranging from data-path architecture, through-silicon via (TSV) placement, and TSV-PHY alignment. A power TSV placement in the middle of array and at the chip edge along with a dedicated top metal for power mesh improves power IR drop by 62%. An on-die ECC (OD-ECC) scheme featuring a self-scrubbing function is designed to be orthogonal to system ECC. An uncorrectable bit error rate (UBER) is improved by 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> times with the proposed OD-ECC and scrubbing scheme. A memory built-in self-test (MBIST) block supports low-frequency cell and core test in a parallel manner and all channel at-speed operation with adjustable ac parameters. The proposed parallel-bit MBIST reduces test time by 66%. A 16-GB HBM2E fabricated in the second generation of 10-nm class DRAM process achieves a bandwidth up to 640 GB/s (5 Gb/s/pin) and provides a stable bit-cell operation at a high temperature (e.g., 105 ° C).

Management of Next-Generation NAND Flash to Achieve Enterprise-Level Endurance and Latency Targets

Despite its widespread use in consumer devices and enterprise storage systems, NAND flash faces a growing number of challenges. While technology advances have helped to increase the storage density and reduce costs, they have also led to reduced endurance and larger block variations, which cannot be compensated solely by stronger ECC or read-retry schemes but have to be addressed holistically. Our goal is to enable low-cost NAND flash in enterprise storage for cost efficiency. We present novel flash-management approaches that reduce write amplification, achieve better wear leveling, and enhance endurance without sacrificing performance. We introduce block calibration, a technique to determine optimal read-threshold voltage levels that minimize error rates, and novel garbage-collection as well as data-placement schemes that alleviate the effects of block health variability and show how these techniques complement one another and thereby achieve enterprise storage requirements. By combining the proposed schemes, we improve endurance by up to 15× compared to the baseline endurance of NAND flash without using a stronger ECC scheme. The flash-management algorithms presented herein were designed and implemented in simulators, hardware test platforms, and eventually in the flash controllers of production enterprise all-flash arrays. Their effectiveness has been validated across thousands of customer deployments since 2015.

Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories

Novel fault leveling techniques based on address remapping (AR) are proposed in this paper. We can change the logical-to-physical address mapping of the page buffer such that faulty cells within a flash page can be evenly distributed into different codewords. Therefore, the adopted ECC scheme can correct them effectively. Based on the production test or on-line BIST results, the fault bitmap can be used for executing the heuristic fault leveling analysis (FLA) algorithm and evaluating control words used to steer fault leveling. A new page buffer architecture suitable for address remapping is also proposed. According to experimental results, repair rate, yield, and reliability can be improved significantly with negligible hardware overhead.

Secure medical data transmission by using collaborative neighbour based method in WBAN

Wireless body area network or body area sensor network is wearable device in human body. In online healthcare, transmitting of medical data from sensor node to destination, medical device is used with the member function. However, WBAN has faced many security issues and challenges when transmitting the data. Existing ECC secure key distribution methods are implemented, using this method the time is consumed, efficiency and security of data was discussed. ECC scheme implements for secure key distribution and data exchange. The proposed collaborative neighbour based method is used. Overall, the proposed method proves a better security in healthcare devices. Collaborative neighbour selection and time taken on packet forwarding from one point to another identify the presence of data being appended in the framework. The proposed framework includes enhancement to security and efficiency by forwarding the node information and performing the verification procedure based on the received packet to filter the false data. Extensive experiments and simulation results indicate that, in terms of bandwidth efficiency, packet transmission, network security and processing time, performs favourably compared to existing ECC mechanisms in wireless body area sensor network.

Secure medical data transmission by using collaborative neighbour based method in WBAN

Wireless body area network or body area sensor network is wearable device in human body. In online healthcare, transmitting of medical data from sensor node to destination, medical device is used with the member function. However, WBAN has faced many security issues and challenges when transmitting the data. Existing ECC secure key distribution methods are implemented, using this method the time is consumed, efficiency and security of data was discussed. ECC scheme implements for secure key distribution and data exchange. The proposed collaborative neighbour based method is used. Overall, the proposed method proves a better security in healthcare devices. Collaborative neighbour selection and time taken on packet forwarding from one point to another identify the presence of data being appended in the framework. The proposed framework includes enhancement to security and efficiency by forwarding the node information and performing the verification procedure based on the received packet to filter the false data. Extensive experiments and simulation results indicate that, in terms of bandwidth efficiency, packet transmission, network security and processing time, performs favourably compared to existing ECC mechanisms in wireless body area sensor network.

Security Implementation in WSN with Symmetric and Matrix Mapping on Asymmetric ECC Cryptographic Techniques

As the wireless sensor networks are easily deployable, the volume of sensor applications has been increased widely in various fields of military and commercial areas. In order to attain security on the data exchanged over the network, a hybrid cryptographic mechanism which includes both symmetric and asymmetric cryptographic functions is used. The public key cryptographic ECC security implementation in this paper performs a matrix mapping of data’s at the points on the elliptical curve, which are further encoded using the private symmetric cipher cryptographic algorithm. This security enhancement with the hybrid mechanism of ECC and symmetric cipher cryptographic scheme achieves efficiency in energy conservation of about 7% and 4% compared to the asymmetric and symmetric cipher security implementations in WSN.

E 3 CC: A memory error protection scheme with novel address mapping for subranked and low-power memories

This study presents and evaluates E 3 CC (Enhanced Embedded ECC), a full design and implementation of a generic embedded ECC scheme that enables power-efficient error protection for subranked memory systems. It incorporates a novel address mapping scheme called Biased Chinese Remainder Mapping (BCRM) to resolve the address mapping issue for memories of page interleaving, plus a simple and effective cache design to reduce extra ECC traffic. Our evaluation using SPEC CPU2006 benchmarks confirms the performance and power efficiency of the E 3 CC scheme for subranked memories as well as conventional memories.

Post-manufacturing, 17-times acceptable raw bit error rate enhancement, dynamic codeword transition ECC scheme for highly reliable solid-state drives, SSDs

A dynamic codeword transition ECC scheme is proposed for highly reliable solid-state drives, SSDs. By monitoring the error number or the write/erase cycles, the ECC codeword dynamically increases from 512 Byte (+parity) to 1 KByte, 2 KByte, 4 KByte…32 KByte. The proposed ECC with a larger codeword decreases the failure rate after ECC. As a result, the acceptable raw bit error rate, BER, before ECC is enhanced. Assuming a NAND Flash memory which requires 8-bit correction in 512 Byte codeword ECC, a 17-times higher acceptable raw BER than the conventional fixed 512 Byte codeword ECC is realized for the mobile phone application without an interleaving. For the MP3 player, digital-still camera and high-speed memory card applications with a dual channel interleaving, 15-times higher acceptable raw BER is achieved. Finally, for the SSD application with 8 channel interleaving, 13-times higher acceptable raw BER is realized. Because the ratio of the user data to the parity bits is the same in each ECC codeword, no additional memory area is required. Note that the reliability of SSD is improved after the manufacturing without cost penalty. Compared with the conventional ECC with the fixed large 32 KByte codeword, the proposed scheme achieves a lower power consumption by introducing the “best-effort” type operation. In the proposed scheme, during the most of the lifetime of SSD, a weak ECC with a shorter codeword such as 512 Byte (+parity), 1 KByte and 2 KByte is used and 98% lower power consumption is realized. At the life-end of SSD, a strong ECC with a 32 KByte codeword is used and the highly reliable operation is achieved. The random read performance is also discussed. The random read performance is estimated by the latency. The latency is below 1.5 ms for ECC codeword up to 32 KByte. This latency is below the average latency of 15,000 rpm HDD, 2 ms.

Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC

This paper presents an SRAM architecture employing a multiword-based ECC (MECC) scheme for soft error mitigation and a row virtual ground technique for array leakage reduction. The MECC combines four data words to form a 128 bit composite ECC word, two of which are interleaved in a row to mitigate cosmic neutron-induced multi-bit errors. The use of a composite word reduces the number of check-bits by 68%, however, requires a unique write operation that updates the check-bits by writing one data word while reading the other three data words. The ground potential of the composite word is raised to a nonzero value during retention in order to limit the leakage power consumption. A critical charge-based soft error rate (SER) model is proposed to estimate the resulting increase in the SER. Both the MECC scheme and the SER model are verified by implementing a 64-kb SRAM macro in 90 nm CMOS technology. The SRAM consumes 5.34 pJ energy with a data latency of 3.3 ns, thus showing up to 82% per-bit energy saving and 8x speed improvement over previously reported multiword ECC schemes. Accelerated neutron radiation test of the SRAM confirms 85% soft error correction by the MECC and 90% accuracy of the SER model.

A 130-nm triple-V/sub t/ 9-MB third-level on-die cache for the 1.7-GHz Itanium/spl reg/ 2 processor

The 18-way set-associative, single-ported 9 MB cache for the Itanium 2 processor uses 210 identical 48-kB sub-arrays with a 2.21-/spl mu/m/sup 2/ cell in a 130-nm 6-metal technology. The processor runs at 1.7 GHz at 1.35 V and dissipates 130 W. The 432-mm/sup 2/ die contains 592 M transistors, the largest transistor count reported for a microprocessor. This paper reviews circuit design and implementation details for the L3 cache data and tag arrays. The staged mode ECC scheme avoids a latency increase in the L3 tag. A high V/sub t/ implant improves the read stability and reduces the sub-threshold leakage.

Primary steps of oxidation and electronic interactions in anodic cleavage of $alpha;,$omega;-diisocyanurate substituted dialkyl disulfides

The electrochemical oxidation of 1,1′-bis(3,5-dimethyl-[1,3,5]triazinane-2,4,6-trionyl)-α,α′-diorganyl-ω,ω′-disulfides involves a fast electron transfer followed by two chemical steps according to a ECC scheme. Using MM+, PM3 and ab initio SCF/3-21G∗ molecular modeling it was shown that the low oxidation potential and the smallest current-determining cleavage rate constant in the reaction series of the disulfide with (CH2)6 spacer between SS bridge and the terminal heterocycles is due to an interaction of the π-components of the highest filled orbitals of the two heterocycles (HOMO and HOMO-1) with the LUMO (n-orbital of S) of the cation radical.

Primary steps of oxidation and electronic interactions in anodic cleavage of α,ω-diisocyanurate substituted dialkyl disulfides

The electrochemical oxidation of 1,1′-bis(3,5-dimethyl-[1,3,5]triazinane-2,4,6-trionyl)-α,α′-diorganyl-ω,ω′-disulfides involves a fast electron transfer followed by two chemical steps according to a ECC scheme. Using MM+, PM3 and ab initio SCF/3-21G ∗ molecular modeling it was shown that the low oxidation potential and the smallest current-determining cleavage rate constant in the reaction series of the disulfide with (CH 2) 6 spacer between SS bridge and the terminal heterocycles is due to an interaction of the π-components of the highest filled orbitals of the two heterocycles (HOMO and HOMO-1) with the LUMO ( n-orbital of S) of the cation radical.