Early Performance Estimation Research Articles

EPE‐Mobile—A framework for early performance estimation of mobile applications

SummaryConsidering the constrained resources of mobile devices, a thorough performance evaluation of a mobile application is crucial. However, performance evaluation in the mobile domain is still a manual and time‐consuming task. The diversity of mobile devices only increases the complexity of this task. We propose EPE‐Mobile, a framework to automate early performance estimation in mobile applications. It is composed of a configurable library of basic operations and an engine that automatically creates a synthetic program based on the specification of a new app. The synthetic program that EPE‐Mobile generates provides feedback for mobile developers at the first design stages and before the actual implementation of a new application. The fast evaluation can also guide developers in optimizing their applications or in choosing devices with the best trade‐off between cost and performance to run a given application. Finally, developers can reuse the data collection infrastructure of the framework to collect performance data during all development stages. We validate the proposed framework using 4 applications from the Android Play Store. Based on their specifications, 4 synthetic programs were generated and executed on different devices. We compared the results to those obtained from the execution of the actual applications in the same devices. Experimental results show that it is possible to create synthetic applications with similar behavior to that of real applications and, thus, classify devices based on the actual application needs. The framework uses aspect‐oriented programming to collect the metrics of interest. This approach provides increased modularity and separation of concerns, thus facilitating the improvement of the framework itself, by adding other metrics or basic operations.

Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project

The design of high-performance application-specific multi-core processor systems still is a time consuming task which involves many manual steps and decisions that need to be performed by experienced design engineers. The ASAM project sought to change this by proposing an automatic architecture synthesis and mapping flow aimed at the design of such application specific instruction-set processor (ASIP) systems. The ASAM flow separated the design problem into two cooperating exploration levels, known as the macro-level and micro-level exploration. This paper presents an overview of the micro-level exploration level, which is concerned with the analysis and design of individual processors within the overall multi-core design starting at the initial exploration stages but continuing up to the selection of the final design of the individual processors within the system. The designed processors use a combination of very-long instruction-word (VLIW), single-instruction multiple-data (SIMD), and complex custom DSP-like operations in order to provide an area- and energy-efficient and high-performance execution of the program parts assigned to the processor node.In this paper we present an overview of how the micro-level design space exploration interacts with the macro-level, how early performance estimates are used within the ASAM flow to determine the tasks executed by each processor node, and how an initial processor design is then proposed and refined into a highly specialized VLIW ASIP. The micro-level architecture exploration is then demonstrated with a walk-through description of the process on an example program kernel to further clarify the exploration and architecture specialization process.The main findings of the experimental research are that the presented method enables an automatic instruction-set architecture synthesis for VLIW ASIPs within a reasonable exploration time. Using the presented approach, we were able to automatically determine an initial architecture prototype that was able to meet the temporal performance requirements of the target application. Subsequently, refinement of this architecture considerably reduced both the design area (by 4x) and the active energy consumption (by 2x).

Study of Voltage-Controlled Characteristics for Thermoelectric Coolers

Based on the Peltier effect, thermoelectric coolers (TECs) have been widely used in solving thermal management issues for semiconductor devices such as semiconductor laser, charge-coupled devices and nanoelectronic circuits with hot-spots. However, performance control mechanisms especially voltage-controlled parameters for TEC still face challenges. In this paper, a standard mathematical model for multi-stage TECs is proposed with thermal resistances from both sides and performance parameters dependent on voltage. The proposed models agreed with experimental results. Compared with the available model, the relative standard deviations between the obtained equivalent thermal conductivity model and experimental results at 25°C and 50°C are decreased by 88.87% and 30.14%, respectively. Also, the relative standard deviations between the proposed thermoelectric figure of merits model and calculated results based on experiments at two different temperatures are decreased by 84.45% and 62.94%, respectively. The results provide a controllable method of thermoelectric characteristics with high accuracy, which can be employed for early thermometric performance estimation for TEC design.

Analytical Model for High–Level Area Estimation of FPGA Design

FPGAs have been used as a target platform because they have increasingly interesting in system design and due to the rapid technological progress ever larger devices are commercially affordable. These trends make FPGAs an alternative in application areas where extensive data processing plays an important role. Consequently, the desire emerges for early performance estimation in order to quantify the FPGA approach. A mathematical model has been presented that estimates the maximum number of LUTs consumed by the hardware synthesized for different FPGAs using LLVM.. The motivation behind this research work is to design an area modeling approach for FPGA based implementation at an early stage of design. The equation based area estimation model permits immediate and accurate estimation of resources. Two important criteria used to judge the quality of the results were estimation accuracy and runtime. Experimental results show that estimation error is in the range of 1.33% to 7.26% for Spartan 3E, 1.6% to 5.63% for Virtex-2pro and 2.3% to 6.02% for Virtex-5.

A Review of FPGA-based design methodologies for efficient hardware Area estimation

In recent years, FPGA's have become increasingly important and have found their way into system design. So, the desire emerges for a means that allows early area and performance estimation Understanding how a design maps to them and consumes various FPGA resources can be difficult to predict, so typically designers are forced to run full synthesis on each iteration of the design. For complex designs that involve many iterations and optimizations, the run-time of synthesis can be quite prohibitive .However, to achieve high performance; FPGA must be supported by efficient design methodology and optimization techniques. The motivation behind this work is to review different FPGA based design methodology and optimization techniques that can be employed to efficiently estimate hardware area utilized in terms of look up table (LUT'S) or configurable logic blocks (CLB'S). Keyword:HW/SW Partitioning, Area Estimation, Latency Estimation

Incentivizing wood-based Fischer–Tropsch diesel through financial policy instruments: An economic assessment for Norway

The objective of this study is to evaluate a select set of financial incentive instruments that can be employed by the Norwegian government for encouraging early investment and production experience in wood-based Fischer–Tropsch diesel (FTD) technologies as a means to accelerate reductions in greenhouse gas emissions (GHG) stemming from road-based transport. We start by performing an economic analysis of FTD produced from Norwegian forest biomass at a pioneer commercial plant in Norway, followed with a cost growth analysis to estimate production costs after uncertainty in early plant performance and capital cost estimates are considered. Results after the cost growth analysis imply that the initial production cost estimates for a pioneer producer may be underestimated by up to 30%. Using the revised estimate we then assess, through scenarios, how various financial support mechanisms designed to encourage near-term investment would affect production costs over a range of uncertain future oil prices. For all policy scenarios considered, we evaluate trade-offs between the levels of public expenditure, or subsidy, and private investor profitability. When considering the net present value of the subsidy required to incentivize commercial investment during a future of low oil prices, we find that GHG mitigation via wood-FTD is likely to be considered cost-ineffective. However, should the government expect that mean oil prices in the coming two decades will hover between $97 and 127/bbl, all the incentive policies considered would likely spur investment at net present values ≤$-100/tonne-fossil-CO 2-equivalent avoided.