E-mode Operation Research Articles

Impact of Channel Thickness and Doping Concentration for Normally-Off Operation in Sn-Doped β-Ga2O3 Phototransistors.

We demonstrate a Sn-doped monoclinic gallium oxide (β-Ga2O3)-based deep ultraviolet (DUV) phototransistor with high area coverage and manufacturing efficiency. The threshold voltage (VT) switches between negative and positive depending on the β-Ga2O3 channel thickness and doping concentration. Channel depletion and Ga diffusion during manufacturing significantly influence device characteristics, as validated through computer-aided design (TCAD) simulations, which agree with the experimental results. We achieved enhancement-mode (e-mode) operation in <10 nm-thick channels, enabling a zero VG to achieve a low dark current (1.84 pA) in a fully depleted equilibrium. Quantum confinement in thin β-Ga2O3 layers enhances UV detection (down to 210 nm) by widening the band gap. Compared with bulk materials, dimensionally constrained optical absorption reduces electron-phonon interactions and phonon scattering, leading to faster optical responses. Decreasing β-Ga2O3 channel thickness reduces VT and VG, enhancing power efficiency, dark current, and the photo-to-dark current ratio under dark and illuminated conditions. These results can guide the fabrication of tailored Ga2O3-based DUV phototransistors.

E-Mode AlGaN/GaN HEMTs Using p-NiO Gates

Sputtered p-NiO films were used to suppress gate leakage and produce a positive shift in gate voltage of AlGaN/GaN high electron mobility transistors for e-mode operation. A direct comparison with Schottky gate devices fabricated on the same wafer shows the utility of the NiO in increasing the on-off ratio and shifting the threshold voltage from -0.95 V (Schottky gated) to +0.9 V (NiO gated). The breakdown voltage was 780 V for a 40 µm drain-source separation. The sub-threshold swing decreased from 181 mV/dec for Schottky gate HEMTs to 128 mV/dec on NiO-gated devices. The simple fabrication process without any annealing or passivation steps shows the promise of NiO-gates for e-mode AlGaN/GaN HEMT operation. Figure 1

Investigating the effect of O2 plasma treatment on the operational characteristics of Schottky-gate AlGaN/GaN HEMT

This study investigates the effect of O2 plasma treatment on the physical and electrical properties of the surface region in Schottky-gate AlGaN/GaN high electron mobility transistor (HEMT). We demonstrate that O2 plasma treatment significantly reduces the gate leakage current and enhances the on/off ratio by three orders of magnitude compared to devices without treatment. The O2 plasma treatment removes organic chemical residue and forms Ga–O bonds on the AlGaN surface beneath the gate metal. X-ray photoelectron spectroscopy results indicate that the treatment effectively forms a Ga–O compound oxide layer, which provides surface passivation. Furthermore, atomic force microscope analysis reveals a 50% reduction in surface roughness after the O2 plasma treatment. Using O2 plasma oxidation treatment caused a shift in the threshold voltage (VTH ) of Schottky-gate AlGaN/GaN HEMT. Initially measured at −5.26 V, the VTH value shifted to +0.5 V. Furthermore, we also employ TCAD simulation to assist in the process developed during the manufacturing process. It is worth noting that the drain current decreases as the Ga–O compound oxide layer increases. This is due to effectively depleted the polarization charges at the AlGaN/GaN interfaces during E-mode operation when reducing the thickness of the AlGaN layer beneath the gate metal. Our results demonstrate the importance of O2 plasma surface treatment in achieving optimal device performance. This study systematically discusses the effect of O2 plasma on AlGaN/GaN surface properties and the formation of Ga–O bonding. It offers insights into developing high-performance Schottky-gate AlGaN/GaN HEMT.

DC and RF performance analysis of enhancement mode fin-shaped tri-gate AlGaN/GaN HEMT and MOSHEMT with ultra-thin barrier layer

The DC and RF assessment of critical barrier-AlGaN/GaN nano channel tri-gate fin-shaped High Electron Mobility Transistor (FinHEMT) is investigated for Enhancement-mode (E-mode) operation. We propose and analyze critical barrier layer (CBL) and critical-strained barrier layer (CSBL) FinHEMT for a fixed fin-shaped channel width (W fin = 160 nm) and height (H fin = 70 nm). The CBL FinHEMT ensures an E-mode operation by depleting two-dimensional electron gas (2DEG) near the channel region between AlGaN and GaN hetero-junction. The extracted threshold voltage (V T ) in CBL FinHEMT is 0.4 V as compared to −0.2 V obtained in CSBL FinHEMT. However, increased gate leakage current density and poor gate voltage swing in CBL FinHEMT is improved through a metal-oxide-semiconductor FinHEMT (FinMOSHEMT) structure by the incorporation of Al2O3 gate oxide layer between the tri-gate and CBL AlGaN layer. It results in a stable positive VT of 0.5 V due to the negatively charged Al2O3/barrier interface fixed charge density ( NAl2O3 ). The proposed CBL FinMOSHEMT has also been studied for different atomic layer deposition Al2O3 process-dependent variations in NAl2O3. The maximum on-state drain current and transconductance of 1.01 A mm−1 and 430 mS/mm have been extracted respectively with NAl2O3 of −9.2 × 1012 cm−2. Further, the RF analysis of the proposed CBL FinMOSHEMT structure with the same dimension exhibits improved f T and f max responses with 27 GHz and 90 GHz respectively over CBL FinHEMT. The results of the frequency responses obtained for the proposed design make it suitable for power electronics applications.

Charge trapping layer enabled high-performance E-mode GaN HEMTs and monolithic integration GaN inverters

In this work, high threshold voltage and breakdown voltage E-mode GaN HEMTs using an Al:HfOx-based charge trapping layer (CTL) are presented. The developed GaN HEMTs exhibit a wide threshold modulation range of ΔVTH ∼ 17.8 V, which enables the achievement of enhancement-mode (E-mode) operation after initialization process owing to the high charge storage capacity of the Al:HfOx layer. The E-mode GaN HEMTs exhibit a high positive VTH of 8.4 V, a high IDS,max of 466 mA/mm, a low RON of 10.49 Ω mm, and a high on/off ratio of ∼109. Moreover, the off-state breakdown voltage reaches up to 1100 V, which is primarily attributed to in situ O3 pretreatment effectively suppressing and blocking leakage current. Furthermore, thanks to the VTH of GaN HEMTs being tunable by initialization voltage using the proposed CTL scheme, we prove that the direct-coupled FET logic-integrated GaN inverters can operate under a variety of conditions (β = 10–40 and VDD = 3–15 V) with commendable output swing and noise margins. These results present a promising approach toward realizing the monolithic integration of GaN devices for power IC applications.

E-Mode AlGaN/GaN HEMTs Using p-NiO Gates

Sputtered p-NiO films were used to suppress gate leakage and produce a positive shift in gate voltage of AlGaN/GaN high electron mobility transistors for e-mode operation. A direct comparison with Schottky gate devices fabricated on the same wafer shows the utility of the NiO in increasing the on-off ratio and shifting the threshold voltage from -0.95 V (Schottky gated) to +0.9 V (NiO gated). The breakdown voltage was 780 V for a 40 µm drain-source separation. The sub-threshold swing decreased from 181 mV/dec for Schottky gate HEMTs to 128 mV/dec on NiO-gated devices. The simple fabrication process without any annealing or passivation steps shows the promise of NiO-gates for e-mode AlGaN/GaN HEMT operation.

Numerical study of T-Gate AlGaN/AlInGaN/GaN MOSHEMT with Single and Double Barrier for THz Frequency Applications

This paper presents a comprehensive investigation into the DC analog and AC microwave performance of a state-of-the-art T-gate double barrier AlGaN/AlInGaN/GaN MOSHEMT (Metal Oxide Semiconductor High Electron Mobility Transistor) implemented on a 4H-SiC substrate. The study involves meticulous numerical simulations and an extensive comparison with a single barrier design, utilizing the TCAD-Silvaco software. The observed disparity in performance can be attributed to the utilization of double barrier technology, which enhances electron confinement and current density by augmenting the polarization-induced charge during high-frequency operations. Remarkably, when compared to the single barrier design, the double barrier MOSHEMT exhibits a notable 15% increase in drain current, a 5% increase in transconductance, and an elevated breakdown voltage (VBR) of 140 V in E-mode operation. Furthermore, the radio frequency analysis of the double barrier device showcases exceptional performance, setting new records with a maximum oscillation frequency (fmax) of 1.148 THz and a gain cutoff frequency (ft) of 891 GHz. These impressive results obtained through deck-simulation affirm the immense potential of the proposed double barrier AlGaN/AlInGaN/GaN MOSHEMT for future applications in high-power and terahertz frequency domains.

E-mode AlGaN/GaN HEMTs using p-NiO gates

Sputtered p-NiO films were used to suppress gate leakage and produce a positive shift in the gate voltage of AlGaN/GaN high-electron mobility transistors for e-mode operation. A direct comparison with Schottky-gated devices fabricated on the same wafer shows the utility of the NiO in increasing the on-off ratio and shifting the threshold voltage from −0.95 V (Schottky gated) to +0.9 V (NiO gated). The breakdown voltage was 780 V for a 40 μm drain-source separation. The subthreshold swing decreased from 181 mV/dec for Schottky-gated HEMTs to 128 mV/dec on NiO-gated devices. The simple fabrication process without any annealing or passivation steps shows the promise of NiO gates for e-mode AlGaN/GaN HEMT operation.

Study of enhancement-mode GaN pFET with H plasma treated gate recess

This letter showcases the successful fabrication of an enhancement-mode (E-mode) buried p-channel GaN field-effect-transistor on a standard p-GaN/AlGaN/GaN-on-Si power HEMT substrate. The transistor exhibits a threshold voltage (V TH) of −3.8 V, a maximum ON-state current (I ON) of 1.12 mA/mm, and an impressive I ON/I OFF ratio of 107. To achieve these remarkable results, an H plasma treatment was strategically applied to the gated p-GaN region, where a relatively thick GaN layer (i.e., 70 nm) was kept intact without aggressive gate recess. Through this treatment, the top portion of the GaN layer was converted to be hole-free, leaving only the bottom portion p-type and spatially separated from the etched GaN surface and gate-oxide/GaN interface. This approach allows for E-mode operation while retaining high-quality p-channel characteristics.

High threshold voltage enhancement-mode GaN p-FET with Si-rich LPCVD SiN x gate insulator for high hole mobility

In this work, the GaN p-MISFET with LPCVD-SiN x is studied as a gate dielectric to improve device performance. By changing the Si/N stoichiometry of SiN x , it is found that the channel hole mobility can be effectively enhanced with Si-rich SiN x gate dielectric, which leads to a respectably improved drive current of GaN p-FET. The record high channel mobility of 19.4 cm2/(V∙s) was achieved in the device featuring an Enhancement-mode channel. Benefiting from the significantly improved channel mobility, the fabricated E-mode GaN p-MISFET is capable of delivering a decent-high current of 1.6 mA/mm, while simultaneously featuring a negative threshold-voltage (V TH) of –2.3 V (defining at a stringent criteria of 10 μA/mm). The device also exhibits a well pinch-off at 0 V with low leakage current of 1 nA/mm. This suggests that a decent E-mode operation of the fabricated p-FET is obtained. In addition, the V TH shows excellent stability, while the threshold-voltage hysteresis ΔV TH is as small as 0.1 V for a gate voltage swing up to –10 V, which is among the best results reported in the literature. The results indicate that optimizing the Si/N stoichiometry of LPCVD-SiN x is a promising approach to improve the device performance of GaN p-MISFET.

Dynamic Performance Analysis of Logic Gates Based on p-GaN/AlGaN/GaN HEMTs at High Temperature

The high-temperature operation of the AlGaN/GaN high electron mobility transistors (HEMTs) and direct-coupled FET logic (DCFL) inverters, NOR gates, and NAND gates are demonstrated. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> -GaN-gate HEMTs which are used as drivers in DCFL circuits exhibit proper E-mode operation with a relatively stable threshold voltage <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> (drift -0.31 V) and high electron mobility μ of 587 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V∙S at 300 °C. The fabricated logic gates have a small switching time at room temperature (RT). As the temperature increases to 300 °C, these logic gates exhibit a slight increase in switching time, wherein the fall time and rise time of the inverter from room temperature to 300 °C increases from 16 ns to 129 ns and 128 ns to 0.864 μs, respectively. The logic gates herein exhibit accurate and stable operation at 300 °C. Furthermore, the reason for the switching time increase at high temperature is revealed from the perspective of devices.

Monolithic β -Ga2O3 NMOS IC based on heteroepitaxial E-mode MOSFETs

In this Letter, we report on a monolithically integrated β-Ga2O3 NMOS inverter integrated circuit (IC) based on heteroepitaxial enhancement mode (E-mode) β-Ga2O3 metal-oxide-semiconductor field-effect transistors on low-cost sapphire substrates. A gate recess technique was employed to deplete the channel for E-mode operation. The E-mode devices showed an on-off ratio of ∼105 with a threshold voltage of 3 V. In comparison, control devices without the gate recess exhibited a depletion mode (D-mode) with a threshold voltage of −3.8 V. Furthermore, depletion-load NMOS inverter ICs were fabricated by monolithically integrating D- and E-mode transistors on the same substrate. These NMOS ICs demonstrated inverter logic operation with a voltage gain of 2.5 at VDD = 9 V, comparable with recent GaN and other wide-bandgap semiconductor-based inverters. This work lays the foundation for heteroepitaxial low-cost and scalable β-Ga2O3 ICs for monolithic integration with (ultra)wide bandgap Ga2O3 power devices.

Recess-Free E-Mode AlGaN/GaN MIS-HFET with Crystalline PEALD AlN Passivation Process

We utilized a plasma-enhanced atomic layer deposition (PEALD) process to deposit an AlN passivation layer on AlGaN/GaN surface to enhance the polarization effects, which enabled the fabrication of an enhancement-mode (E-mode) AlGaN/GaN metal-insulator-semiconductor heterojunction field-effect transistor (MIS-HFET) without the need for a gate recess process. The AlN film deposited by PEALD exhibited a crystalline structure, not an amorphous one. The enhanced polarization effect of introducing the PEALD AlN film on a thin AlGaN barrier was confirmed through electrical analysis. To fabricate the E-mode AlGaN/GaN MIS-HFET, the PEALD AlN film was deposited on a 4.5 nm AlGaN barrier layer and then a damage-free wet etching process was used to open the gate region. The MIS-gate structure was formed by depositing a 15 nm plasma-enhanced chemical vapor deposition (PECVD) silicon dioxide (SiO2) film. The fabricated thin-AlGaN/GaN MIS-HFET demonstrated successful E-mode operation, with a threshold voltage of 0.45 V, an on/off ratio of approximately 109, a specific on-resistance of 7.1 mΩ·cm2, and an off-state breakdown voltage exceeding 1100 V.

An intensive study on effects of lateral scaling and gate metals on the RF/DC performance of recessed T-gated Fe-doped AlN/GaN/SiC HEMTs for future RF and microwave power applications

In this simulation work, the effect of AlxGa1-xN and InxGa1-xN back barriers (BB) on the RF & DC performances of recessed T-gated Fe-doped AlN/GaN/SiC HEMT device is investigated. The novel HEMT achieved a peak GM of 435.9 mS/mm, the highest ID of 1.89 A/mm, and a maximum fT of 197.4 GHz with Al0.18Ga0.82N BB which can be attributed to enhanced mobility and carrier confinement in the quantum well (QW) due to the integration of BB, presence of Fe-doping in the GaN buffer in conjunction with recessed T-gate approach. On the other hand, the device with In0.20Ga0.80N BB recorded a peak GM of 434.9 mS/mm, a peak ID of 1.83 A/mm, and a maximum fT of 196.4 GHz. The flatness GM is attributable to the applied high drain bias of 5 V. The device performance deteriorated with an increase of Al and In mole fractions of the BB layers following an increased dislocation density which influenced the epitaxial quality of the heterostructures. This paper also investigates the impact of gate metals on the electrical performance of the Al0.18Ga0.82N and In0.20Ga0.80N BB devices. In both cases, the TCAD results revealed that the HEMT with lower ϕm (work function) gate metal i.e., Al-gate exhibited superior DC/RF performance. Owing to an uplift of the conduction band edge the performance degraded following the raise of the Schottky barrier that leads to the collection of the least number of carriers at the AlN/GaN interface hence resulting in poor sheet carrier density. Besides, the gate metal Pt with the highest work function of 5.65 eV is suitable to pursue E-Mode operation. In addition, the simulation to explore the impact of scaling source-drain spacing (LSD) revealed that limiting gate-to-drain distance (LGD) and gate-to-source distance (LGS) is the key to achieve enhance RF/DC performance. It is no surprise that this device is at the forefront of the future 5G/6G, military, defense, and RF power applications.

Depletion- and Enhancement-Mode p-Channel MISHFET Based on GaN/AlGaN Single Heterostructures on Sapphire Substrates

We report on p-channel metal-insulator-semiconductor heterostructure field-effect transistors (MISHFET) based on p-GaN/uid-GaN/Al0.29Ga0.71N single heterostructures on sapphire substrates, grown by metalorganic vapor phase epitaxy (MOVPE). The impact of p-GaN layer removal and channel layer thickness adjustment by dry-etching on the characteristics of the MISHFET are investigated. Depending on the remaining GaN thickness (tGaN), the fabricated MISHFET show either depletion-mode (d-mode) operation with a threshold voltage Vth of 3.8 V and an on-current |ID,on| of 9.5 mA/mm (tGaN = 21 nm) or enhancement-mode (e-mode) operation with Vth of -2.3 V and |ID,on| of 1.5 mA/mm (tGaN = 12 nm). Independent of the etching depth, all devices exhibit a very low off-state drain current |ID,off| 10-8 mA/mm and a steep subthreshold swing (SS) between 80 and 89 mV/dec. Similar to n-channel devices, a Vth instability caused by charge trapping at the dielectric/semiconductor interface is found, emphasizing that careful interface engineering is required for good device performance.

Improved Breakdown Voltage and Low Damage E-Mode Operation of AlON/AlN/GaN HEMTs Using Plasma Oxidation Treatment

Low-damage plasma oxidation treatment for AlN/GaN high-electron-mobility transistors (HEMTs) was developed in this letter, with which high-performance enhancement-mode (E-mode) AlON/AlN/GaN HEMTs were demonstrated. After removal of in situ SiN cap layer within gate area, remote plasma oxidation (RPO) treatment of 4.9nm AlN barrier layer at 300 °C leads to formation of AlON insulator layer and effective depletion of 2-D electron gas channel, without etch-induced damage or serious interfacial issues compared with the commonly used gate- recess metal-insulator-semiconductor HEMTs. Thanks to the low-damage RPO treatment, the achieved E-mode HEMTs with threshold voltage of 0.4 V exhibit quite a small loss of output current (7.8%) compared with the depletion-mode devices. In addition, the AlON gate insulator layer results in a remarkable increase in breakdown voltage of devices from 20 V to 74 V, which benefits the high-voltage operation of AlN/GaN technology. Further investigation shows that the oxidation process of AlN barrier tends to be saturated with treatment time increasing, providing a promising solution to the high-performance E-mode operation of scaled GaN-based HEMTs in RF applications.

Modeling Electrostatics and Low-Field Electron Mobility of GaN FinFETs

Gallium nitride (GaN) high electron mobility transistors (HEMTs) are currently being used for RF applications due to the intrinsically high saturation velocity and high mobility of GaN compared to both Silicon and SiC. However, GaN HEMTs suffer from a variety of issues, such as a lack of E-Mode operation and non-linearity, which impacts their widespread adoption in the RF and low-voltage switching devices. Recent advances in material processing, high aspect ratio epitaxial growth, and etching methods has led to an increased interest in 3-D GaN nanostructures such as AlGaN/GaN MIS FinFET wherein a layer of Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> surrounds the AlGaN/GaN fin. Theoretical calculations of transport properties of AlGaN/GaN FinFETs are scarce compared to those of their planar HEMT counterparts. This work employs for the first time self-consistent solution of the coupled 1-D Boltzmann – 2-D Schrödinger – 3-D Poisson problem to yield the channel electrostatics and the transport characteristics of AlGaN/GaN MIS FinFETs. The low field electron mobility in the quasi-1-D region is calculated, using 1-D ensemble Monte Carlo method, as a function of temperature and fin width. Acoustic, piezoelectric and polar optical phonon scattering, and interface roughness scattering at the AlGaN/GaN interface, are incorporated in the theoretical model. Our simulations suggest that E-mode FinFETs can be achieved in ultranarrow fin channels. As suggested experimentally, we confirm via simulation experiments that strain relaxation increases the sheet resistance of the channel.

Proposal and Simulation of Ga2O3MOSFET With PN Heterojunction Structure for High-Performance E-Mode Operation

Proposal and Simulation of Ga₂O₃MOSFET With PN Heterojunction Structure for High-Performance E-Mode Operation

GaN high electron mobility transistors (HEMTs) with self-upward-polarized AlScN gate dielectrics toward enhancement-mode operation

A threshold voltage (V th) shifting method for GaN high electron mobility transistors using self-upward polarized Al1-x Sc x N gate dielectrics was proposed. The direction of the spontaneous polarization was controlled by the insertion of an Al2O3 layer between the Al1-x Sc x N and the AlGaN layers. A V th shift of 8 V was found by changing the direction of the polarization. The thickness scaling in the Al1-x Sc x N layer from 40 to 30 nm showed a linear relationship to the V th, revealing to retain a high spontaneous polarization. A high positive V th for enhancement-mode (E-mode) operation is feasible with the method in combination with a recess process.

Hf-Based and Zr-Based Charge Trapping Layer Engineering for E-Mode GaN MIS-HEMT Using Ferroelectric Charge Trap Gate Stack

E-mode hybrid ferroelectric charge storage gate (FEG) GaN HEMTs have shown promising performances for future power GaN device applications. The FEG-HEMT demonstrates a combination of ferroelectric polarization and charge trapping process in the ferro-charge-storage gate stack, leading to a positive threshold voltage shift for E-mode operations. In this work, FEG-HEMTs with various Hf-based and Zr-based charge trapping layers are systematically studied. FEG-HEMT which employed nitrogen incorporated HfO2 (HfON) as the charge trapping layer shows an E-mode operation with the highest Vth (+2.3 V) after initialization. Moreover, the gate leakage of the HfON sample was further reduced due to the nitrogen incorporation, leading to a more complete charging process during initialization. The Vth instability is also addressed and investigated. The FEG-HEMT with HfON as the charge trapping layer showed a negligible Vth hysteresis (-43mV) and the highest Vth stability in both the PBTI (positive bias threshold voltage instability) and NBTI (negative bias threshold voltage instability) test measurements.