E-mode GaN Research Articles

Design optimization of wide-gate swing E-mode GaN HEMTs with junction barrier Schottky gate

To increase the gate swing, a GaN-based high-electron-mobility transistor with a junction barrier Schottky gate (JBS-HEMT) was proposed. Compared to conventional p-GaN Schottky gate HEMTs (Conv-HEMT), the high electric field at the surface is transferred to the pn junction inside the body, and the extended depletion region of the pn junction shields the surface Schottky contact interface for the JBS-HEMT. After fitting the model to the reported device, the proposed JBS-HEMT was simulated and optimized using the Sentaurus TCAD tool. The simulation results of the optimized JBS-HEMT demonstrate a high gate breakdown voltage (17.6 V), which is 158.5% higher than the gate breakdown voltage of the Conv-HEMT (11.1 V) and a lower gate leakage current of six orders of magnitude than the Conv-HEMT at the gate-to-source voltage of 10 V. The proposed JBS-HEMT exhibits a positive threshold voltage (1.68 V) and excellent threshold voltage stability, and the maximum threshold voltage drift of the JBS-HEMT (+0.237 V) is smaller than that of the Conv-HEMT (−0.714 V) under gate stress conditions. The peak transconductance of the JBS-HEMT (186 mS mm−1) at athe drain-to-source voltage of 10 V showed almost no reduction compared to the Conv-HEMT (189 mS mm−1), which solves the problem of decreased transconductance capability of the reported GaN HEMT with a p-n junction gate (PNJ-HEMT). It was confirmed that the JBS-HEMT has excellent gate stability and potential for power electronics applications.

GaN-based E-mode p-FETs with polarization-doped p-type graded AlGaN channels

Herein, a novel enhancement-mode (E-mode) GaN-based p-channel FETs (p-FETs) with a linearly graded AlGaN (LGA) p-channel is proposed and numerically studied by Silvaco TCAD. Thanks to strong polarization-induced doping, three-dimensional hole gas (3DHG) can be uniformly generated in LGA to form a continuous p-channel with a hole concentration over 1018 cm–3. Combined with an optimized recessed gate structure, the LGA p-FET can simultaneously achieve a large threshold voltage (|V TH|) > 2 V and a high current density (|J DS|) of ∼10 mA mm−1 at V DS = −10 V. Additionally, two critical parameters of the LGA p-FETs, i.e. the depth of recessed gate and initial Al composition of LGA, are specifically studied to reveal the unique carrier behavior of 3DHG in the devices. Importantly, the LGA structure is further optimized and implemented as the p-type cap layer to construct an E-mode GaN n-FET. Thereby, based on the same LGA configuration, a GaN-based inverter with the matched complementary n- and p-FETs is monolithically constructed, showing sharp voltage transition. The reported novel LGA structure and its availability in both GaN-based E-mode n- and p-FETs provides valuable insights and guidance to construct highly efficient GaN p-type devices and All-GaN-based integrated circuits for compact power electronic systems.

Charge trapping layer enabled high-performance E-mode GaN HEMTs and monolithic integration GaN inverters

In this work, high threshold voltage and breakdown voltage E-mode GaN HEMTs using an Al:HfOx-based charge trapping layer (CTL) are presented. The developed GaN HEMTs exhibit a wide threshold modulation range of ΔVTH ∼ 17.8 V, which enables the achievement of enhancement-mode (E-mode) operation after initialization process owing to the high charge storage capacity of the Al:HfOx layer. The E-mode GaN HEMTs exhibit a high positive VTH of 8.4 V, a high IDS,max of 466 mA/mm, a low RON of 10.49 Ω mm, and a high on/off ratio of ∼109. Moreover, the off-state breakdown voltage reaches up to 1100 V, which is primarily attributed to in situ O3 pretreatment effectively suppressing and blocking leakage current. Furthermore, thanks to the VTH of GaN HEMTs being tunable by initialization voltage using the proposed CTL scheme, we prove that the direct-coupled FET logic-integrated GaN inverters can operate under a variety of conditions (β = 10–40 and VDD = 3–15 V) with commendable output swing and noise margins. These results present a promising approach toward realizing the monolithic integration of GaN devices for power IC applications.

The Effect of Fluorine Doping in the Charge Trapping Layer on Device Characteristics and Reliability of E-Mode GaN MIS-HEMTs

The Effect of Fluorine Doping in the Charge Trapping Layer on Device Characteristics and Reliability of E-Mode GaN MIS-HEMTs

Novel Temperature Calibration Method of E-Mode and D-Mode GaN Power Modules Considering Dynamic ON-Resistance

This paper presents a method for measuring temperature using the temperature sensitive parameter (TSP) of a GaN power module. Current collapse occurs in GaN high electron mobility transistors (HEMTs). This results in dynamic on-resistance because of trapped electrons. Thus, dynamic conditions should be considered to accurately measure thermal characteristics. GaN HEMTs are operated in the enhanced mode (E-mode) and depletion mode (D-mode). In this study, E-mode and D-mode GaN power modules are designed to compare their thermal characteristics. Among three common temperature-measurement methods, this work employs the TSP-based approach in consideration of the device operation, instead of those using thermo-sensitive optical or material properties. The calibration is conducted in steady-state and dynamic-state. The ambient temperature is estimated using steady-state calibration data. Power cycling is examined for considering dynamic conditions. It is confirmed that dynamic on-resistance changes according to the cycle period, on time, and number of cycles. Experiments are conducted using different values of these parameters. Finally, an equation for temperature is obtained from the experimental results. The equation precisely estimates temperature with an error of 0.7%.

Highly Reliable Short-Circuit Protection Circuits for Gallium Nitride High-Electron-Mobility Transistors

This paper presents a circuit for detecting and protecting against short circuits in E-mode gallium nitride high-electron-mobility transistors (GaN HEMTs) and analyzes the protection performance of the circuit. GaN HEMTs possess fast switching characteristics that enable high efficiency and power density in power conversion devices. However, these characteristics also pose challenges in protecting against short circuits and overcurrent situations. The proposed method detects short-circuit events by monitoring an instantaneous drop in the DC bus voltage of a circuit with GaN HEMTs applied and uses a bandpass filter to prevent the malfunction of the short-circuit protection circuit during normal switching and ensure highly reliable operation. Using this method, the short-circuit detection time of E-mode GaN HEMTs can be reduced to 257 ns, successfully protecting the device without malfunctions even in severe short-circuit situations occurring at high DC link voltages.

In-situ S/TEM DC biasing of p-GaN/AlGaN/GaN heterostructure for E-mode GaN HEMT devices

This work describes an in-situ electrical DC bias study of the E-mode GaN high electron mobility transistor (HEMT) device. A single transistor structure is biased and studied in real-time. The sample was made from an E-mode GaN HEMT device using Focused Ion Beam (FIB) milling and upright lift-off. The device lamella is subjected to forward gate bias to understand the device operation and physical changes under the bias. Active device area and micron level changes due to biasing were studied and identified as crucial factors affecting device reliability during continuous operation. Electric bias-induced physical changes are observed at the p-GaN layer and AlGaN interface on the p-GaN and GaN sides. Localized damage and defect formation, along with elemental diffusion, is observed. The formation of new defects over existing growth defects was seen in the p-GaN/AlGaN/GaN heterostructure. The study helped us identify the exact location of the failure, the region affected under bias, and the occurrence of physical changes due to the electrical bias on the in-situ device. Based on the study, gate breakdown failure and its location at the metal/p-GaN interface are understood to result from physical changes activated by electrical bias.

Monolithically Integrated Logic Circuits Based on p-NiO Gated E-Mode GaN HEMTs

Monolithically Integrated Logic Circuits Based on p-NiO Gated E-Mode GaN HEMTs

Thermal Modeling and Degradation Profiling of E-Mode GaN HEMTs for Aging Characterization

Thermal Modeling and Degradation Profiling of E-Mode GaN HEMTs for Aging Characterization

Degradation and Failure Mechanism of p-GaN Gate E-Mode GaN HEMTs

GaN-based power transistors are becoming pivotal devices for high power and high voltage operation due to their higher breakdown voltage, higher carrier mobility because of two-dimensional electron gas (2-DEG), better thermal resistance, higher frequency switching, and lower on-state resistance (RON) [1]. P-GaN gate E-mode GaN HEMTs have emerged as a center of extensive research to understand their operation and reliability [2]. However, one of the reasons the E-mode GaN HEMTs are not yet successfully utilized to their maximum potential is the lack of complete understanding of gate breakdown. Gate degradation of p-GaN gate E-mode GaN HEMT is less understood because of the complexities involving the operating conditions and variables such as gate length, the acceptor doping concentration in the p-GaN layer [3], p-GaN gate thickness, and design of the device [4-5]. To outline a consistent degradation mechanism, this work aims to present an electro-physical model of gate breakdown in p-GaN gate E-mode HEMTs.Lateral E-mode GaN HEMT devices with p-GaN gate configuration are used for this study. According to the Scanning Transmission Electron Microscopy (STEM) imaging of a new device, the AlGaN barrier is 10 nm thick, and the p-GaN cap is 65 nm. The gate-source and gate-drain lengths are 0.5 micrometer and 2.5 micrometer, respectively. The gate length defined by the p-GaN layer is 0.5 micrometer and the edges of the gate metal are pulled in from the top edge of the p-GaN layer by 40 nm. A 0.7 micrometer-long, source-connected field plate is over the p-GaN gate. The p-GaN gate is subjected to static stress to induce accelerated breakdown. Devices were stressed with HP 4155 Semiconductor Analyzer. The electrical measurements were performed with the source, drain, and substrate connected to the ground. FEI 200 Nova was used for Scanning Electron Microscopy (SEM) imaging and Focused Ion-Beam (FIB) milling. ARM JEM-200F with a Cs corrector was used for STEM.Our results show that time-to-fail is highly dependent on device operating conditions. We found no correlation between time-to-fail and initial gate current (IG0). Instead, a higher impact of temperature was found on the gate current of the device (IG) and time-to-fail at 100 °C. Gate failure at constant voltage stress was a single-stage failure. Under constant current stress, on the other hand, the gate shows a multi-stage failure. The breakdown mechanism depends on the impact of static stress on the gate degradation, starting with increased gate current leading to Schottky barrier leakage and finally to catastrophic contact failure. Our study shows that the metal/p-GaN interface at the gate finger becomes the weakest part of the gate stack, likely to be the initiation point of degradation. Metal/p-GaN interface and surface defects develop as percolation paths acting as leakage sources, and nano-cracks have been observed in the gate cap. FA also shows physical degradation at the metal/p-GaN cap due to electrical stress. Observed physical damage in the gate region is correlated to the gate leakage characteristics to develop an electro-physical failure model for gate breakdown in p-GaN gate E-mode GaN HEMTs.

Modelling and mitigating oscillation in E-mode GaN HEMT: A simulation-based approach to parasitic inductance optimization

The escalating demands in energy conversion necessitate the evolution of efficient power electronic devices beyond the limitations of traditional silicon (Si) counterparts. This research delves into the intricacies of the Enhancement mode Gallium Nitride High Electron Mobility Transistor (E-mode GaN HEMT). A focus is placed on its static characterization, parameter analysis, and the influence of external parasitic inductances, particularly regarding oscillation challenges during its hard switching process. Forward and revise bias are conducted through comparison with Si-MOSFET and Cascade-GaN HEMT, along with its static on-resistance and transfer characteristics. Through rigorous half-bridge double pulse circuit LTSPICE simulations, this study deciphers the turn-on and turn-off dynamics of the E-mode GaN HEMT. By scrutinizing various parasitic inductances, the research elucidates mechanisms instigating high-frequency voltage and current oscillations. Significantly, the research presents a hierarchy of parasitic inductance influences, employing an energy loss comparison. This analysis underscores the prominent impact of the common source parasitic inductance, which exhibits energy loss increases of 23.6 % and 22.7 % at junction temperatures of 25 °C and 75 °C, respectively. Building on these insights, the study recommends strategies to mitigate the effects of external parasitic inductance, underscoring the pivotal role of oscillation suppression in advanced GaN Printed Circuit Board (PCB) and Integrated Circuit (IC) designs. This comprehensive inquiry provides a blueprint for enhancing GaN circuit designs, paving the way for their optimal application in the evolving realm of power electronics.

In-Circuit Assessment of the Long-Term Reliability of E-Mode GaN HEMTs

In-Circuit Assessment of the Long-Term Reliability of E-Mode GaN HEMTs

Characterization and Reliability Analysis of Enhancement-Mode PEALD AlN/LPCVD SiNx GaN MISFET with In Situ H2/N2 Plasma Pretreatment

An effective in situ H2/N2 pretreatment technique for enhancement-mode GaN MISFET with a PEALD AlN/LPCVD SiNx Dual Gate Dielectric is presented. This technique features in situ H2 (15%)/N2 (85%) plasma pretreatment prior to AlN deposition. By using in situ H2 (15%)/N2 (85%) plasma pretreatment and a PEALD AlN protection layer, combined with an LPCVD SiNx gate dielectric, the quality of the AlN/GaN interface can be further improved due to the reduced interface trap densities between the AlN/GaN interface. The interface protection technique enables the successful integration of a high-quality PEALD AlN/LPCVD SiNx gate dielectric in an E-mode GaN MISFET with high performance, high stability, and high reliability. The fabricated enhancement-mode GaN MISFET exhibits a high gate swing and high channel effective mobility of 187.5 cm2/Vs, a threshold voltage of 2.9 V defined at 1 µA/mm, an on/off current ratio of 108, and a breakdown voltage of 1760 V defined at ID = 10 μm/mm. Our experiments showed a significant reduction in dynamic ON resistance and the suppression of current collapse when using the enhancement-mode GaN MISFET with PEALD AlN/LPCVD SiNx under high drain bias switching conditions, especially when the VDS is greater than the 60 V drain bias switch operating state.

High-performance enhancement-mode GaN-based p-FETs fabricated with O3-Al2O3/HfO2-stacked gate dielectric

In this letter, an enhancement-mode (E-mode) GaN p-channel field-effect transistor (p-FET) with a high current density of −4.9 mA/mm based on a O3-Al2O3/HfO2 (5/15 nm) stacked gate dielectric was demonstrated on a p++-GaN/p-GaN/AlN/AlGaN/AlN/GaN/Si heterostructure. Attributed to the p++-GaN capping layer, a good linear ohmic I−V characteristic featuring a low-contact resistivity (ρ c) of 1.34 × 10−4 Ω·cm2 was obtained. High gate leakage associated with the HfO2 high-k gate dielectric was effectively blocked by the 5-nm O3-Al2O3 insertion layer grown by atomic layer deposition, contributing to a high I ON/I OFF ratio of 6 × 106 and a remarkably reduced subthreshold swing (SS) in the fabricated p-FETs. The proposed structure is compelling for energy-efficient GaN complementary logic (CL) circuits.

Investigation of time-dependent gate dielectric breakdown in recessed E-mode GaN MIS-HEMTs using ferroelectric charge trap gate stack (FEG-HEMT)

The aim of achieving E-mode operations has led to the proposal of novel hybrid ferroelectric charge trap gate stack schemes. These schemes involve utilizing a combination of the charge trapping layer (CTL) and the ferroelectric laminated layer to positively shift the threshold voltage to a normally-off margin after initializing the gate pulse, thus achieving the Enhancement-mode (E-mode) characteristic. This study focuses on the forward gate bias time-dependent dielectric breakdown (TDDB) gate reliability in the E-Mode GaN MIS-HEMTs using ferroelectric charge trap gate stack (FEG-HEMT) with and without recess and investigates the impact of temperature on TDDB. The gate voltages required for operation with a 1 % failure rate over a 10-year period are 12.95 V and 10.22 V at 25 °C and 150 °C for both samples, respectively. Also, the examination of the stability of the recessed process by calculating the activation energies (0.7 eV) of both samples are demonstrated. The article also investigates the relationship between long-term reliability and short-term initialization by examining the transition point of the time-dependent failure curve.

Degradation and Failure Mechanism of p-GaN Gate E-Mode GaN HEMTs

This work describes the cause-effect-based degradation process of the p-GaN gate in Enhancement-mode (E-mode) GaN High Electron Mobility Transistors (HEMTs) using gate stressing and failure analysis (FA). We found no correlation between time-to-fail and initial gate current (IG0). Instead, a higher impact of temperature was found on the gate current of the device (IG) and time-to-fail at 100 °C. Gate failure at constant voltage stress was a single-stage failure. Under constant current stress, the gate shows a multi-stage failure. The breakdown starts with increased gate current leading to Schottky barrier leakage and finally to catastrophic contact failure. The metal/p-GaN interface at the gate finger becomes the weakest part of the gate stack. Metal/p-GaN interface and surface defects develop as percolation paths acting as leakage sources, and nano-cracks have been observed in the gate cap. FA also shows physical degradation at the metal/p-GaN cap due to electrical stress.

Total Ionizing Dose Effects on the Threshold Voltage of GaN Cascode Devices.

GaN devices are nowadays attracting global attention due to their outstanding performance in high voltage, high frequency, and anti-radiation ability. Research on total ionizing dose and annealing effects on E-mode GaN Cascode devices has been carried out. The Cascode device consists of a low-voltage MOSFET and a high-voltage depletion-mode GaN MISHEMT. Cascode devices of both conventional processed MOSFET and radiation-hardened MOSFET devices are fabricated to observe the TID effects. Experiment results indicate that, for the Cascode device with conventional processed MOSFET, the VTH shifts to negative values at 100 krad(Si). For the Cascode device with radiation-hardened MOSFET, the VTH shifts by -0.5 V at 100 krad(Si), while shifts to negative values are 500 krad(Si). The annealing process, after the TID experiment, shows that it can release trapped charges and help VTH recover. On one hand, the VTH shift and recover trends are similar to those of a single MOSFET device, suggesting that the MOSFET is the vulnerable part in the Cascode which determines the anti-TID ability of the device. On the other hand, the VTH shift amount of the Cascode device is much larger than that of a previously reported p-GaN HEMT device, indicating that GaN material shows a better anti-TID ability than Si.

High threshold voltage enhancement-mode GaN p-FET with Si-rich LPCVD SiN x gate insulator for high hole mobility

In this work, the GaN p-MISFET with LPCVD-SiN x is studied as a gate dielectric to improve device performance. By changing the Si/N stoichiometry of SiN x , it is found that the channel hole mobility can be effectively enhanced with Si-rich SiN x gate dielectric, which leads to a respectably improved drive current of GaN p-FET. The record high channel mobility of 19.4 cm2/(V∙s) was achieved in the device featuring an Enhancement-mode channel. Benefiting from the significantly improved channel mobility, the fabricated E-mode GaN p-MISFET is capable of delivering a decent-high current of 1.6 mA/mm, while simultaneously featuring a negative threshold-voltage (V TH) of –2.3 V (defining at a stringent criteria of 10 μA/mm). The device also exhibits a well pinch-off at 0 V with low leakage current of 1 nA/mm. This suggests that a decent E-mode operation of the fabricated p-FET is obtained. In addition, the V TH shows excellent stability, while the threshold-voltage hysteresis ΔV TH is as small as 0.1 V for a gate voltage swing up to –10 V, which is among the best results reported in the literature. The results indicate that optimizing the Si/N stoichiometry of LPCVD-SiN x is a promising approach to improve the device performance of GaN p-MISFET.

Enhancement-Mode GaN Transistor Technology for Harsh Environment Operation

This letter reports an enhancement-mode (E-mode) GaN transistor technology which has been demonstrated to operate in a simulated Venus environment (460 °C, ~ 92 atm., containing CO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> etc.) for 10 days. The robustness of the W/p-GaN-gate AlGaN/GaN high electron mobility transistor (HEMT) was evaluated by two complementary approaches, (1) <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in-situ</i> electrical characterization, which revealed proper transistor operation (including E-mode <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_TH</i> with < 0.09 V variation) in extreme environments; and (2) advanced microscopy investigation of the device after test, which highlighted the effect of the stress conditions on the epitaxial and device structures. To the best of the authors’ knowledge, this is the first demonstration and comprehensive analysis of E-mode GaN transistors in such harsh environments, therefore establishing the proposed GaN technology as a strong contender for harsh environment mixed-signal electronics.

Novel E-mode GaN high-electron-mobility field-effect transistor with a superlattice barrier doped with Mg by thermal diffusion

A novel E-mode GaN high-electron-mobility field-effect transistor with a superlattice barrier doped with Mg by thermal diffusion. This strategy can provide new ideas for the commercialisation of E-mode devices.