Dynamic Voltage Frequency Scaling Research Articles

Energy Efficient Heuristics to Schedule Task Graphs on Heterogeneous Voltage-Frequency Islands

For energy and cost-efficient computing, many desktops and embedded computing devices these days use voltage frequency islands (VFIs) based processors. An island in VFIs consists of multiple homogeneous cores; however, multiple islands are generally heterogeneous in nature. In contrary to architectures (non-VFI) with per-core dynamic voltage frequency scaling (DVFS), in VFI, all the cores in an island run on the same voltage/frequency at the same time. The energy-aware scheduling of task graphs on VFI architectures is challenging and different from non-VFI architectures in which task-based DVFS is possible. However, in VFI scheduling, the time slot for which an island runs on a particular voltage will be decided. In this paper, we analyse 20 different scheduling heuristics for VFI architectures by varying the size of this time slot based on the workload properties and also by varying the voltage/frequency of the time slots. We also propose a heuristic OptSlotVFI to utilize all the slots optimally. The results show that the VFI scheduling heuristics are able to generate schedules which improve energy consumption up to 25% with an equivalent or shorter schedule length than the state-of-the-art approaches.

A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs

Sound techniques for mapping soft real-time applications to resources are indispensable for meeting the application deadlines and minimizing objectives such as energy consumption, particularly on heterogeneous MPSoC architectures. For applications with input-dependent workload variations, static mappings are not able to sufficiently cope with the run-time variation, which can lead to deadline misses or unnecessary energy consumption. As a remedy, hybrid application mapping (HAM) techniques combine a design-time optimization with run-time management that adapts the mappings dynamically to the changes of the arriving input. This paper focuses on scenario-based HAM techniques. Here, the application input space is systematically clustered such that data inside the same scenario exhibit similar characteristics concerning workload when being processed under the same operating points. This static clustering of the input space into data scenarios has proven to be a good abstraction layer for simplifying the design and employment of high-quality run-time managers. However, existing state-of-the-art scenario-based HAM approaches neglect or underutilize the synergistic interplay between mapping selection and the usage of dynamic voltage/frequency scaling (DVFS) when adapting to workload variation. By combining mapping and DVFS selection, variations in the input can be either compensated by a complete re-mapping of the application, evoking a potential high reconfiguration overhead or by just changing the DVFS settings of the resources, offering a low-overhead adaptation alternative and thus significantly reducing the necessary overhead compared to DVFS-agnostic HAM. Furthermore, DVFS enables a fine-grained adaptation of a mapped application to the input data variation, e.g., by slowing down tasks with no impact on the end-to-end latency for the current input using low-frequency DVFS settings. It is shown that this combined approach can save even more energy than a pure mapping adaptation scheme, especially in the presence of data scenarios. In particular, scenario-based design operates as a catalyst for eliciting the synergies between a combined DVFS and mapping optimization and the peculiarities inside a data scenario, i.e., exploiting the commonalities inside a data scenario by perfectly tailored DVFS settings and task mapping. In this scope, this paper proposes two supplementary scenario-based DVFS-aware HAM approaches that consistently outperform existing state-of-the-art mapping approaches in terms of the number of deadline misses and energy consumption as we demonstrate in an empirical study on the basis of four different applications and three different architectures. It is also shown that these benefits still apply to target architectures with increasing mapping migration overheads, thwarting frequent mapping reconfigurations.

An efficient reducing mechanism for energy consumption in data center using hybrid consolidation techniques

The rise in internet user demand is a major factor in the expansion of infrastructure and the upsurge in energy use in cloud, colocation, and some business data centres. The advent of 5G has compounded the situation, as it substantially gives room for many new types of digital services, resulting in a need for richer consume a lot of energy when no scaling method is applied. Services such as mail, data storage and retrieval and other cloud services also require a lot of high energy consumption which eventually result into carbon(IV) oxide (CO2) emissions to the environment. This research therefore, focuses on lowering the energy usage of a data centre with heterogeneous power awareness either in an idle server state or high-performance state using a novel hybridized algorithm called “DyVoFesLoReMu”, comprising Dynamic Voltage Frequency Scaling (Dvfs) and a modified Local Regression Minimum Utilization (LrMu). A real dataset (workload) obtained online from PlanetLab consisting of hosts and Virtual Machines (VM) was simulated on a data center in CloudSim 3.0.3. Tool kit with preset parameters consisting of VM Allocation Policy and VM Selection Policy was used. The tool kit was utilised to create cloud infrastructure and simulate the essential features of a cloud environment. The Cloudsim was installed on Eclipse Integrated Development Environment (IDE) 2019 version on Windows 10 operating system. The hybridized algorithm was compared with other five (5) existing energy reducing algorithms and it was found to be more efficient with a range of 41-90% reduction in energy usage from the ten days workload traces and in comparison with the existing algorithms used for the simulation.

AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing

As the timing guardband consumes more and more design margin with the technology scaling, better-than-worst-case (BTWC) techniques have gained more attention as a promising solution. BTWC techniques can relax the design margin by transcending the pessimistic static timing constraints and utilizing the dynamic timing information. However, to guarantee the design reliability throughout the lifetime, the conventional dynamic timing analysis (DTA) engines need an extra reliability guardband, which is commonly evaluated under the worst-case corners of aging and variation. This type of guardbanding consumes the precious design margin, thus hindering the efficiency improvement from BTWC techniques. Therefore, in this paper, we propose AVATAR, an aging-and variation-aware dynamic timing analyzer that can perform DTA with the impact of transistor aging and random process variation, including the gate-level aging analysis and random variation model that can accurately calculate cell delay under the impact of transistor aging and random variation, and an event-based DTA algorithm that avoids the pessimistic property of graph-based analysis. We also propose an ML-assisted DTA acceleration flow for the multicycle DTA of homogeneous multicore designs. We present two case studies using AVATAR to show its effectiveness. First, we present an application-based dynamic-voltage-frequency-scaling (DVFS) design methodology based on AVATAR, which can exploit application-level dynamic timing slack (DTS) to improve energy efficiency and performance. The results demonstrate that, compared to the design based on the conventional corner-based DTA, the additional performance improvement of the design based on AVATAR can be up to 14% or the additional power-saving can be up to 20%. Second, we demonstrate using the proposed ML-assisted acceleration flow for reliability-aware deep neural network (DNN) accelerator simulation. We use the proposed flow to estimate the impact of timing errors due to aging and random variation on the inference accuracy of two benchmark DNNs. The results demonstrate that the proposed acceleration flow achieves up to 10W speedup with an average error of less than 2%.

On Stochastic Optimization for Smartphone CPU Energy Consumption Decrease

Extending smartphone working time is an ongoing endeavour becoming more and more important with each passing year. It could be achieved by more advanced hardware or by introducing energy-aware practices to software, and the latter is a more accessible approach. As the CPU is one of the most power-hungry smartphone devices, Dynamic Voltage Frequency Scaling (DVFS) is a technique to adjust CPU frequency to the current computational needs, and different algorithms were already developed, both energy-aware and energy-agnostic kinds. Following our previous work on the subject, we propose a novel DVFS approach to use simultaneous perturbation stochastic approximation (SPSA) with two noisy observations for tracking the optimal frequency and implementing several algorithms based on it. Moreover, we also address an issue of hardware lag between a signal for the CPU to change frequency and its actual update. As Android OS could use a default task scheduler or an energy-aware one, which is capable of taking advantage of heterogeneous mobile CPU architectures such as ARM big.LITTLE, we also explore an integration scheme between the proposed algorithms and OS schedulers. A model-based testing methodology to compare the developed algorithms against existing ones is presented, and a test suite reflecting real-world use case scenarios is outlined. Our experiments show that the SPSA-based algorithm works well with EAS with a simplified integration scheme, showing CPU performance comparable to other energy-aware DVFS algorithms and a decreased energy consumption.

An automated and portable method for selecting an optimal GPU frequency

Power consumption poses a significant challenge in current and emerging graphics processing unit (GPU) enabled high-performance computing systems. In modern GPUs, dynamic voltage frequency scaling (DVFS) appears to be a reliable control to regulate power consumption and performance. However, the DVFS design space is large - hence, brute-force approaches are infeasible to select the optimal frequency. Furthermore, no single frequency can be universally optimal for applications with varying computational intensities. Thus, the application’s complexity and the availability of a wide range of frequency settings are a challenge in selecting the optimal frequency configuration for a given GPU workload. To that end, this paper proposes a systematic approach that consists of three steps. The feature characterization study identifies the fine-grain GPU utilization metrics that influence the power consumption and execution time of a given workload. To understand the performance, power, and energy consumption behaviors of a workload across GPU’s DVFS design space, we derived analytical power and performance models using the identified fine-grain features. It is shown that the same set of GPU utilization metrics can estimate both the power consumption and execution time while being agnostic of changes to frequency and input sizes. Applying a power control with the single objective of reducing power may cause performance degradation, leading to more energy consumption. A multi-objective approach is proposed to select the optimal GPU DVFS configuration for a workload that reduces power consumption with negligible degradation in performance. The evaluation was conducted using SPEC ACCEL benchmarks and three real applications - NAMD LAMMPS, and LSTM on NVIDIA GV100, GA100, and AMD MI210 GPUs. On average, real applications showed 29.6% energy savings with a performance loss of 5.2% on GA100 and 22.6% energy savings with a performance loss of 4.7% on GV100. Moreover, the proposed models are portable to real applications, GPU architectures, and vendors, and require metric collection at only the default frequency rather than all supported DVFS configurations. Additionally, we conducted a comparison between our models and the GPU assembly instructions (PTX)-based static models. The results revealed a significant reduction in the average error rates, with a decrease from 19.7% to 3.1% for power models and from 29.4% to 5.2% for performance models.

Co-Optimizing CPU Voltage, Memory Placement, and Task Offloading for Energy-Efficient Mobile Systems

Energy-saving is one of the most important missions in the design of battery-based mobile systems. Many ideas have been suggested for saving energy in different system layers. Specifically, (1) lowering the supply voltage for idle CPU time slots, (2) using hybrid memory to save DRAM refresh power, and (3) task offloading to edge/cloud servers are well-acknowledged techniques used in CPU, memory, and network subsystems. In this paper, we show that co-optimizing these three techniques is necessary for further reducing the energy consumption of mobile real-time systems. To this end, we present an extended task model and formulate the effect of dynamic voltage/frequency scaling (DVFS), hybrid memory allocation, and task offloading problems as a unified measure. We then present a new real-time task scheduling scheme, called Co-TOMS, to co-optimize the energy-saving techniques in CPU, memory, and network subsystems by considering the given task set and resource conditions. The main contributions of our study can be summarized as follows. First, we optimize three energy-saving techniques across different system layers and find that they have significant influence on each other. For example, the effect of DVFS alone is limited in mobile systems, but combining it with offloading greatly amplifies its efficiency. Second, previous studies on offloading usually define a deadline as the maximum allowable latency at the application-level, but we focus on hard real-time systems that must meet task-level deadlines. Third, we design a steady-state genetic algorithm that allows fast convergence with reasonable computation overhead under various resource and workload conditions.

SAFLA: Scheduling Multiple Real-Time Periodic Task Graphs on Heterogeneous Systems

Many modern Cyber Physical Systems (CPSs) are composed of multiple independent periodically executing real-time control tasks having inter-dependent component sub-tasks. Each such control task is therefore usually represented as <i>Directed-acyclic Task Graphs</i> (DTGs). These CPSs are often distributed in nature and are quickly shifting from homogeneous to heterogeneous processing platforms in order to meet ever increasing demands for performance and energy savings, within limited resource budgets. In spite of the practical relevance of the problem in today's CPS design scenario, very few research works in literature have tried to address this due to its inherent computational as well as design complexity. This work endeavors to solve the problem of co-scheduling a set of periodic real-time applications each modelled as an independent DTG, to be executed on a distributed platform consisting of heterogeneous processors communicating using shared buses. Assuming the processing platform to be DVFS (Dynamic Voltage Frequency Scaling) enabled, we attempt to minimize dynamic energy dissipation associated with the execution of all DTGs over an hyperperiod <inline-formula><tex-math notation="LaTeX">$\mathcal {H}$</tex-math></inline-formula> while ensuring that no DTG instance within <inline-formula><tex-math notation="LaTeX">$\mathcal {H}$</tex-math></inline-formula> misses its deadline. The problem has first been formally represented as a constraint optimization problem. However, an optimal solution using standard solvers become prohibitively compute as well as memory intensive and doesn't scale even for moderate problem sizes. Hence, in this work, we attempt to develop a three-phase list-based hierarchical scheduling algorithm called <i>Slack Aware Frequency Level Allocator</i> ( <i>SAFLA</i> ). The efficacy of <i>SAFLA</i> has been critically evaluated through simulation using benchmark DTGs.

Distributionally robust chance-constrained planning for regional integrated electricity–heat systems with data centers considering wind power uncertainty

This paper proposed an optimal planning method for regional integrated electricity–heat systems with data centers (DC-RIEHS) considering wind power uncertainty to reduce economic costs and improve system flexibility. First, a novel data center model is developed, where various flexible operating characteristics of the data center are modeled in detail, including thermal inertia of indoor air, rescheduling of delay-tolerant workloads, dynamic voltage frequency scaling technique of servers and heat recovery. The heat recovery system is specially built based on the electric cooling system of the studied data center and heat pump, which connects electric power systems and district heating systems. On this basis, a three-stage distributionally robust chance-constrained (DRCC) planning model of DC-RIEHS is proposed. It is converted into a tractable single-stage mixed-integer conic model by applying affine decision rules to hedge against wind power uncertainty. The proposed planning method determines the optimal capacities of energy equipment and the scheduling decisions of representative days considering wind power uncertainty. Simulation results demonstrate that the flexible resources in a data center can significantly reduce system costs and actively participate in coping with wind power uncertainty. Compared with the chance-constrained optimization method under Gaussian distribution, the proposed DRCC method exhibits better out-of-sample performance in terms of violation probability and system operation results under the wind uncertainty with spatial–temporal correlation.

Using dynamic voltage frequency scaling and service‐level agreement to reduce energy consumption in cloud datacenters based on distance

AbstractEnergy consumption in cloud is an important topic. Previous works have reduced energy consumption, but have not consider and optimal selection of servers in a datacenter. In our paper, we try to elicit optimal selection of servers in a datacenter. We will modify the architecture of the system and the proposed algorithm using service‐level agreement (SLA) for datacenter servers in this selection, we consider the distance between the servers and the job and if there is a violation of SLA, the migration of virtual machines (VMs) occurs. On the other hand, unnecessary migration of VMs increases energy consumption. So we provide an algorithm for migrating VMs, and because we need task scheduling to perform tasks in the cloud, we will also provide algorithms for tasks migrating. Energy consumption is important for us, we use dynamic voltage frequency scaling to reduce energy consumption. On the other hand, the selection of service providers is done in the SLA management, and these service providers are located on different datacenters, we consider the parameter of the distance to the service consumer in selecting the appropriate datacenter.

Modeling and Analysis of Thermal Covert Channel Attacks in Many-core Systems

In a many-core chip, thermal flux and thermal correlation among the cores can be explored to create a thermal covert channel (TCC). In this paper, we provide an analytical model to quickly determine the key TCC performance metrics, in terms of bit error rate (BER), signal to noise ratio (SNR), and channel capacity, without going through lengthy computer simulation and/or physical experiments that are normally needed in current TCC performance studies. According to our model, the TCC’s BER is proportional to the square root of the transmission frequency, which can be explored quantitatively to boost the TCC’s transmission efficiency by letting the TCC’s thermal signal be transmitted at a higher frequency. In addition, our proposed model also links the jamming noise and application of Dynamic Voltage Frequency Scaling (DVFS) to TCC’s BER performance, a feature that can be explored to design/optimize the countermeasures against the TCC attacks. The TCC performance predicted by the proposed theoretical model is found in a good agreement with that obtained from computer simulations, with an average error lower than 7%.

Reducing energy consumption using heterogeneous voltage frequency scaling of data-parallel applications for multicore systems

This paper investigates the exploitation of heterogeneous DVFS (dynamic voltage frequency scaling) control for improving the energy efficiency of data-parallel applications on ccNUMA shared-memory systems. We propose to adjust the clock frequency individually for the appropriately selected groups of cores, taking into account the diversified costs of parallel computation. This paper aims to evaluate the proposed approach using two different data-parallel applications: solving the 3D diffusion problem, and MPDATA fluid dynamics application. As a result, we observe the energy-savings gains of up to 20 percentage points over the traditional homogeneous frequency scaling approach on the server with two 18-core Intel Xeon Gold 6240. Additionally, we confirm the effectiveness of our strategy using two 64-core AMD EPYC 7773X. This paper also introduces two pruning algorithms that help select the optimal heterogeneous DVFS setups taking into account the energy or performance profile of studied applications. Finally, the cost and efficiency of developed algorithms are verified and compared experimentally against the brute-force search.

CARAT – A reliability analysis framework for BTI-HCD aging in circuits

Circuit Aging Reliability Analysis Tool (CARAT), a framework that calculates random activity (frequency and duty) aware degradation of FETs to simulate circuit aging under real operating workloads is proposed. Bias Temperature Instability (BTI) and Hot Carrier Degradation (HCD) induced degradation of FETs is calculated in a cycle-by-cycle manner based on actual terminal waveforms grabbed from SPICE. Framework capability is demonstrated by using Level Shifter (LS) under random data-path activity, and Ring Oscillator (RO) under Dynamic Voltage Frequency Scaling (DVFS) conditions. The risk associated with the standard blanket approach is discussed.

An Ageing-Aware and Temperature Mapping Algorithm for Multilevel Cache Nodes

Increase in chip inactivity in the future threatens the performance of many-core systems and therefore, efficient techniques are required for continuous scaling of transistors. As of a result of this challenge, future proposed many-core system designs must consider the possibility of a 50% functioning chip per time as well maintaining performance. Fortunately, this 50% inactivity can be increased by managing the temperature of active nodes and the placement of the dark nodes to leverage a balance working chip whilst considering the lifetime of nodes. However, allocating dark nodes inefficiently can increase the temperature of the chip and increase the waiting time of applications. Consequently, due to stochastic application characteristics, a dynamic rescheduling technique is more desirable compared to fixed design mapping. In this paper, we propose an Ageing Before Temperature Electromigration-Aware, Negative Bias Temperature Instability (NBTI) & Time-dependent Dielectric Breakdown (TDDB) Neighbour Allocation (ABENA 2.0), a dynamic rescheduling management system which considers the ageing and temperature before mapping applications. ABENA also considers the location of active and dark nodes and migrate task based on the characteristics of the nodes. Our proposed algorithm employ Dynamic Voltage Frequency Scaling (DVFS) to reduce the Voltage and Frequency (VF) of the nodes. Results show that, our proposed methods improve the ageing of nodes compared to a conventional round-robin management system by 10% in temperature, and 10% ageing.

Fault tolerance aware workload resource management technique for real‐time workload in heterogeneous computing environment

AbstractWorkload execution is composed by mapping larger tasks onto heterogeneous environments such as cloud platforms for enhancing the efficiency of workload resource management techniques. Execution of scientific workflow on a cloud platform is time‐consuming, expensive, and requires a fault‐tolerance guarantee. The existing methodology has emphasized on minimizing processing time to reduce costs. However, the processing cost can be reduced by minimizing energy consumption. In providing fault‐tolerance while meeting the workload quality of service requirement the task is offloaded to a new physical machine; Hence, this increases energy consumption and thereby increases the cost of workload execution. In addressing the research challenges this paper presents the fault‐tolerant aware (FTA) workload resource management (WRM) technique. First, the FTA‐WRM optimizes processing and communication costs as an energy constraint leveraging the dynamic voltage frequency scaling technique. Then, a task offloading mechanism is modeled as an energy constraint with an application delay requirement for providing fault tolerance into the FTA‐WRM. The experiment outcome shows the FTA‐WRM significantly improves processing and energy efficiency in comparison with the existing workload resource management technique.

Multitimescale Mitigation for Performance Variability Improvement in Time-Critical Systems

Ensuring a timing guarantee is crucial for time-critical applications. However, this task becomes more challenging with the increasing performance variability generated by complicated modern hardware and software. A widespread solution to the problem is real-time scheduling, which depends on worst-case execution time (WCET) and dynamic voltage frequency scaling (DVFS). Although these techniques provide the necessary guarantees, they also exhibit important limitations from the long switching time of DVFS and the overly pessimistic execution time model of WCET. In this work, a multitimescale mitigation methodology is proposed to improve the way of tackling performance variability in both timing guarantee and energy saving. By using both the DVFS and heterogeneous datapath (HDP) knobs, this methodology can push the timescale of mitigation down to the submillisecond level. Moreover, this methodology can calculate a tight upper bound of execution time at run-time using dynamic scenarios (DSs). Simulation shows that the proposed methodology can ensure zero deadline misses with a smaller safety time margin than the method using only DVFS and WCET. This advantage can translate into an energy reduction by half compared to the conventional WCET-based method with a single DVFS knob.

Quality Optimization of Adaptive Applications via Deep Reinforcement Learning in Energy Harvesting Edge Devices

Applications with adaptability are widely available on the edge devices with energy harvesting capabilities. For their runtime quality optimization, however, current approaches cannot tackle the variations of quality modeling and harvested energy simultaneously. Therefore, in this article, we are the first to propose a deep reinforcement learning (DRL)-based dynamic voltage frequency scaling (DVFS) method that optimizes the application execution quality of energy harvesting edge devices to mitigate the variations. First, we propose a baseline DRL formulation that novelly migrates the objective of quality maximization into a reward function and constructs a DRL quality agent. Second, we devise a long short-term memory (LSTM)-based selector that performs DRL quality agent selection based on the energy harvesting history. Third, we further propose two optimization methods to alleviate the nonnegligible overhead of DRL computations: 1) an improved thinking-while-moving concurrent DRL scheme to compromise the “state drifting” issue during the DRL decision process and 2) a variable interstate duration decision scheme that compromises the DVFS overhead incurred in each action taken. The experiments take an adaptive stereo matching application as a case study. The results show that the proposed DRL-based DVFS method on average achieves 17.9% runtime reduction and 22.05% quality improvement compared to state-of-the-art solutions.

Coordinated Batching and DVFS for DNN Inference on GPU Accelerators

Employing hardware accelerators to improve the performance and energy-efficiency of DNN applications is on the rise. One challenge of using hardware accelerators, including the GPU-based ones, is that their performance is limited by internal and external factors, such as power caps. A common approach to meet the power cap constraint is using the Dynamic Voltage Frequency Scaling (DVFS) technique. However, the functionally of this technique is limited and platform-dependent. To tackle this challenge, we propose a new control knob, which is the size of input batches fed to the GPU accelerator in DNN inference applications. We first evaluate the impact of batch size on power consumption and performance of DNN inference. Then, we introduce the design and implementation of a fast and lightweight runtime system, called BatchDVFS. Dynamic batching is implemented in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BatchDVFS</i> to adaptively change the batch size, and hence, trade-off throughput with power consumption. It employs an approach based on binary search to find the proper batch size within a short period of time. Combining dynamic batching with the DVFS technique, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BatchDVFS</i> can control the power consumption in wider ranges, and hence, yield higher throughput in the presence of power caps. To find near-optimal solution for long-running jobs that can afford a relatively significant profiling overhead, compared with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BatchDVFS</i> overhead, we also design an approach, called BOBD, that employs Bayesian Optimization to wisely explore the vast state space resulted by combination of the batch size and DVFS solutions. Conducting several experiments using a modern GPU and several DNN models and input datasets, we show that our <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BatchDVFS</i> can significantly surpass the techniques solely based on DVFS or batching, regarding throughput (up to 11.2x and 2.2x, respectively), while successfully meeting the power cap.

Improving Energy Efficiency in Cloud Computing Data centres Using Intelligent Mobile Agents

Cloud computing has become a profound name and also a solid bedrock for new emerging technology. Cloud technology fully supports the dynamic provisioning of computing resources as a utility service on a pay-as-you-go approach. Its numerous benefits (such as rapid elasticity, flexibility, network resource pooling) empower small, medium, and large enterprises to use other technologies through the Internet's flexibility. Despite the benefits cloud technology offers, the challenge of the high power consumption rate it incurs as it leverages its promised attributes remains a major concern. Academic research has shown that a typical 500 square meter data centre consumes about 27,048 kilowatts per hour of power per day regardless of whether it is active or not. Over the years, the most dominant energy efficient techniques for managing data centre has been Dynamic voltage frequency scaling and virtual machine consolidation, which has had a significant setback due to its inability to manage systems on overload state. Therefore, a novel paradigm based on an intelligent mobile agent approach has been proposed. This proposed approach is highly intelligent can easily detect underutilised and overloaded components of the data centre due to its unique feature. Agent technique has successfully shown it can prevent and manage overloading issues due to change in workloads and achieve a more efficient load balancing with a low power consumption rate. The mobile agent was embedded into servers and switches to regulate their activities and then shut down underutilised components. Mobile agent (Java agent) is the first of its kind used in a cloud environment. This research proposal saves a significant amount of energy and improves the entire system performance. In this thesis, the intelligent-based Agent approach is used to address energy efficiency and costaware related problems. Agent approach helps facilitate resource management, allocation of cloud data centre components with a significant reduction in energy usage rate with a more efficient system performance while maintaining a highly reliable system as promised by service providers.

Radiation Tolerant Multi-Bit Flip-Flop System With Embedded Timing Pre-Error Sensing

This article presents the design, implementation methodology, and validation of a multi-bit flip-flop (FF) system that provides tolerance against single-event upsets (SEUs) and single-event transients (SETs) caused by radiation strikes. The proposed solution also has embedded timing pre-error sensing capability, which enables closed-loop integration of digital systems to work at optimal operating point (OPP) without any fail. It allows efficient real-time dynamic voltage frequency scaling (DVFS) implementation in the digital system. It helps detect aging-related and total ionizing dose (TID)-induced timing degradation in digital circuits. It can be implemented with any standard digital cell library (non-rad-hard), thereby providing a cost-effective solution for rad-hard applications. The design is implemented in ST BCD 90-nm technology in multiple configurations of bit sizes. A digital system based on ARM cortex M4 microprocessor has also been implemented with the proposed FF and put on silicon for testing to validate various capabilities of the proposed design. The results are presented based on simulations, electrical characterization, and radiation tests.