Dynamic Voltage And Frequency Scaling Control Research Articles

A Sub-nW 93% Peak Efficiency Buck Converter With Wide Dynamic Range, Fast DVFS, and Asynchronous Load-Transient Control

This article presents a highly efficient buck converter with sub-nW quiescent power and wide dynamic range for ultra-low-power (ULP) Internet-of-Things (IoT) systems-on-chip (SoCs). To optimize the SoC power consumption and performance, this buck converter supports fast dynamic voltage and frequency scaling (DVFS) and fast load-transient response (FLTR) using an asynchronous control scheme. To achieve robust and high-efficiency power delivery over process, voltage, and temperature variations, an adaptive deadtime controller (ADTC) is proposed with minimized area and power overhead. The power stage and gate drivers are optimized by a length split technique and a strong-up weak-down (SuWd) scheme to achieve low quiescent power. In addition, the buck converter is fully self-contained with a bias generator (BG), clock, and power-on-reset (PoR) integrated on-chip. Fabricated in 65-nm CMOS, measurement results show that the buck converter achieves 802-pW quiescent power and 93% peak efficiency at 1.5-V input voltage. The measured dynamic range is from 0.5 to 2.75 mW, which is over six orders of magnitude. The measured voltage droop is 56 mV for a 45-nA-to-1-mA load current step and DVFS up- and down-tracking takes 10.57 and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$19.81~\mu \text{s}$ </tex-math></inline-formula> for an 88- and 92-mV reference step, respectively. This sub-nW buck converter integrates fast DVFS and FLTR features with a wide dynamic range making it suitable for ULP IoT applications.

Multidevice Collaborative Power Management Through Decentralized Knowledge Sharing

Minimizing energy consumption while satisfying the user-specified performance requirement is a primary design objective for mobile devices. To achieve this, off-the-shelf mobile devices are usually equipped with dynamic voltage and frequency scaling (DVFS)-enabled processors to tradeoff performance for energy reduction through online adjustment of operating points. Recently, reinforcement learning algorithms have been widely studied and show great potential for runtime DVFS control because of their adaptability to the changing environment. However, the rapid evolution of hardware and the ever-growing diversity of mobile applications increase the system complexity dramatically and make it hard for the learning agent to quickly obtain an efficient power management policy. To address this challenge, we propose a decentralized collaborative Q-learning (DCQL)-based approach in this article to solve the DVFS control problem of multicore mobile processors. By exchanging learning experiences and knowledge among multiple devices, DCQL increases the convergence rate of the learning algorithm and improves the quality of the derived power management policy. On each device, the 4-phase action selection strategy is applied for efficient exploration of the action space defined by various power settings. Experimental results on realistic applications show that DCQL can achieve 3.4%–8.0% energy reduction over various existing approaches while providing an average of $3.4\times $ speedup over the state-of-the-art individual learning algorithm. We also show that the proposed approach can scale well with the number of cores through clustered DVFS control.

Power-performance assessment of different DVFS control policies in NoCs

We analyze the power-delay trade-off in a Network-on-Chip (NoC) under three Dynamic Voltage and Frequency Scaling (DVFS) policies. The first rate-based policy sets frequency and voltage of the NoC to the minimum value that allows to sustain the injection rate without reaching saturation. The second queue-based policy uses a feedback-loop approach to throttle the NoC frequency and voltage such that the average backlog of the injection queues tracks a target value. The third delay-based policy uses a closed-loop strategy that targets a given NoC end-to-end average delay. We first show that, despite the different mechanism and implementation, both rate-based and queue-based policies obtain very similar results in terms of power and delay, and we propose a theoretical interpretation of this similarity. Then, we show that delay-based policy generally offers a better power-delay trade-off. We obtained our results with an extensive set of experiments on synthetic traffic, as well as multimedia, communications and PARSEC benchmarks. For all the experiments, we report both cycle-accurate simulation results for the analysis of NoC delay and accurate power results obtained targeting a standard-cell library in an advanced 28-nm FDSOI CMOS technology.

Voltage Regulator Efficiency Aware Power Management

Conventional off-chip voltage regulators are typically bulky and slow, and are inefficient at exploiting system and workload variability using Dynamic Voltage and Frequency Scaling (DVFS). On-die integration of voltage regulators has the potential to increase the energy efficiency of computer systems by enabling power control at a fine granularity in both space and time. The energy conversion efficiency of on-chip regulators, however, is typically much lower than off-chip regulators, which results in significant energy losses. Fine-grained power control and high voltage regulator efficiency are difficult to achieve simultaneously, with either emerging on-chip or conventional off-chip regulators. A voltage conversion framework that relies on a hierarchy of off-chip switching regulators and on-chip linear regulators is proposed to enable fine-grained power control with a regulator efficiency greater than 90%. A DVFS control policy that is based on a reinforcement learning (RL) approach is developed to exploit the proposed framework. Per-core RL agents learn and improve their control policies independently, while retaining the ability to coordinate their actions to accomplish system level power management objectives. When evaluated on a mix of 14 parallel and 13 multiprogrammed workloads, the proposed voltage conversion framework achieves 18% greater energy efficiency than a conventional framework that uses on-chip switching regulators. Moreover, when the RL based DVFS control policy is used to control the proposed voltage conversion framework, the system achieves a 21% higher energy efficiency over a baseline oracle policy with coarse-grained power control capability.

Voltage Regulator Efficiency Aware Power Management

Conventional off-chip voltage regulators are typically bulky and slow, and are inefficient at exploiting system and workload variability using Dynamic Voltage and Frequency Scaling (DVFS). On-die integration of voltage regulators has the potential to increase the energy efficiency of computer systems by enabling power control at a fine granularity in both space and time. The energy conversion efficiency of on-chip regulators, however, is typically much lower than off-chip regulators, which results in significant energy losses. Fine-grained power control and high voltage regulator efficiency are difficult to achieve simultaneously, with either emerging on-chip or conventional off-chip regulators. A voltage conversion framework that relies on a hierarchy of off-chip switching regulators and on-chip linear regulators is proposed to enable fine-grained power control with a regulator efficiency greater than 90%. A DVFS control policy that is based on a reinforcement learning (RL) approach is developed to exploit the proposed framework. Per-core RL agents learn and improve their control policies independently, while retaining the ability to coordinate their actions to accomplish system level power management objectives. When evaluated on a mix of 14 parallel and 13 multiprogrammed workloads, the proposed voltage conversion framework achieves 18% greater energy efficiency than a conventional framework that uses on-chip switching regulators. Moreover, when the RL based DVFS control policy is used to control the proposed voltage conversion framework, the system achieves a 21% higher energy efficiency over a baseline oracle policy with coarse-grained power control capability.

User-Centric Power Management for Embedded CPUs Using CPU Bandwidth Control

Dynamic power management for mobile processors has become very important due to the increased clock speed and number of cores. There have been various power management governors using dynamic voltage and frequency scaling (DVFS). Among them, a user-centric power management has received a lot of attention as a method to save power while maintaining the quality of user experience (UX) referring to the perceived quality of system services to end users. Most user-centric governors have employed DVFS as a method to reduce the power consumption. However, DVFS may not be adequate enough to guarantee UX qualities for all task because the CPU clock speed changed by DVFS can affect all tasks running at the same processor. In order to minimize such inter-task interferences by DVFS, it is necessary to employ task-specific power management methods. This paper shows that CPU bandwidth control developed for CPU resource management within Linux kernel can be employed as a task-specific power management method, and a novel CPU power management scheme employing both DVFS and CPU bandwidth control is proposed. Experimental results show that the proposed governor can reduce the power consumption more than the Ondemand governor can achieve while maintaining the quality of UX.

A dynamic, compiler guided DVFS mechanism to achieve energy-efficiency in multi-core processors

Continuing progress and integration levels in silicon technologies make possible complete end-user systems on a single chip. This massive level of integration makes modern multi-core chips widely adoptable in multiple domains. In the design of high-performance massive multi-core chips, power and heat are dominant constraints. The increasing power consumption is of growing concern due to several reasons, e.g., cost, performance, reliability, scalability, and environmental impact. Increased power consumption not only raises chip temperature and cooling cost, but also decreases chip reliability and performance. Dynamic voltage and frequency scaling (DVFS) is a popular methodology to optimize the power usage/heat dissipation of electronic systems without significantly compromising overall system performance. The recent trend towards chip-multiprocessors (CMP) executing multi-threaded workloads with heterogeneous behavior motivates the need for per-core DVFS control mechanisms. In this paper, we propose a set of algorithms that use compile-time information to achieve DVFS control at run-time. By using compile-time information, we propose suitable heuristics, which make our power management mechanism more precise at run-time. We demonstrate that the proposed compiler-based DVFS mechanism performs better than the existing history- or profile-based methods that predict the future program behavior depending on the past statistics.

PowerTracer: Tracing Requests in Multi-Tier Services to Reduce Energy Inefficiency

As energy has become one of the key operating costs in running a data center and power waste commonly exists, it is essential to reduce energy inefficiency inside data centers. In this paper, we develop an innovative framework, called PowerTracer , for diagnosing energy inefficiency and saving power. Inside the framework, we first present a resource tracing method based on request tracing in multi-tier services of black boxes. Then, we propose a generalized methodology of applying a request tracing approach for energy inefficiency diagnosis and power saving in multi-tier service systems. With insights into service performance and resource consumption of individual requests, we develop (1) a bottleneck diagnosis tool that pinpoints the root causes of energy inefficiency, and (2) a power saving method that enables dynamic voltage and frequency scaling (DVFS) with online request tracing. We implement a prototype of PowerTracer, and conduct extensive experiments to validate its effectiveness. Our tool analyzes several state-of-the-practice and state-of-the-art DVFS control policies and uncovers existing energy inefficiencies. Meanwhile, the experimental results demonstrate that PowerTracer outperforms its peers in power saving.

Energy-centric DVFS controlling method for multi-core platforms

Dynamic voltage and frequency scaling (DVFS) is a well-known and effective technique for reducing energy consumption in modern processors. However, accurately predicting the effect of frequency scaling on system performance is a challenging problem in real environments. In this paper, we propose a realistic DVFS performance prediction method, and a practical DVFS control policy (eDVFS) that aims to minimize total energy consumption in multi-core platforms. We also present power consumption estimation models for CPU and DRAM by exploiting a hardware energy monitoring unit. We implemented eDVFS in Linux, and our evaluation results show that eDVFS can save a substantial amount of energy compared with Linux "on-demand" CPU governor in diverse environments.

LAURA-NoC: Local Automatic Rate Adjustment in Network-on-Chips With a Simple DVFS

In this brief, we propose local automatic rate adjustment in network-on-chips (NoC) (LAURA-NoC), a NoC with a distributed approach to dynamic voltage and frequency scaling (DVFS). The utilization of the switch buffers is used in a local feedback loop to automatically determine the appropriate clock frequency and voltage that allow the switch to sustain the rate at its input ports, without a global controller. The DVFS controller is simple and uses 2 voltage and 16 frequency values. We report a significant power saving compared to a global DVFS approach in a 45-nm CMOS technology, 33 % on average over four realistic video applications.

Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip

Runtime power management is a critical technique for reducing the energy footprint of digital electronic devices and enabling sustainable computing, since it allows electronic devices to dynamically adapt their power and energy consumption to meet performance requirements. In this article, we consider the case of MultiProcessor Systems-on-Chip (MPSoC) implemented using multiple Voltage and Frequency Islands (VFIs) relying on fine-grained Dynamic Voltage and Frequency Scaling (DVFS) to reduce the system power dissipation. In particular, we present a framework to theoretically analyze the impact of three important technology-driven constraints; (i) reliability-driven upper limits on the maximum supply voltage; (ii) inductive noise-driven constraints on the maximum rate of change of voltage/frequency; and (iii) the impact of manufacturing process variations on the performance of DVFS control for multiple VFI MPSoCs. The proposed analysis is general, in the sense that it is not bound to a specific DVFS control algorithm, but instead focuses on theoretically bounding the performance that any DVFS controller can possibly achieve. Our experimental results on real and synthetic benchmarks show that in the presence of reliability- and temperature-driven constraints on the maximum frequency and maximum frequency increment, any DVFS control algorithm will lose up to 87% performance in terms of the number of steps required to reach a reference steady state. In addition, increasing process variations can lead to up to 60% of fabricated chips being unable to meet the specified DVFS control specifications, irrespective of the DVFS algorithm used. Nonetheless, we note that although conventional DVFS might become less effective with technology scaling, it will continue to play an important role in the context of emerging power management techniques, for example, for massively parallel multiprocessor systems where only a subset of cores can be turned on at any given point of time due to total power constraints.