Dynamic Voltage And Frequency Scaling Algorithm Research Articles

A Double Deep Q-Learning Model for Energy-Efficient Edge Scheduling

Reducing energy consumption is a vital and challenging problem for the edge computing devices since they are always energy-limited. To tackle this problem, a deep Q-learning model with multiple DVFS (dynamic voltage and frequency scaling) algorithms was proposed for energy-efficient scheduling (DQL-EES). However, DQL-EES is highly unstable when using a single stacked auto-encoder to approximate the Q-function. Additionally, it cannot distinguish the continuous system states well since it depends on a Q-table to generate the target values for training parameters. In this paper, a double deep Q-learning model is proposed for energy-efficient edge scheduling (DDQ-EES). Specially, the proposed double deep Q-learning model includes a generated network for producing the Q-value for each DVFS algorithm and a target network for producing the target Q-values to train the parameters. Furthermore, the rectified linear units (ReLU) function is used as the activation function in the double deep Q-learning model, instead of the Sigmoid function in QDL-EES, to avoid gradient vanishing. Finally, a learning algorithm based on experience replay is developed to train the parameters of the proposed model. The proposed model is compared with DQL-EES on EdgeCloudSim in terms of energy saving and training time. Results indicate that our proposed model can save average $2\%\hbox{-}2.4\%$2%-2.4% energy and achieve a higher training efficiency than QQL-EES, proving its potential for energy-efficient edge scheduling.

Energy-efficient global illumination algorithms for mobile devices using dynamic voltage and frequency scaling

With increases of display resolution and graphical quality demands, global illumination techniques are sought after to meet such demands. However, global illumination algorithms have a long processing time on mobile devices, such as smartphones or tablet PCs. Besides the performance issue, the algorithms consume a large amount of battery-powered energy. The performance and energy consumption have a trade-off relationship. The dynamic voltage and frequency scaling (DVFS) algorithms control the balance between the performance and the energy consumption by adjusting the GPU and CPU’s frequencies. To improve the performance of the global illumination algorithm and reduce the high energy consumption of the current DVFS algorithm, we suggest new algorithms with new metrics for estimating the amount of workload for GPUs as well as their memory workload. Using our new DVFS algorithms, we increase the energy efficiency, the performance per watt, of a global illumination algorithm by 33.59% in comparison to a conventional general-purpose DVFS algorithm, without modifying the underlying algorithm core.

Hybrid DVFS Scheduling for Real-Time Systems Based on Reinforcement Learning

Power consumption is one of the most challenging issues in the design of modern computing systems. In any computational device, processor consumes significant amount of power compared with other components. In order to reduce power consumption, dynamic voltage and frequency scaling (DVFS) has been commonly used in modern processors. In recent years, there has been much research on real-time DVFS techniques. These techniques work with different strategies and perform well under different conditions. However, a single algorithm is not always optimal under different workloads, dynamic slacks, and power settings. Furthermore, the variation in device configuration also affects the suitability of a given DVFS algorithm. Aiming for adaptability, in this paper, we propose a novel reinforcement learning-based approach, which takes a set of existing techniques, specialized to handle different conditions, and switches to the most suitable one in various situations. Experimental results show that the proposed hybrid approach saves more energy than any single policy executing individually.

GPGPU-Perf: efficient, interval-based DVFS algorithm for mobile GPGPU applications

Although general purpose computations on graphics processing unit (GPGPU) technologies are available even on GPUs, their performance has been seriously affected by the underlying dynamic voltage and frequency scaling (DVFS) mechanism of GPU. In order to save the energy, eventually prolonging the battery life, the DVFS adjusts the GPU's frequency according to the past utilization. When the GPU processes graphic tasks only, it is enough to process them within a fixed time (typically 30---60 frames per second), so the DVFS parameters can be conservatively set. However, in GPGPU case, the GPU should process them at much higher rates depending on applications. Although a modification of DVFS parameters may improve the GPGPU performance, the energy efficiency is sacrificed, and the performance of graphic tasks is affected, as these parameters are shared by both graphic and GPGPU tasks. In order to improve the GPGPU performance without influencing the graphic performance, we devise the new GPGPU-Perf algorithm that adjusts the DVFS parameters such as thresholds and an interval. The new algorithm controls the frequency more intelligently for mobile GPGPU applications, and thus the performance over energy increases by 1.44 times with no influences on graphic tasks and any modifications of GPGPU algorithms. To the best of our knowledge, this paper is the first work that proposes a GPU-DVFS algorithm for GPGPU applications.

A Comparative Study of the Effectiveness of CPU Consolidation Versus Dynamic Voltage and Frequency Scaling in a Virtualized Multicore Server

Companies operating large datacenters are focusing on how to reduce the electrical energy costs of operating datacenters. A common way of cost reduction is to perform a dynamic voltage and frequency scaling (DVFS), thereby matching the CPU's performance and power level to incoming workloads. Another power saving technique is CPU consolidation, which uses the minimum number of CPUs necessary to meet the service request demands and turns OFF the remaining unused CPUs. DVFS has been already extensively studied and verified its effectiveness. On the other hand, it is necessary to study more about the effectiveness of CPU consolidation. Key questions that must be answered are how effectively the CPU consolidation improves the energy efficiency and how to maximize the improvement. These questions are addressed in this paper. After understanding modern power management techniques and developing an appropriate power model, this paper provides an extensive set of hardware-based experimental results and makes suggestions about how to maximize energy efficiency improvement through CPU consolidation. In addition, this paper also presents new online CPU consolidation algorithms, which reduce the energy-delay product up to 13% compared with the Linux default DVFS algorithm.

영상 프레임 디코딩 복잡도 예측을 통한 DVFS 전력감소 방식

최근 영상 디코더 시스템에서 소모전력을 절감하기 위한 방안으로 DVFS (Dynamic Voltage and Frequency Scaling) 방식을 적용한 알고리즘 들이 제안되고 있다. 이에 저자들은 논문[1]에서 전력소모를 최소화할 수 있는 스케줄링 알고리즘을 제시하였다. 이 알고리즘은 수학적으로 최적의 결과를 보장하지만, 사전에 화면 당 디코딩 계산양을 알 수 있다는 조건이 만족하여야 한다. 그러나 실제응용에서 이 조건은 만족되기 어려운 경우가 종종 존재한다. 본 논문에서는 이 제약사항을 극복하는 방안으로, 프레임의 데이터크기로 프레임의 디코딩 계산양을 예측하는 기법에 기초한 수정된 알고리즘을 제안한다. 실제 영상에서 추출된 데이터를 이용한 결과, 계산양 예측 알고리즘은 평균적으로 90%이상의 정확도를 보였으며, 따라서 계산양 예측 기법과 임계점에서의 프래임 크기 20% 내외의 완충버퍼 마진을 적용한 수정한 알고리즘은 버퍼 고갈과 넘침이 일어나지 않으며, 최적알고리즘과 비교할 때 거의 동일한 성능 (1~2% 이하의 성능저하)을 보이는 것을 확인하였다. Recently, intensive research has been performed for reducing video decoder energy consumption, especially based on DVFS (Dynamic Voltage and Frequency Scaling) technique. Our previous work [1] has proposed the optimal DVFS algorithm for energy reduction in video decoders. In spite of the mathematical optimality of the algorithm, the precondition of known frame decoding cycle/complexity limits its application to some realistic scenarios. This paper overcomes this limitation by frame data size-based estimation of frame decoding complexity. The proposed decoding complexity estimation method shows over 90% accuracy. And with this estimation method and buffer underflow margin of around 20% of frame size, almost same power consumption reduction performance as the optimal algorithm can be achieved.

Performance Evaluation for Dynamic Voltage and Frequency Scaling Using Runtime Performance Counters

Dynamic voltage and frequency scaling (DVFS) is an effective technique for reducing power consumption. The system performance is not easy to evaluate through Dynamic Voltage and Frequency Scaling. Most of studies use the execution time as an indicator while measuring the performance. However, DVFS adjusted processor speed during a fixed-length period so it cannot rely on the execution time to evaluate the system performance. This study proposes a novel and simple performance evaluation method to evaluate the system performance when DVFS is activated. Based on the performance evaluation method, this study also proposes a DVFS algorithm (P-DVFS) for a general-purpose operating system. The algorithm has been implemented on the Linux operating system and used a PXA270 development board. The results show that P-DVFS could accurately predict the suitable frequency, given runtime statistics information of a running program. In this way, the user can easily control the energy consumption by specifying allowable performance loss factor.

Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip

Runtime power management is a critical technique for reducing the energy footprint of digital electronic devices and enabling sustainable computing, since it allows electronic devices to dynamically adapt their power and energy consumption to meet performance requirements. In this article, we consider the case of MultiProcessor Systems-on-Chip (MPSoC) implemented using multiple Voltage and Frequency Islands (VFIs) relying on fine-grained Dynamic Voltage and Frequency Scaling (DVFS) to reduce the system power dissipation. In particular, we present a framework to theoretically analyze the impact of three important technology-driven constraints; (i) reliability-driven upper limits on the maximum supply voltage; (ii) inductive noise-driven constraints on the maximum rate of change of voltage/frequency; and (iii) the impact of manufacturing process variations on the performance of DVFS control for multiple VFI MPSoCs. The proposed analysis is general, in the sense that it is not bound to a specific DVFS control algorithm, but instead focuses on theoretically bounding the performance that any DVFS controller can possibly achieve. Our experimental results on real and synthetic benchmarks show that in the presence of reliability- and temperature-driven constraints on the maximum frequency and maximum frequency increment, any DVFS control algorithm will lose up to 87% performance in terms of the number of steps required to reach a reference steady state. In addition, increasing process variations can lead to up to 60% of fabricated chips being unable to meet the specified DVFS control specifications, irrespective of the DVFS algorithm used. Nonetheless, we note that although conventional DVFS might become less effective with technology scaling, it will continue to play an important role in the context of emerging power management techniques, for example, for massively parallel multiprocessor systems where only a subset of cores can be turned on at any given point of time due to total power constraints.

Three-phase time-aware energy minimization with DVFS and unrolling for Chip Multiprocessors

Energy consumption has been one of the most critical issues in the Chip Multiprocessor (CMP). Using the Dynamic Voltage and Frequency Scaling (DVFS), a CMP system can achieve a balance between the performance and the energy-efficiency. In this paper, we propose a three-phase discrete DVFS algorithm for a CMP system dedicated to applications where the period of the applications’ task graph is smaller than the deadline of tasks. In these applications, multiple task graphs are unrolled and then concatenated together to form a new task graph. The proposed DVFS algorithm is applied to the newly formed task graph to stretch tasks’ execution time, lower operating frequencies of processors and achieve the system power efficiency. Experimental results show that the proposed algorithm reduces the energy dissipation by 25% on average, compared to previous DVFS approaches.

Dynamic Voltage and Frequency Scaling Under an Accurate System Energy Model

Dynamic voltage and frequency scaling (DVFS) is a technique used in modern portable devices operated by battery to set voltage and frequency levels that meet performance requirements while minimizing energy consumption. Most of the present work on DVFS policies are based on simplistic assumptions about the hardware characteristics. In this paper, we discuss the DVFS problem under an accurate system energy model which comes from a application system portable media player (PMP) with a DVFS-capable processor PXA255. We present an optimal DVFS algorithm based on all frequency combinations at the cost of large computation. And a simplified algorithm based on two frequency combinations consumes a little more energy than the former with less computations. The experiment results show that the proposed two algorithms reduce the energy consumption effectively.

DVFS Algorithm Exploiting Correlation in Runtime Distribution

Dynamic voltage and frequency scaling (DVFS) is an effective method to achieve low power design. In our work, we present an analytical DVFS method which judiciously exploits correlation information in runtime distribution while satisfying deadline constraints. The proposed method overcomes the previous distribution-aware DVFS method [2] which has pessimistic assumption on which runtime distributions are independent. Experimental results show the correlation-aware DVFS offers 13.3% energy reduction compared to existing distribution-aware DVFS [2].