Dynamic Threshold Voltage Research Articles

Generalized Bio-Plausible Neuron Model with Refractoriness, Frequency Adaptation and Dynamic Threshold

Real biological neurons are dynamical systems that can process a nonlinear, arbitrary input signal with a dynamic threshold voltage, exhibit refractory time, and have a smooth [Formula: see text]–[Formula: see text] curve. This paper presents a generalized bio-plausible neuron model with refractoriness, frequency adaptation, and dynamic threshold. The spiking characteristics of the generalized neuron are enhanced with less circuitry and fewer parameters compared to older circuits. The proposed silicon neuron can generate all known spiking behaviors, just like a biological neuron. The circuit is designed using a 180[Formula: see text]nm standard CMOS process. The entire design uses 22 transistors with a total power consumption of only 2[Formula: see text]nW for a 1[Formula: see text]nA step current at a spike frequency of 122[Formula: see text]Hz. The power consumption and spike frequency rate depend on the input current. The proposed neuron is also capable of displaying both Type I and Type II frequency response characteristics. In addition, our neuron model underwent Monte Carlo simulation with 1000 sample runs to assess its robustness and stability against process variations and uncertainties. The results indicate that the average energy consumption of the proposed neuron model falls within the range of 16[Formula: see text]pJ to 68[Formula: see text]pJ.

SiC Fin-Channel MOSFET for Enhanced Gate Shielding Effect

A SiC fin-channel MOSFET structure (Fin-MOS) is proposed for an enhanced gate shielding effect. The gates are placed on each side of the narrow fin-channel region, while grounded p-shield regions below the gates provide a strong shielding effect. The device is investigated using Sentaurus TCAD. For a narrow fin-channel region, there is difficulty in forming an Ohmic contact to the p-base; a floating p-base might potentially store negative charges upon high drain voltage, and, thus, causes threshold voltage instabilities. The simulation reveals that, for a fin-width of 0.2 μm, the p-shield regions provide a stringent shielding effect against high drain voltage, and the dynamic threshold voltage shift (∆Vth) is negligible. Compared to conventional trench MOSFET (Trench-MOS) and asymmetric trench MOSFET (Asym-MOS), the proposed Fin-MOS boasts the lowest OFF-state oxide field and reverse transfer capacitance (Crss), while maintaining a similar low ON-resistance.

A New Low-Voltage Second Generation Voltage Conveyor Using Merged Voltage Follower and DTMOS Techniques

A very simple, compact and low-power second generation voltage conveyor circuit using only eight transistors is proposed in this work. Voltage follower stage is implemented using merged voltage follower (MVF), offering very low output impedance. A simple current mirror forms the input stage of the proposed voltage conveyor. To further enhance the linearity, another circuit is proposed where input transistor in MVF is replaced with DTMOS (Dynamic Threshold Voltage MOSFET), giving [Formula: see text][Formula: see text]mV linearity range as compared to [Formula: see text][Formula: see text]mV of the first proposal. Proposed-II VCII provides reduced offset voltage due to decreased effective threshold of DTMOS, and gain bandwidth product of the circuit also improves. Simulation results are computed using 180-nmCMOS technology with supply voltage of [Formula: see text][Formula: see text]V to validate the proposed circuits. Proposed-I and proposed-II VCII consume 85.1[Formula: see text][Formula: see text]W and 97.5[Formula: see text][Formula: see text]W, respectively. An application of the proposed conveyors as “current to voltage converter”, is also presented.

A Differential Rectifier With VTH Compensation for High-Frequency RF Inputs.

A CMOS differential-drive bootstrap (BS) rectifier achieving an efficient dynamic threshold voltage ( VTH)-drop compensation at high-frequency RF inputs is proposed for small biomedical implants with wireless power transmission. A bootstrapping circuit with a dynamically controlled NMOS transistor and two capacitors is proposed to implement a dynamic VTH-drop compensation (DVC). The proposed bootstrapping circuit dynamically compensates the VTH drop of the main rectifying transistors by generating a compensation voltage only when the compensation is required, improving the power conversion efficiency (PCE) of the proposed BS rectifier. The proposed BS rectifier is designed for an ISM-band frequency of 433.92MHz. A prototype of the proposed rectifier is co-fabricated in a 0.18- μm standard CMOS process with another configuration of the rectifier and two conventional BS rectifiers for fair performance comparison at various conditions. According to the measurement results, the proposed BS rectifier achieves better DC output voltage level, voltage conversion ratio, and PCE than the conventional BS rectifiers. With 0-dBm input power, 433.92-MHz frequency, and 3-k Ω load resistor, the proposed BS rectifier achieves a peak PCE of 68.5%.

Analysis of Dead-Time Energy Loss in GaN-Based TCM Converters With an Improved GaN HEMT Model

For gallium nitride (GaN) based triangular current mode (TCM) applications, the dead-time has a significant effect on the switching loss. However, previous GaN high electron mobility transistor (HEMT) models focus on the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on/off</small> process without fully considering the effect of the dead-time. Hence, this article analyzes the switching transients under the superfluous and insufficient dead-time and evaluates the dead-time loss with an improved GaN HEMT model. The proposed model improves an existing GaN HEMT model by adding the voltage rising/falling time of the gate driver, the dynamic threshold voltage of Schottky-type GaN HEMTs, and an equivalent gate-drain capacitance obtained from the datasheet. Verified by a GaN-based double-pulse test, the proposed model can more accurately calculate the gate-source voltage and the self-commutated reverse conduction voltage. Verified by a GaN-based TCM Buck converter, the proposed model can predict the dead-time loss well and has higher simulation accuracy for the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> process induced by the inappropriate dead-time.

Characterization and modeling of drain lag using a modified RC network in the ASM-HEMT framework

Gallium-Nitride High Electron Mobility Transistors (GaN-HEMTs) are susceptible to trapping effects, significantly degrading device performance. The degradation can be seen in the current–voltage characteristics and also manifests in the form of a shift in the dynamic on-resistance and threshold voltage. In this paper, we present pulsed characterization and empirical modeling of a 250 × 10 μm RF GaN HEMT device. To study the impact of drain-induced trapping, pulse I-V characterization is performed at a fixed quiescent gate voltage of −7 V with varying drain quiescent voltage. An empirical RC network approach is proposed to accurately model the trapping in the device. The model effectively captures the impact of trapping and takes into account the self-limiting behavior of traps. The model is implemented in Verilog-A within the Advanced SPICE Model for High Electron Mobility Transistors (ASM-HEMT) framework. Validation of the model is done with six different quiescent conditions of pulse measurement with on-state drain bias varying from 0 V to 20 V.

Extraction of Dynamic Threshold Voltage in Resistive Load Hard Switching Operation of Schottky-Type p-GaN Gate HEMT

Threshold voltage (VTh) drift of Schottky-type p-GaN gate high-electron mobility transistor (HEMT) was analyzed under high-voltage and hard switching conditions with a resistive load (R-Load). To overcome the distortion in the drain current (ID) – gate voltage (VG) curve caused by the internal drain capacitance (IDisp) charging current during the switching transients, a method is presented to accurately measure dynamic VTh through appropriate correction of IDisp. The dynamic variation of VTh was tracked with a gate-drive rise/fall times of 200 ns. During the switching operation, VTh increases rapidly at the beginning and then saturates at a stable value. This is attributed to the gate forward current during turn-on that increases the hole depletion of the p-GaN gate through the AlGaN barrier. The dynamic VTh increases linearly at a rate of 40% with the increase of gate turn-on voltage. VTh is independent of duty cycle but minorly increases with frequency at high voltages, suggesting that channel hot electrons be injected into the AlGaN barrier and p-GaN.

Effect of Dynamic Threshold-Voltage Instability on Dynamic ON-State Resistance in SiC MOSFETs

This work presents an investigation of several important phenomena related to threshold-voltage instability in SiC MOSFETs. Such instability can occur in previously unstressed as-processed devices, including trench-geometry devices, when exposed to a negative gate-bias overstress. This work also reports, for the first time for SiC MOSFETs, on the dynamic nature of ON resistance in the presence of large threshold-voltage instabilities, whether occurring in as-processed devices or due to an ac stress-induced degradation.

(Invited) Updated Issues Regarding Threshold-Voltage Instability in SiC MOSFETs

This work will provide an updated overview of our understanding of several key reliability issues for SiC power MOSFETs related to threshold-voltage stability. Threshold-voltage instability likely occurs due to the charging and discharging of near-interfacial oxide traps in response to a change in gate bias. If enough traps change charge state, it can lead to significant shifts in the threshold voltage, which may in turn lead to increases in leakage current in the off state, or increases in on-state resistance in the on state. An important question is, what is the best—or most appropriate—test method to use to determine the reliability of these devices. It has recently been observed that one commercial device manufacturer has quite large instabilities, even in previously unstressed devices, and that such large instabilities can result in significant increases in on-resistance during normal switching conditions, thereby degrading circuit performance. Other issues addressed will be the effects of AC Stressing, measuring both static and dynamic threshold voltage, and comparing effects in trench and planar geometry devices.

A four-quadrant analog multiplier using DTMOS for low power applications

ABSTRACT The four-quadrant analog multipliers (FQAM) are widely used in signal processing applications such as amplitude modulation, frequency doubling, and adaptive filters. In this paper, a FQAM has been realised in dynamic threshold voltage MOSFET (DTMOS) technology. It relies on the square-law characteristics of the MOS transistor. Several simulations have been carried out to assess the operation of the proposed FQAM. The supply voltage is set to ±0.2 V, and 68 µW power consumption is determined. The input signal can be applied to the full scale of the supply voltage. The bandwidth is 22.86 MHz, and the output signal’s total harmonic distortion (THD) is less than 2%. Intermodulation products of the output signal have been calculated. Monte Carlo and temperature simulations have been performed in a way that confirms the robustness of the circuit against the technological spread. In summary, low power consumption, wide bandwidth, and linearity are the advantages of the proposed circuit.

TCAD Modeling of the Dynamic V TH Hysteresis Under Fast Sweeping Characterization in p-GaN Gate HEMTs

TCAD modeling of the dynamic threshold voltage shift (hysteresis) occurring under fast sweeping characterization in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) is reported, to the best of our knowledge, for the first time. Dynamic <inline-formula> <tex-math notation="LaTeX">${V}_{\text{TH}}$ </tex-math></inline-formula> hysteresis has been first experimentally characterized under different sweeping times, temperatures, and AlGaN barrier configurations. Then, TCAD simulations have been carried out, reproducing the experimental evidences and understanding the microscopic mechanisms responsible for such effect. In particular, nonlocal tunneling models implemented in Sentaurus TCAD, defined at the gate Schottky contact and assisted by traps in the AlGaN barrier layer, have been adopted and properly tuned against experiments. Results show that the dynamic <inline-formula> <tex-math notation="LaTeX">${V}_{\text{TH}}$ </tex-math></inline-formula> hysteresis is mainly caused by the time-dependent hole charging/discharging processes in the floating p-GaN layer, which are governed by the Schottky and AlGaN barrier leakage current components.

A 900 MHz, Wide-Input Range, High-Efficiency, Differential CMOS Rectifier for Ambient Wireless Powering.

This paper presents a wide dynamic-range CMOS rectifier with high efficiency and high sensitivity for RF energy harvesting. A new adaptive-biasing scheme is implemented using stacking diodes with dynamic threshold voltage to mitigate the reverse-leakage current of the NMOS rectifying devices at high RF power levels. The proposed design employs the adaptive-biasing technique to control the conduction of the PMOS rectifying devices with self-bulk biasing of the feedback diodes to minimize the leakage current. The proposed novel techniques extend the dynamic range of the RF-to-DC power converter with high efficiency, which is 17 times better than a conventional cross-coupled rectifier. The prototype is implemented using a standard 65 nm CMOS technology and occupies a 0.0093 mm2 active area. The proposed design achieves a peak power conversion efficiency (peak PCE) of 73%, −18.8 dBm 1-V sensitivity, and a superb dynamic range of 17.3 dB with efficiency greater than 80% of its peak PCE, which outperforms the state-of-the-art RF CMOS rectifiers, when operating at UHF 900 MHz with a 100-KΩ load.

Vertical nanowire/nanosheet FETs with a horizontal channel for threshold voltage modulation

A new type of vertical nanowire (VNW)/nanosheet (VNS) FETs combining a horizontal channel (HC) with bulk/back-gate electrode configuration, including Bulk-HC and FD-SOI-HC VNWFET, is proposed and investigated by TCAD simulation. Comparisons were carried out between conventional VNWFET and the proposed devices. FD-SOI-HC VNWFET exhibits better I on/I off ratio and DIBL than Bulk-HC VNWFET. The impact of channel doping and geometric parameters on the electrical characteristic and body factor (γ) of the devices was investigated. Moreover, threshold voltage modulation by bulk/back-gate bias was implemented and a large γ is achieved for wide range V th modulation. In addition, results of I on enhancement and I off reduction indicate the proposed devices are promising candidates for performance and power optimization of NW/NS circuits by adopting dynamic threshold voltage management. The results of preliminary experimental data are discussed as well.

Wireless Multimodality Sensing System-on-a-Chip With Time-Based Resolution Scaling Technique and Analog Waveform Generator in 0.18 μm CMOS for Chronic Wound Care.

Multimodal sensing can provide a comprehensive and accurate diagnosis of biological information. This paper presents a fully integrated wireless multimodal sensing chip with voltammetric electrochemical sensing at a scanning rate range of 0.08-400 V/s, temperature monitoring, and bi-phasic electrical stimulation for wound healing progress monitoring. The time-based readout circuitry can achieve a 1-20X scalable resolution through dynamic threshold voltage adjustment. A low-noise analog waveform generator is designed using current reducer techniques to eliminate the large passive components. The chip is fabricated via a 0.18 μm CMOS process. The design achieves R2 linearity of 0.995 over a wide current detection range (2 pA-12 μA) while consuming 49 μW at 1.2 V supply. The temperature sensing circuit achieves a 43 mK resolution from 20 to 80 degrees. The current stimulator provides an output current ranging from 8 μA to 1 mA in an impedance range of up to 3 kΩ. A wakeup receiver with data correlators is used to control the operation modes. The sensing data are wirelessly transmitted to the external readers. The proposed sensing IC is verified for measuring critical biomarkers, including C-reactive protein, uric acid, and temperature.

Operational Amplifier Design Employing DTMOS Technique with Dual Supply Voltages

An operational amplifier (OPAMP) for portable devices with dual supply voltage is presented in this work. The design is realized with a 600[Formula: see text]mV supply for the core design and a 1.8[Formula: see text]V supply for the biasing circuit to improve input common mode range (ICMR), gain, and common mode rejection ratio (CMRR). The designed amplifier is implemented with dynamic threshold voltage MOSFET (DTMOS) transistors to decrease power consumption and increase the performance of the design. The power consumption of the core design is obtained as 2[Formula: see text][Formula: see text]W while the biasing circuitry consumes 7.38[Formula: see text][Formula: see text]W. The application of different supply voltages has greatly increased the gain of the circuit, where the circuit exhibits 100.2[Formula: see text]dB DC gain and 3.41[Formula: see text]MHz gain bandwidth product (GBW). CMRR of the designed circuit is 84.22[Formula: see text]dB. The simulations are performed in Cadence environment with 0.18[Formula: see text][Formula: see text]m CMOS technology.

Ferroelectric α‐In2Se3 Wrapped‐Gate β‐Ga2O3 Field‐Effect Transistors for Dynamic Threshold Voltage Control

AbstractIndium selenide (α‐In2Se3), which is a recently emerging ferroelectric semiconductor, can solve a major hindrance to applications of an ultra‐wide bandgap beta‐gallium oxide (β‐Ga2O3) semiconductor. Here, ferroelectric α‐In2Se3 wrapped‐gate β‐Ga2O3 field‐effect transistors (FETs) for dynamic threshold voltage (VTH) control is demonstrated. The dry‐transferred α‐In2Se3 layer is wrapped around β‐Ga2O3 channel, which allows efficient electrostatic gate modulation. Thus, the ferroelectricity of α‐In2Se3 and a thin native oxide interlayer formed at the interface between β‐Ga2O3 and α‐In2Se3 can provide effective VTH control. Applying a positive voltage pulse to the gate electrode induces positive VTH shift; hence, the device can be even changed from depletion to enhancement (E‐) mode. The E‐mode β‐Ga2O3 FET exhibits steep‐subthreshold slope with a negligible hysteresis. The VTH of E‐mode can be further modulated by applying back‐gate bias, and electrical performance can be enhanced via dual‐gate operation. The approach demonstrates an energy efficient β‐Ga2O3‐based switching device architecture integrated with ferroelectric van der Waals 2D materials.

A DTMOS-based power efficient recycling folded cascode operational transconductance amplifier

The focus of the present study is on a recycling folded cascode (RFC) operational transconductance amplifier (OTA) in which the transconductance, as well as the slew rate of OTA, are enhanced. RFC OTA, proposed in this study, is employed using a Dynamic Threshold Voltage MOSFET (DTMOS) based differential pair with class AB operation. To achieve class AB operation, an adaptive biasing technique comprising a flip voltage follower is used which boosts the dynamic current and gain-bandwidth product of OTA. Conventional current mirrors are replaced with source degenerated non-linear current mirrors to achieve a better slew rate. The conventional and proposed RFC structures are designed and simulated in a standard 180 nm CMOS process at 1 V supply voltage. The proposed RFC OTA demonstrates a significant enhancement in the performance parameter as 11 dB improvement in the gain as well as 290% more GBW and achieves a slew rate that is nine times better compared to the conventional RFC.

Principles and impacts of dynamic threshold voltage in a p-GaN gate high-electron-mobility transistor

GaN power transistors are attracting increasing attention for next-generation power switching applications. However, GaN power transistors should not be regarded as a direct replacement for silicon power metal–oxide–semiconductor field-effect transistors, since the unique properties of GaN power transistors require special treatment. In this work we review a unique and critical property of GaN power transistors, the dynamic threshold voltage (V th). GaN power transistors feature a p-GaN gate structure, while the gate metal contacts the p-GaN layer through a Schottky junction. This unique p-GaN gate structure is distinctively different from the silicon metal–oxide–semiconductor gate structure in that the p-GaN layer is actually a floating region without direct electrical contact to the external electrodes of the device. The floating p-GaN layer enables a charge storage process during the switching operation of a p-GaN gate high-electron-mobility transistor. Through carefully designed experiments, the strong correlation between charge storage and the dynamic V th shift has been revealed; this also serves as an approach to accurately predict the dynamic V th during switching operation. The influence of the dynamic V th on power switching applications is discussed. For example, with a positive dynamic V th shift, the reverse conduction voltage of a GaN power transistor is significantly increased, adding to the power loss. This positive V th shift also demands a sufficiently high gate drive voltage to ensure that the GaN power transistor can be fully turned on, which reduces the safety margin for the gate reliability of the device. To design a GaN based power switching circuit, accurate simulation of the device/circuit characteristics is necessary. Circuit simulations that do not consider the dynamic V th lead to a large deviation from the measurement circuit characteristics. We demonstrate that by incorporating the dynamic V th into the circuit model this deviation can be effectively eliminated.

Nanopower multiple-input DTMOS OTA and its applications to high-order filters for biomedical systems

A new solution for a low-voltage multiple-input dynamic threshold operational transconductance amplifier (MIDT OTA) for low-frequency signal processing applications is presented. The differential pairs of the proposed OTA combine, for the first time, the multiple-input MOS technique along with the dynamic threshold voltage MOS to achieve a very simple and power-efficient CMOS structure with increased total transconductance. Further, the proposed MIDT OTA has been used to realize a fifth-order low-pass filter (LP) and a sixth-order band-pass filter (BP) using coupled-biquads. The proposed OTA and the filter applications are supplied with 0.5 V and consume 5 nW and 25 nW, respectively. The input band pass filter noise is 82.76 µV, while the dynamic range is 59.5 dB for the third intermodulation distortion (IMD) of 2%. The proposed circuits were designed in a 0.18 µm TSMC technology, and validated by simulations using Cadence platform.

Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs

One of the main challenging issues for germanium (Ge) devices is the gate stack engineering which determines the interface state density (NIT) and the associated channel/oxide interface quality. This paper shows how this issue can play a role in p-channel Ge MOSFETs considering both the operation mode, i.e., comparing conventional, dynamic threshold voltage (DT, where VBS = VGS) and enhanced dynamic threshold voltage (eDT, where VBS=k*VGS) modes, and the main analog parameters like the Early voltage (VEA) and intrinsic voltage gain (AV). Moreover, the impact of different HfO2/Al2O3 gate stack thicknesses is under evaluation. Although the thinnest Al2O3 layer degrades all evaluated parameters, specifically: lower VEA and AV, higher drain current hysteresis and subthreshold swing (SS) due to the higher NIT, the dynamic threshold voltage showed to be an effective mode to strongly minimize the hysteresis effects and improves up to 60% in eDT (k = 2) mode compared to the conventional mode (k = 0), thanks to the dynamic threshold voltage reduction.