Dynamic Threshold Voltage Control Research Articles

Ferroelectric α‐In2Se3 Wrapped‐Gate β‐Ga2O3 Field‐Effect Transistors for Dynamic Threshold Voltage Control

AbstractIndium selenide (α‐In2Se3), which is a recently emerging ferroelectric semiconductor, can solve a major hindrance to applications of an ultra‐wide bandgap beta‐gallium oxide (β‐Ga2O3) semiconductor. Here, ferroelectric α‐In2Se3 wrapped‐gate β‐Ga2O3 field‐effect transistors (FETs) for dynamic threshold voltage (VTH) control is demonstrated. The dry‐transferred α‐In2Se3 layer is wrapped around β‐Ga2O3 channel, which allows efficient electrostatic gate modulation. Thus, the ferroelectricity of α‐In2Se3 and a thin native oxide interlayer formed at the interface between β‐Ga2O3 and α‐In2Se3 can provide effective VTH control. Applying a positive voltage pulse to the gate electrode induces positive VTH shift; hence, the device can be even changed from depletion to enhancement (E‐) mode. The E‐mode β‐Ga2O3 FET exhibits steep‐subthreshold slope with a negligible hysteresis. The VTH of E‐mode can be further modulated by applying back‐gate bias, and electrical performance can be enhanced via dual‐gate operation. The approach demonstrates an energy efficient β‐Ga2O3‐based switching device architecture integrated with ferroelectric van der Waals 2D materials.

A Novel SRAM Cell Design with a Body-Bias Controller Circuit for Low Leakage, High Speed and Improved Stability

A dynamic threshold voltage control strategy is presented in this paper to minimize leakage power while enhancing the speed and stability. The threshold voltage of driver and access transistor are tuned dynamically through a novel body-bias controller circuit. The word line signal level controls the action of the proposed body-bias controller. In order to reduce subthreshold leakage current, the threshold voltage of NMOS access and driver transistors are adjusted to a high value by applying a reverse body-bias. On the other hand, forward body-bias lowers the threshold voltage of NMOS access transistor thereby enabling faster read and writes operation. Simulation results shows that the proposed design is much better than conventional and other SRAM cells such as, NC SRAM, PP SRAM, WRE8T. The amount of leakage power reduction is as high as 41.071 % over conventional 6T SRAM cell when tested on (8 × 16) SRAM array. Whereas, the improvement in read and write delay is 30 and 15.81 % respectively.

49.3: Oxide TFT Scan Driver with Dynamic Threshold Voltage Control

AbstractOxide TFTs have a negative threshold voltage (Vth), which can become even more negative in response to DC or AC stress. Therefore, these voltage stresses can cause severe leakage current in a scan driver. In this paper, a scan driver with dynamic threshold voltage control (DTVC) is proposed to minimize the leakage current and enlarge operating margin. Effectiveness of DTVC was verified with a 14‐inch AMOLED.

Tri-Gate Bulk MOSFET Design for CMOS Scaling to the End of the Roadmap

A tri-gate bulk MOSFET design utilizing a low-aspect-ratio channel is proposed to provide an evolutionary pathway for CMOS scaling to the end of the roadmap. 3-D device simulations indicate that this design offers the advantages of a multi-gate FET (reduced variability in performance and improved scalability) together with the advantages of a conventional planar MOSFET (low substrate cost and capability for dynamic threshold-voltage control).

Static Noise Margin Enhancement by Flex-Pass-Gate SRAM

A Flex-Pass-Gate SRAM, i.e. a fin-type-field-effect-transistor- (FinFET-) based SRAM, is proposed to enhance noise margin during both read and write operations. In its cell, the flip-flop is composed of usual three-terminal- (3T-) FinFETs while pass gates are composed of four-terminal- (4T-) FinFETs. The 4T-FinFETs enable to adopt a dynamic threshold-voltage control in the pass gates. During a write operation, the threshold voltage of the pass gates is lowered to enhance the writing speed and stability. During the read operation, on the other hand, the threshold voltage is raised to enhance the static noise margin. An asymmetric-oxide 4T-FinFET is helpful to manage the leakage current through the pass gate. In this paper, a design strategy of the pass gate with an asymmetric gate oxide is considered, and a TCAD-based Monte Carlo simulation reveals that the Flex-Pass-Gate SRAM based on that design strategy is expected to be effective in half-pitch 32-nm technology for low-standby-power (LSTP) applications, even taking into account the variability in the device performance.

Dynamic threshold voltage control for dual supply voltage scheme on PD-SOI

The dual supply voltage (dual-VDD) scheme reduces the active power consumption without performance degradation by using two power supply rails. However, an increase in the delay due to the scaled-down supply voltage has made assigning the lower supply voltage (VDDL) more difficult in the conventional dual-VDD scheme. We propose a technique for the dual-VDD scheme employing the Active Body-biasing Control (ABC) on PD-SOI, which increases the number of VDDL-cells owing to lowered threshold voltage. Simulation results have shown our approach effectively reduces the power consumption even at low voltage operation.

Back-gated CMOS on SOIAS for dynamic threshold voltage control

The simultaneous reduction of power supply and threshold voltages for low-power design without suffering performance losses will eventually reach the limit of diminishing returns as static leakage power dissipation becomes a significant portion of the total power consumption. This is especially acute in systems that are idling most of the time. In order to meet the opposing requirements of high performance at reduced power supply voltage and low-static leakage power during idle periods, a dynamic threshold voltage control scheme is proposed. A novel Silicon-On-Insulator (SOI)-based technology called Silicon-On-Insulator-with-Active-Substrate (SOIAS) was developed whereby a back-gate is used to control the threshold voltage of the front-gate; this concept was demonstrated on a selectively scaled CMOS process implementing discrete devices and ring oscillators. For a 250 mV switch in threshold voltage, a reduction of 3-4 decades in subthreshold leakage current was measured.