Dynamic Reference Voltage Research Articles

A dynamic reference voltage adjustment strategy for Open-UPQC to increase hosting capacity of electrical distribution networks

Future electrical grids, particularly the distribution networks, may face more severe voltage rises/drops, and in general, more power quality problems in the presence of new loads such as electric vehicle chargers and renewable energy generation units like photovoltaic systems. This necessitates investing in additional high-cost infrastructure to increase the capability of the feeder in hosting higher levels of loads and generation units while the existing capacity is not utilized effectively. In the stated condition, effective voltage stabilization strategies in electrical distribution networks can contribute to hosting capacity improvement and the better utilization of the existing infrastructure. Accordingly, in this paper, the application of Open-UPQC in voltage profile improvement and hosting capacity enhancement is evaluated in low-voltage distribution networks. Furthermore, a dynamic reference voltage adjustment strategy is applied to the device to improve its capabilities in power quality improvement and hosting capacity enhancement. Simulation studies have been implemented to evaluate the capability of Open-UPQC either with static reference voltage or the dynamically-adjusted one in low-voltage networks with real measured data while different cases are assessed regarding the topology and the length of the feeder. The simulation results approved the capability of Open-UPQC especially with the dynamic reference voltage in hosting capacity enhancement while providing the highest level of voltage profile improvement among all the assessed custom power devices in the studied low-voltage networks.

An Energy-Efficient Inference Engine for a Configurable ReRAM-Based Neural Network Accelerator

Resistive random-access memory (ReRAM) offers a potential solution to accelerate the inference of deep neural networks by performing processing-in-memory. However, the peripheral circuits of ReRAM crossbars used to perform arithmetic operations consume significant amounts of power. Based on a power consumption analysis of the ReRAM crossbar circuits, we propose using the dynamic reference voltage scalable analog-to-digital circuits (ADCs) to conduct the dot product operation to enable the reconfigurability of the ReRAM-based neural network (NN) accelerator while maintaining accuracy. We propose a configurable ReRAM-based NN accelerator to provide various degrees of computing granularity with different levels of power consumption, creating a tradeoff between performance and power consumption in the given NN. Next, we develop an energy-efficient inference engine for the configurable ReRAM-based NN accelerator, EIF, to assign the operation unit (OU) size to perform vector-matrix multiplication (VMM) based on the data dependence of the NN. Our evaluation shows that the proposed EIF provided an energy savings of up to 36% over the state-of-the-art ReRAM-based accelerator while maintaining performance without resource duplication.

A Timing-Based Split-Path Sensing Circuit for STT-MRAM.

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) applications have received considerable attention as a possible alternative for universal memory applications because they offer a cost advantage comparable to that of a dynamic RAM with fast performance comparable to that of a static RAM, while solving the scaling issues faced by conventional MRAMs. However, owing to the decrease in supply voltage (VDD) and increase in process fluctuations, STT-MRAMs require an advanced sensing circuit (SC) to ensure a sufficient read yield in deep submicron technology. In this study, we propose a timing-based split-path SC (TSSC) that can achieve a greater read yield compared to a conventional split-path SC (SPSC) by employing a timing-based dynamic reference voltage technique to minimize the threshold voltage mismatch effects. Monte Carlo simulation results based on industry-compatible 28-nm model parameters reveal that the proposed TSSC method obtains a 42% higher read access pass yield at a nominal VDD of 1.0 V compared to the SPSC in terms of iso-area and -power, trading off 1.75× sensing time.

A Hybrid Constant On-Time Mode for Buck Circuits

To achieve a designed and fixed operating frequency for a controller with high dynamic performance and a high load capacity, a hybrid constant on-time (COT) voltage mode for a Buck circuit is proposed and discussed in this paper. The proposed hybrid strategy is a combination of the classical COT method, a dynamic reference voltage technology and a proportional–differential (PD) module. The workflow is demonstrated in brief, simulations of a Buck circuit with the proposed hybrid COT mode are conducted and comparisons with developed pulse-width modulation (PWM) technology and the hysteresis mode are made. The results show that, with the help of the proposed control scheme, impressive performance from the Buck circuit can be expected. The operating frequency can be fixed well by the hybrid technology without losses of performance and robustness in steady state and will not jump much even with the sudden change of the inputs and the load. The proposed control strategy contributes to the foundation of circuit design and optimization.

Novel MTJ-Based Sensing Inverter Variation Tolerant Nonvolatile Flip-Flop in the Near-Threshold Voltage Region

In recent years, the low power design of Internet of Things devices has become increasingly important. The most basic method to implement a low power design is to reduce static power consumption. In this regard, a spin-transfer-torque magnetic-tunnel-junction-based nonvolatile flip-flop (NVFF) is a promising candidate for storing the computing data while the power is off. However, as the technology node scales down, the process variation increases, leading to a restoration failure in previous NVFFs, especially in the near-threshold voltage (NTV) region. For better energy efficiency when operating the NVFF in the NTV region, this article presents a novel NVFF that guarantees a target restore yield of 4σ and a target read disturbance margin of 6σ in the NTV region (0.6 V supply voltage), along with auto-zeroing and dynamic reference voltage (DRV) techniques, using only a single capacitor to improve the NVFF's restore yield. The Monte Carlo HSPICE simulation results using industry-compatible 28-nm model parameters show that the proposed NVFF satisfies both the target restore yield and the read disturbance margin, saving 44% restoration time compared with the current state-of-the-art NVFF, which does not satisfy the target restore yield despite having offset cancellation characteristic.

Dynamic Reference Voltage Sensing Scheme for Read Margin Improvement in STT-MRAMs

This paper proposes a novel approach to enhance the STT-MRAMs read margin based on the concept of dynamic reference (DR). Our dynamic reference scheme dynamically adjusts the sense amplifier reference voltage according to the bitline voltage, aiming to widen the difference between the bitline and the reference voltage (i.e., the read margin). As a result, larger variations can be accommodated, thus improving the read robustness and substantially reducing the read failure rate. This DR scheme does not require any change in the bitcell and requires minimal modifications of conventional arrays, hence it can be jointly used with existing assist techniques enhancing the read robustness. From Monte Carlo simulations in 65 nm, the proposed DR scheme improves the read bit error rate by two orders of magnitude across a wide range of voltages (0.75–1.2 V) compared with the conventional voltage sensing scheme. This is achieved at 0.3% area overhead, less than 15% performance degradation, and less than 25% energy penalty. Furthermore, the joint adoption of the DR approach and switched-cap bitline boosting further reduces the sense amplifier area by 25% at iso-failure rate, and reduces the energy by 6–10% compared with the standalone DR.

Power and Voltage Balance Control of a Novel Three-Phase Solid-State Transformer Using Multilevel Cascaded H-Bridge Inverters for Microgrid Applications

This paper presents a new application of power and voltage balance control schemes for the cascaded H-bridge multilevel inverter (CHMI)-based solid-state transformer (SST) topology. To reduce load on the controller and simplify modulation algorithm, a master–slave control (MSC) strategy is designed for the dual active bridge (DAB) stage. The master controller executes all control and modulation calculations, and the slave controllers manage only device switching and protection. Due to the inherent power and dc-link voltage unbalance in cascaded H-bridge-based SST, this paper presents a compensation strategy based on three-phase dq decoupled current controller. An optimum zero-sequence component is injected in the modulation scheme so that the three-phase grid currents are balanced. Furthermore, to tightly regulate the output voltage of all the DAB modules to target value, a dynamic reference voltage method is also implemented. With this proposed control method, the three-phase grid currents and dc-link voltage in each module can be simultaneously balanced. Finally, simulation and experimental results are presented to validate the performance of the controller and its application to microgrid SST.

Design Considerations for a 6 Bit 20 GS/s SiGe BiCMOS Flash ADC Without Track-and-Hold

A novel comparator placing scheme and reference ladder concept are presented for flash analog-to-digital converters (ADC), that minimize the dynamic reference voltage distortions at high signal speed. No track-and-hold or time interleaving is used in the ADC, which reduces the design complexity and minimizes the conversion latency. The data input signal is buffered by an emitter follower (EF) and distributed by a passive transmission line (TML) tree to the comparators. The EF and comparators are systematically optimized with respect to the energy efficiency and design considerations for the trade off between dynamic linearity and power dissipation are given in detail. The TML tree is designed such that in spite of inhomogeneous loading by the comparators equal transfer functions are achieved along all paths. The ADC achieves without calibration or correction an effective resolution beyond 3.7 bits up to 10 GHz signal frequency and 20 GS/s sampling. With 1.0 W of power dissipation the conversion efficiency is 3.9 pJ per conversion step, which sets a record for single-core ADCs beyond 10 GS/s Nyquist rate.

AN IMPLANT FOR A VISUAL CORTICAL STIMULATOR

We present the design of an implantable micro-stimulator intended for a cortical visual prosthesis. The device is composed of several integrated modules to be assembled on a thin and flexible substrate providing placement flexibility on the cortex. The stimulator provides the user with significant usage flexibility, supplying biphasic current pulses using either monopolar or bipolar configurations, with single or distributed return electrode, and having a fixed or dynamic reference voltage. Monitoring of electrode-tissue interface condition is possible by measuring both simulation currents and voltages at any electrode for enhanced safety, and for enabling troubleshooting after implantation. In order to avoid erroneous stimulation to be executed, potentially caused by the implant's wireless transcutaneous power transfer, constant parameters stored in volatile memory are constantly monitored, and in case of data corruption, stimulation is automatically disabled. A power efficient recovery and regulation circuit is proposed for providing dual supply voltages. Also, a bidirectional wireless link with data rates up to 1.5 Mbps and 500 kbps, downlink and uplink respectively, has been designed for use with a 13.56 MHz carrier. Performances attained with a prototype, combined with the stimulator module's configurable communication protocol, are suitable for a cortical implant having more than 1000 stimulation sites, which is expected to be sufficient for providing blind subjects with a useful vision.

A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters

This letter presents the design of a window successive approximation (SAR) analog-to-digital converter (ADC) using an ultra-fast, offset-cancelled auto-zero comparator for digital DC---DC converters. It is designed in a standard CMOS 0.18 μm process. The ADC has a dynamic reference voltage range to reduce power consumption. The auto-zero scheme of the comparator is realized internally with a preamplifier stage and a latch stage. Post-layout simulation shows that the response time of the comparator from low-to-high and high-to-low is 3.78 ns and 2.47 ns, respectively. The resolution of the proposed window SAR ADC is 7.5 mV. The ADC is fabricated as part of a digital DC---DC converter integrated circuit and measurement results show that an average power consumption of 0.8 μW is achieved. The transient time of the DC---DC converter is within 150 ns for a load current change of 495 mA.

2.5 Gb/s DC coupled retimed optical transducer with a dynamic reference voltage comparator

A monolithic broad-band dc-coupled Silicon bipolar optical transducer has been designed to receive and retime uncoded data at rates up to 2.5 Gb/s. The transducer employs a modified feedback emitter coupled logic (FECL) loop to dynamically set reference voltages derived from the and 0 level output signals of the single-ended pre-amplifier for balanced operation of the decision circuit. The pre-amplifier has a nominal sensitivity of -23.1 dBm at 1 GHz.

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 /spl mu/m complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V. >