Dynamic Reconfigurable Architecture Research Articles

SHARP: An Adaptable, Energy-Efficient Accelerator for Recurrent Neural Networks

The effectiveness of Recurrent Neural Networks (RNNs) for tasks such as Automatic Speech Recognition has fostered interest in RNN inference acceleration. Due to the recurrent nature and data dependencies of RNN computations, prior work has designed customized architectures specifically tailored to the computation pattern of RNN, getting high computation efficiency for certain chosen model sizes. However, given that the dimensionality of RNNs varies a lot for different tasks, it is crucial to generalize this efficiency to diverse configurations. In this work, we identify adaptiveness as a key feature that is missing from today’s RNN accelerators. In particular, we first show the problem of low resource utilization and low adaptiveness for the state-of-the-art RNN implementations on GPU, FPGA, and ASIC architectures. To solve these issues, we propose an intelligent tiled-based dispatching mechanism for increasing the adaptiveness of RNN computation, in order to efficiently handle the data dependencies. To do so, we propose Sharp as a hardware accelerator, which pipelines RNN computation using an effective scheduling scheme to hide most of the dependent serialization. Furthermore, Sharp employs dynamic reconfigurable architecture to adapt to the model’s characteristics. Sharp achieves 2×, 2.8×, and 82× speedups on average, considering different RNN models and resource budgets, compared to the state-of-the-art ASIC, FPGA, and GPU implementations, respectively. Furthermore, we provide significant energy reduction with respect to the previous solutions, due to the low power dissipation of Sharp (321 GFLOPS/Watt).

Intelligent Optimization Approaches for a Secured Dynamic Partial Reconfigurable Architecture-Based Health Monitoring System

In this work, an intelligent multi-objective optimization technique is proposed to optimize various parameters such as power consumption ([Formula: see text]), computation time ([Formula: see text]) and area ([Formula: see text]) for a health monitoring system designed using the Secured Dynamic Partial Reconfiguration (SDPR) architecture. The cost-efficient Dynamic Partial Reconfiguration (DPR)-based field-programmable gate array (FPGA) is very useful for analyzing many applications such as automation and data processing. The novelty of this paper is to design a new intelligent SDPR (i-SDPR) module in order to achieve better performance in a health monitoring system by considering various performance parameters. The SDPR architecture is incorporated with two reconfigurable modules such as Encrypt and Authenticate, which results in an increase in the core power consumption ([Formula: see text]), computation time ([Formula: see text]) and area ([Formula: see text]). So, to improve the performance of the SDPR-based health monitoring system, there is a necessity to optimize the performance parameters and it is achieved through intelligent multi-objective evolutionary (MOEA) techniques. The intelligent multi-objective evolutionary techniques such as Niched-Pareto Genetic Algorithm (NPGA), Pareto Archived Evolution Strategy (PAES) and Pareto Envelope-based Selection Algorithm (PESA) have been considered for better optimization in the performance parameters. For the study, the free-to-use MIMIC-III dataset is taken, which contains critically admitted various intensive care unit patient data. The dataset is processed through any one of the multi-objective evolutionary operators till satisfying the conditions and then forwarded to implementation. The proposed architecture has been implemented and tested using Cyclone[Formula: see text] V SX SoC Development Kit. The comparative analysis of various performance parameters was done for the proposed i-SDPR with the existing techniques such as the DPR and SDPR approach to show the improvement. The results declare that the proposed techniques obtain better performance compared to the existing techniques.

A Dynamic Reconfigurable Architecture for Hybrid Spiking and Convolutional FPGA-Based Neural Network Designs

This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Reconfiguration (DPR) is increasingly used in NN accelerators, the throughput is usually lower than pure static designs. This work presents a dynamically reconfigurable energy-efficient accelerator architecture that does not sacrifice throughput performance. The proposed accelerator comprises reconfigurable processing engines and dynamically utilizes the device resources according to model parameters. Using the proposed architecture with DPR, different NN types and architectures can be realized on the same FPGA. Moreover, the proposed architecture maximizes throughput performance with design optimizations while considering the available resources on the hardware platform. We evaluate our design with different NN architectures for two different tasks. The first task is the image classification of two distinct datasets, and this requires switching between Convolutional Neural Network (CNN) architectures having different layer structures. The second task requires switching between NN architectures, namely a CNN architecture with high accuracy and throughput and a hybrid architecture that combines convolutional layers and an optimized Spiking Neural Network (SNN) architecture. We demonstrate throughput results from quickly reprogramming only a tiny part of the FPGA hardware using DPR. Experimental results show that the implemented designs achieve a 7× faster frame rate than current FPGA accelerators while being extremely flexible and using comparable resources.

The DReAM framework for dynamic reconfigurable architecture modelling: theory and applications

Modern systems evolve in unpredictable environments and have to continuously adapt their behaviour to changing conditions. The “DReAM” (Dynamic Reconfigurable Architecture Modelling) framework has been designed for modelling reconfigurable dynamic systems. It provides a rule-based language, inspired from Interaction Logic, which is expressive and easy to use encompassing all aspects of dynamicity including parametric multi-modal coordination with creation/deletion of components as well as mobility. Additionally, it allows the description of both endogenous/modular and exogenous/centralized coordination styles and sound transformations from one style to the other. The DReAM framework is implemented in the form of a Java API bundled with an execution engine. It allows us to develop runnable systems combining the expressiveness of the rule-based notation together with the flexibility of this widespread programming language.

Towards Dynamic and Partial Reconfigurable Hardware Architectures for Cryptographic Algorithms on Embedded Devices

In the era of IoT, embedded systems are becoming the cornerstone of many IoT related applications, such as smart cars and wearable devices. However, embedded devices have numerous constraints and requirements, including stringent area and power, reduced cost and time-to-market, and increased speedup. Furthermore, these applications are becoming increasingly compute/data-intensive requiring more processing power. Also, especially for IoT related applications, security is another major issue in resource-constrained embedded devices. Although cryptographic algorithms are widely used to ensure the security of these applications, commonly used ones, such as AES, are unsuitable for highly constrained embedded devices, due to their sheer complexity. Hence, several lightweight cryptographic algorithms were proposed in the literature that might be better suited for embedded devices. From these, SPECK and SIMON, introduced by NSA, are the two most popular ones. Another important challenge is how to incorporate the cryptographic algorithms in to embedded devices, efficiently and effectively, without compromising the integrity of the compute/data-intensive applications running on these small-footprint devices. Our previous analysis demonstrated that FPGAs are currently the best avenue to support compute/data-intensive applications running on resource-constrained embedded devices, due to FPGA’s many attractive traits, including, post-fabrication reprogrammability, dynamic and partial reconfiguration capabilities, and reduced time-to-market. Also, FPGAs can be utilized to provide several advantages/features required for the embedded device’s security, such as cryptographic algorithm agility, algorithm upload, algorithm modification, and resource efficiency. In this research work, we introduce novel, unique, and efficient dynamic and partial reconfigurable hardware architectures for the most popular SPECK and SIMON algorithms on embedded devices, considering the constraints associated with these devices and the requirements of the applications running on embedded devices. We also introduce unique system-level architectures for our proposed designs. To the best of our knowledge, no similar work exists in the literature that provides dynamic and partial reconfigurable hardware for SPECK and SIMON, and also provides system-level architecture. Our dynamic and partial reconfigurable hardware designs achieve 28% space saving compared to its static reconfigurable hardware, and 59 times speedup compared to its software counterpart.

Nullspace-Based Input Reconfiguration Architecture for Overactuated Aerial Vehicles

A dynamic input reconfiguration architecture is proposed for overactuated aerial vehicles to accommodate actuator failures. The method is based on the dynamic nullspace computed from the linear parameter-varying model of the plant dynamics. If there is no uncertainty in the system, then any signal filtered through the nullspace has no effect on the plant outputs. This makes it possible to reconfigure the inputs without influencing the nominal control loop and thus the nominal control performance. Since the input allocation mechanism is independent of the structure of the baseline controller, it can be applied even if the baseline controller is not available in analytic form. The applicability of the proposed algorithm is demonstrated via the case study of designing a fault tolerant controller for the Rockwell B-1 Lancer aircraft.

A Multi-Synchronous Bi-Directional NoC (MBiNoC) architecture with dynamic self-reconfigurable channel for the GALS infrastructure

To enhance the performance of on-chip communications of Globally Asynchronous Locally Synchronous Systems (GALS), a dynamic reconfigurable multi-synchronous router architecture is proposed to increase network on chip (NoC) efficiency by changing the path of the communication link in the runtime traffic situation. In order to address GALS issues and bandwidth requirements, the proposed multi-synchronous bidirectional NoC’s router is developed and it guarantees higher packet consumption rate, better bandwidth utilization with lower packet delivery latency. All the input/output ports of the proposed router behave as a bi-directional ports and communicate through a novel multi-synchronous first-in first-out (FIFO) buffer. The bidirectional port is controlled by a dynamic channel control module which provides a dynamic reconfigurable channel to the router itself and associated sub-modules. This proposed multi-synchronous bidirectional router architecture is synthesized using Xilinx ISE 14.7 and FPGA Virtex 6 family device XC6VLX760 is considered as target technology and its performance is evaluated in terms of power, area and delay.

Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

With the advancement of mobile and embedded devices, many applications such as data mining have found their way into these devices. These devices consist of various design constraints including stringent area and power limitations, high speed-performance, reduced cost, and time-to-market requirements. Also, applications running on mobile devices are becoming more complex requiring significant processing power. Our previous analysis illustrated that FPGA-based dynamic reconfigurable systems are currently the best avenue to overcome these challenges. In this research work, we introduce efficient reconfigurable hardware architecture for principal component analysis (PCA), a widely used dimensionality reduction technique in data mining. For mobile applications such as signature verification and handwritten analysis, PCA is applied initially to reduce the dimensionality of the data, followed by similarity measure. Experiments are performed, using a handwritten analysis application together with a benchmark dataset, to evaluate and illustrate the feasibility, efficiency, and flexibility of reconfigurable hardware for data mining applications. Our hardware designs are generic, parameterized, and scalable. Furthermore, our partial and dynamic reconfigurable hardware design achieved 79 times speedup compared to its software counterpart, and 71% space saving compared to its static reconfigurable hardware design.

컴포넌트 관리 및 검증도구 설계와 동적 재구성 아키텍처 기반 SAM 시뮬레이터 개발

모델링 및 시뮬레이션 기술은 전장 환경을 고려한 실험 환경을 조성하여 무기 체계의 구성 요소에 대한 성능 분석을 실제와 유사하게 할 수 있다. 그러나 이전까지 모델링 및 시뮬레이션에서 개발된 무기체계 모델은 제한된 범위 내에서만 활용되어 확장성이 낮고 재사용성은 크게 고려하지 않았다. 이에 본 연구에서는 재사용성을 고려하여 개발된 컴포넌트에 대한 사용 검증 및 확장성 판단을 위한 검증도구와 컴포넌트를 효율적으로 관리하기 위한 관리 도구를 개발한다. 또한 이전 연구에서 설계한 유도무기체계의 동적 컴포넌트 재구성 아키텍처를 지대공유도무기 SAM(Surface to Air Missile) 교전 시뮬레이터에 적용하여 기 개발된 컴포넌트에 대한 효과도를 확인한다. 그리하여, 동적 컴포넌트 재구성 아키텍처의 시뮬레이션 적용을 통해 컴포넌트 기반의 재사용으로 유도무기체계에 대한 다양한 시스템을 구성하게 되었다. Modeling and simulation techniques construct experimental environment considering battlefields and are able to analyze performance of components of weapon system that closely resemble reality. However, developed model has low scalability and not cared reusability because it has been used only in a limited range of domain. In this paper, we develop a verification tool to verify reusability of developed component for dynamic reconfiguration and to judge scalability of it and a management tool to control data of it effectively. In addition, dynamic reconfiguration architecture of guided weapon systems designed in the previous study has been applied to SAM(Surface to Air Missile) System Simulator, and we study effectiveness of the developed component. Thus the user can configure various guided weapon systems through simulation application of dynamic reconfiguration architecture of component.

Reconfigurable 2.5-Gb/s Baseband and 60-GHz (155-Mb/s) Millimeter-Waveband Radio-Over-Fiber (Interleaving) Access Network

In this paper, we propose a dynamic reconfigurable wavelength division multiplexed (WDM) millimeter-waveband radio-over-fiber (RoF) and baseband access network. We also demonstrate dynamic channel allocation capability of millimeter-waveband optical RoF and baseband signals in WDM access network using a supercontinuum (SC) light source, arrayed-waveguide gratings, and a reconfigurable optical crossconnect switch. The dynamic reconfigurable RoF and baseband network architecture is presented and its features are described. Two 155-Mb/s RoF channels and two 2.5-Gb/s baseband channels are effectively generated, transmitted through 25 km of fiber, switched, and then transmitted again through 2 km of fiber and detected with error-free operation (bit error rate< 10-9). The proposed architecture allows the RoF and baseband to coexist and is highly scalable, both in terms of channel counts and access point (AP) counts.

Dynamic Reconfigurable WDM 60-GHz Millimeter-Waveband Radio-Over-Fiber Access Network: Architectural Considerations and Experiment

We will propose a dynamic reconfigurable wavelength-division-multiplexed (WDM) millimeter-waveband (mm-waveband) radio-over-fiber (RoF) access network and demonstrate, for the first time, a dynamic-channel-allocation capability of millimeter-waveband optical RoF signals in WDM access network using a supercontinuum light source, arrayed-waveguide gratings, and a reconfigurable optical-crossconnect switch. The dynamic reconfigurable RoF network architecture is presented, and its features are described. Then, four 155-Mb/s RoF channels are effectively generated, transmitted through 25 km of fiber, switched, transmitted again through 2 km of fiber, and detected with an error-free operation (bit error rate < 10-10). The proposed RoF architecture is highly scalable, both in terms of channel and access-point counts.

New Adaptive Multi-grained Hardware Architecture for Processing of Dynamic Function Patterns (Neue adaptive multi-granulare Hardwarearchitektur)

A new dynamic reconfigurable hardware architecture, the HoneyComb, will be introduced that has been developed within the project AMURHA. New integrated features enhance the flexibility and usability of future array-based systems by exploring the new approach.

A predictive dynamic output buffer reconfiguration (PDOBR) architecture for ATM networks

The traditional output buffer architecture in ATM switches is realized in one of two forms – shared or separate. In the shared design, all of the N output links utilize a large common buffer, of size S cells, in an effort to achieve efficient use of the total buffer space. Under the separate buffer architecture, distinct buffers, each of size S N cells, are assigned to every output link, the goal being to realize fair buffer usage by every individual output link. For both architectures, however, the buffer organization is determined, permanently, at the time of the switch fabric design, and may not be altered during actual operation. The highly dynamic and stochastic nature of ATM traffic poses a key difficulty for this tradition. This paper introduces a radically new approach, termed Predictive Dynamic Output Buffer Reconfiguration (PDOBR) architecture, wherein the output buffer organization in the switch fabric is reconfigured dynamically, i.e., during network operation, under the call processor’s control, such that the network incurs minimal cell drop stemming from buffer overflow. Under PDOBR, the output buffer at every node of the ATM network is organized in the form of separate buffers for each output link, of size S N cells, plus a “floating” buffer of the same size, that may be appended, at runtime, to any one of the output links to augment its net buffer capacity. In contrast to the shared buffer that experiences severe congestion and gross unfairness under bursty traffic, separate buffers result is fairness in buffer availability between the output links, yielding efficient behavior. Utilizing its knowledge of the successful user call requests and the magnitudes of the corresponding sustained cell rate (SCR) bandwidth requests, the call processor at every ATM node computes the net bandwidth commitment for each of its output links through a simple summation of the corresponding SCR values. The call processor then compares the net bandwidth commitment for every output link against an empirical threshold, obtained through systematic analysis, to predict and identify a single output link, if any, that is likely to incur relatively high cell traffic. The “floating” buffer is then appended to the output link prior to launching the corresponding user’s traffic. Experiments confirm logical thinking that an increase in the size of the “floating” buffer should result in a superior efficiency for PDOBR. Further analysis reveals that a combination of faster technology, FAST Schottky TTL, and a threshold setting of 70 Mb/s yields a very high throughput of 85.05% and low cell drop rate of 14.95%. However, the highest performance is achieved – namely a high throughput of 91.56% coupled with a low cell drop rate of 8.44%, when the “floating” buffer size is increased by 18.98%, the difference, Δ L 2, in the absolute cell drop rates resulting from 70 Mb/s and 100 Mb/s threshold scenarios, and the threshold is set at 70 Mb/s.

A Parallel Dynamically Reconfigurable Architecture Designed for Flexible Application-Tailored Hardware/Software Systems in Future Mobile Communication

The evolving of current and future broadband access techniques into the wireless domain introduces new and flexible network architectures with difficult and interesting challenges. The system designers are faced with a challenging set of problems that stem from access mechanisms, energy conservation, error rate, transmission speed characteristics of the wireless links and mobility aspects. This paper presents first the major challenges in realizing flexible microelectronic system solutions for future mobile communication applications. Based thereupon, the architecture design of flexible system-on-chip solutions in the digital baseband processing for future mobile radio devices is discussed. The focus of the paper is the introduction of a new parallel and dynamically reconfigurable hardware architecture tailored to this application area. Its performance issues and potential are discussed by the implementation of a flexible and computation-intensive component of future mobile terminals.

Low Power Despreader using Dynamic Reconfigurable Architecture for Multicarrier CDMA with Two-Dimensional Spreading and Variable Spreading Factor

In this paper, we propose a dynamic reconfigurable architecture of a despreader for Multicarrier code division multiple access (CDMA) with two-dimensional spreading and variable spreading factor. The spreading factors in the time and frequency domains are varied according to cell configuration, channel load, and propagation channel conditions in the system. The structure of the proposed despreader is dynamically changed with spreading factors. Following this structure, optimum parallel and pipeline processing are achieved. The proposed despreader reduces the power consumption by 60% compared with the basic one.