Dynamic Random Access Memory Capacitors Research Articles

Enhanced Oxidation Resistance and Interface Stability of Atomic-Layer-Deposited MoNx Electrodes via TiN Passivation for DRAM Cell Capacitor Applications.

The continuous miniaturization of dynamic random-access memory (DRAM) capacitors has amplified the demand for electrode materials featuring specific characteristics, such as low resistivity, high work function, chemical stability, excellent interface quality with high-k dielectrics, and superior mechanical properties. In this study, molybdenum nitride (MoNx) films were deposited using a plasma-enhanced atomic layer deposition (PEALD) employing bis(isopropylcyclopentadienyl)molybdenum(IV) dihydride and NH3 plasma for DRAM capacitor electrode applications. Depending on the deposition temperatures of the PEALD MoNx films ranging from 200 to 400 °C, the Mo/N ratio and crystal structure varied, transitioning from the cubic NaCl-B1-type MoN phase with Mo/N ratio of 1.4 to the cubic γ-Mo2N phase with Mo/N ratio of 1.9. Notably, MoNx films grown at 400 °C exhibited low resistivity (435 μΩ·cm), a high work function (5.28 eV), and superior mechanical hardness (11.3 GPa) compared to ALD TiN films. Despite these excellent properties, the PEALD MoNx electrode demonstrated insufficient chemical stability, particularly in terms of oxidation resistance and interface quality with ALD HfxZr1-xO2 (HZO) films. This resulted in poor morphology and the formation of significant oxygen-deficient HZO layers (such as HfO2-x), leading to considerable degradation in the electrical performance of metal-insulator-metal (MIM) capacitors. To mitigate this issue, a thin (2.5-14 nm) ALD TiN layer was introduced as a passivation layer between the MoNx bottom electrode and HZO dielectric. The TiN-passivated MoNx (TiN/MoNx) electrode showed substantially enhanced oxidation resistance and reduced interfacial reactions with the HZO dielectric. Consequently, MIM capacitors with TiN/MoNx bottom electrodes demonstrated outstanding electrical performance, including excellent dielectric properties, low leakage current density, and high mechanical strength. Hence, this study proposes a promising candidates for storage nodes in the next-generation DRAM capacitors.

Interfacial layer suppression in ZrO2/TiN stack structured capacitors via atomic layer deposition

Controlling the formation of interfacial layers in dynamic random-access memory (DRAM) capacitors is crucial because it affects electrical performance, such as increasing the equivalent oxide thickness. This study investigates the formation of an interfacial layer during atomic layer deposition (ALD) of ZrO2 on TiN electrodes and examines its influence on electrical properties. Utilizing O3 and H2O as oxygen sources, we quantitatively identified notable differences in the formation of the interfacial TiOx layer. Using O3 results in a thicker TiOx layer with fewer impurities, which lowers the leakage current, whereas H2O creates a thinner interfacial layer with higher impurity levels, leading to an increased leakage current. To optimize these effects, we developed a two-step ALD process that combines both oxygen sources, reducing the interfacial layer thickness while maintaining low leakage currents. This approach significantly improved the electrical performance of capacitors. Furthermore, similar results were observed for HfO2/TiN systems, suggesting that our findings are broadly applicable to high-k dielectric materials.

Stabilization of Morphotropic Phase Boundary in Hafnia via Microwave Low‐Temperature Crystallization Process for Next‐Generation Dynamic Random Access Memory Technology

The morphotropic phase boundary (MPB), which arises from the combination of antiferroelectric and ferroelectric phases, demonstrates the highest dielectric constant (κ) compared to other phases. This emphasizes its potential as a leading contender for dielectric films in future dynamic random access memory (DRAM) capacitors. MPB‐based high‐κ materials using hafnia have shown a trade‐off between equivalent oxide thickness (EOT) and leakage current density (Jleak) when the crystallization temperature increases with scaling the thickness. Herein, a microwave annealing (MWA) method that can achieve low‐temperature crystallization below 350 °C is employed. The purpose of this method is to mitigate the trade‐off relationships and achieve the strict criteria of current DRAM capacitors. These criteria include low EOT (less than 4 Å) and Jleak (less than 10−7 A cm−2 at 0.8 V) characteristics. The MWA is capable of relatively low‐temperature annealing by supplying energy to the films through both thermal energy and dipole vibration energy. As a result, a record‐low EOT of 3.76 Å and a low leakage current characteristic of 4.2 × 10−8 A cm−2 at 0.8 V are achieved concurrently. It is confident that the research can be important in addressing the challenges associated with reducing the size of next‐generation DRAM capacitors.

Low temperature crystallization of atomic-layer-deposited SrTiO3 films with an extremely low equivalent oxide thickness of sub-0.4 nm

Despite SrTiO3(STO) possessing a high dielectric constant, its application as a capacitor dielectric in dynamic random-access memory(DRAM) capacitors faces challenges due to the high-temperature annealing for crystallization, its compositional inhomogeneity, and the high leakage currents of STO films. To address these issues, we employ atomic layer deposition(ALD) of STO films onto Pt substrates at elevated temperatures(340–380 °C). The use of low-reactivity Pt electrodes effectively mitigates the initial growth of excess Sr, ensuring enhanced compositional uniformity along the film growth direction. Coupled with ALD at high temperatures, this approach facilitates the crystallization of STO films in the as-grown state, further enhancing the crystallinity with increasing film thickness. Subsequent low-temperature post-deposition annealing (PDA) at 400 and 500 °C achieves full crystallization. This process results in a remarkable increase in the dielectric constant, reaching approximately 150. Furthermore, the absence of microcracks after PDA, attributed to the formation of adequately dense films, contributes to substantially improved dielectric properties. Consequently, these STO films exhibit an exceptionally low equivalent oxide thickness of 0.34 nm coupled with an ultralow leakage current of 3.7 × 10−8 A/cm2 at an operation voltage of 0.8 V, promising for advancing DRAM capacitors. This study presents a pathway for the sustainable scaling of DRAMs, addressing challenges in ALD-grown STO films.

Growth of Atomic layer-deposited Monoclinic Molybdenum Dioxide Films Stabilized by Tin Oxide Doping for DRAM Capacitor Electrode Applications.

Dynamic random-access memory (DRAM) capacitor electrodes, exemplified by TiN, face performance limitations owing to their relatively low work functions in addition to the formation of a low-k interfacial layer caused by their insufficient chemical stability. With recent advances in device scaling, these issues have become increasingly problematic, prompting the exploration of alternative electrode materials to replace TiN. Molybdenum dioxide (MoO2) has emerged as a promising candidate for this application, outperforming TiN due to its low resistivity, high work function (>5 eV), and excellent chemical stability. Moreover, monoclinic MoO2 exhibits a distorted rutile structure, enabling the in situ growth of high-k rutile TiO2 on MoO2 at low deposition temperatures. However, MoO2 deposition poses challenges because of its metastable nature compared to the more stable molybdenum oxide (MoOx) phases, such as MoO3 and Mo4O11. In this work, we successfully fabricated Sn-doped MoOx (TMO) films by atomic layer deposition (ALD) at 300 °C. A stabilized monoclinic MoO2 phase was achieved using ALD by incorporating SnOx into MoOx on both SiO2 and TiN substrates. The ALD TMO process comprised MoOx and SnOx subcycles, and the MoOx:SnOx subcycle ratio was varied from 100:1 to 20:1. High growth rates ranging from 0.19 to 0.34 nm/cycle were achieved for ALD TMO with varying the MoOx:SnOx subcycle ratio from 20:1 to 100:0. After post-deposition annealing at 500 °C, polycrystalline TMO films were obtained with smooth surface morphology. ALD TMO exhibited excellent interface quality with ALD TiO2, possessing a negligible low-k interfacial layer. Moreover, a rutile TiO2 film with a high dielectric constant of 136 was successfully grown on a 20% Sn-TMO electrode. Overall, this study provides a strategy to stabilize metastable MoO2 films using ALD, and it demonstrates the superiority of ALD TMO as a promising DRAM capacitor electrode material.

Phase-controlled molybdenum dioxide electrodes by RF reactive magnetron sputtering for achieving high-k rutile TiO2 dielectric

Molybdenum dioxide (MoO2) has recently garnered attention as a promising oxide electrode for next-generation dynamic random-access memory capacitors owing to its high work function, low resistivity, and good thermal stability. The formation of pure, reliable MoO2 films is a significant challenge because of their higher formation energy than that of non-conductive orthorhombic molybdenum trioxide (MoO3). Herein, we investigated the controlled growth of MoO2 films by manipulating the process pressure and oxygen-to-argon (O2/Ar) ratio using radio frequency reactive magnetron sputtering. By increasing the O2/Ar ratio at a fixed process pressure (pp), sputtered MoOx films were fabricated as metallic Mo, monoclinic MoO2, and orthorhombic MoO3. The MoO2 film with Mo/O atomic ratio of 0.5 was achieved in the narrow process window of O2/Ar ratio of 0.22 and pp = 3 mtorr. The MoO2 films exhibited a smooth surface morphology with a root mean square roughness of 0.34–0.68 nm. The resistivity of MoO2 film was 972 μΩ cm, which was decreased to 374–524 μΩ cm by rapid thermal annealing in N2 at 600 °C-800 °C. The phase-controlled MoO2 electrode led to the in-situ crystallization of high-k rutile TiO2 with a dielectric constant of 93 via local epitaxial growth. This might be attributed to the excellent coherence in the atomic arrangement and low lattice mismatch between the distorted rutile MoO2 (011) and rutile TiO2 (110) planes.

Synthesis of highly conformal titanium nitride films via tert-butyl chloride-assisted atomic layer deposition

Integrating the desired properties of dynamic random-access memory (DRAM) capacitors is challenging owing to the continuous downscaling of semiconductor devices. In this paper, we propose inhibitor (tert-butyl chloride, t-BCl)-assisted atomic layer deposition (IA ALD) as a technique for obtaining a highly conformal titanium nitride (TiN) film for DRAM capacitor electrodes. IA ALD relies on an ABC-type ALD cycle, where a t-BCl precursor and reactants are sequentially applied in numerous cycles during the film growth process. The t-BCl molecules function as a medium to prevent excess TiN film deposition at the capacitor hole entrance by controlling the surface reactivity of the precursors and the modulation of the growth per cycle (GPC). The results indicated that the step coverage (>99%) of the TiN film deposited on a substrate with an aspect ratio (ratio of height to width) of 20:1 was significantly increased, while the electrical and intrinsic properties of the TiN film remained unaffected. As the t-BCl feeding rate increased from 25 to 100 sccm, the GPC decreased from 0.352 to 0.146 Å, while the film resistivity remained unaffected. X-ray photoelectron spectroscopy confirmed that there was no change in the composition of the TiN film. In addition, secondary ion mass spectroscopy analysis confirmed that t-BCl did not contain C components and that the amount of Cl impurities decreased. Furthermore, density functional theory simulations, which were performed to study the IA ALD process mechanism, suggested that the film growth rate was reduced because the physisorption of t-BCl molecules partially blocked the reactive adsorption sites for the TiCl4 precursor.

Implementation of rutile-TiO2 thin films on TiN without post-annealing through introduction of SnO2 and its improved electrical properties

Rutile-TiO2 has been actively studied as a high-k candidate for next-generation dynamic random-access memory (DRAM) capacitors due to its higher dielectric constant compared to commercially used ZrO2 and HfO2 based dielectrics. However, because the thermodynamic stabilization temperature of rutile-TiO2 is above 750 °C, which is not acceptable for the DRAM process, noble metal-based functional electrodes, such as RuO2 have been indispensably used for the formation of rutile-TiO2 thin films. The proposed method suggests the strategic introduction of Sn to reliably achieve mass production of rutile-TiO2 thin film on TiN electrodes. However, the atomic layer deposition (ALD) process with a commercially employed Sn precursor had issues such as requiring additional thermal process for crystallization due to low process temperature or generating a reducing by-product. Therefore, in this study, we realized rutile-TiO2 thin films on TiN electrodes without an additional post-thermal process using a new Sn precursor capable of high-temperature deposition. By employing an optimized Sn-doped TiO2 on seed layer, it was possible to implement a high dielectric constant of over 100, and the leakage current improvement effect was also confirmed. Therefore, the process presented in this study suggests a direction for future high-k research on next-generation DRAM capacitors.

Low-Power Single Bitline Load Sense Amplifier for DRAM

With the significant growth in modern computing systems, dynamic random access memory (DRAM) has become a power/performance/energy bottleneck in data-intensive applications. Both the power management mechanism and downscaling method face decreasing performance or difficulties in the smaller footprint of the DRAM capacitor. Since optimizing the circuit of sense amplifier (SA) is an efficient method to reduce energy consumption, we propose two single bitline load sense amplifier (SBLSA) circuits, i.e., a redundant voltage discharged SBLSA (RVD-SBLSA) circuit and a bit aware SBLSA (BA-SBLSA) circuit, to improve conventional and single bitline write (SBW) circuits. The RVD-SBLSA circuit utilizes a clamp diode to discharge redundant voltage over VDD/2 with an additional working stage. The BA-SBLSA circuit abandons the single bitline load (SBL) circuit during read and write ‘1’ operations. The RVD-SBLSA circuit can offer the lowest total energy consumption, and the BA-SBLSA circuit can make a better balance between energy consumption and latency. Through the simulation results, the proposed circuits can efficiently reduce energy consumption or balance energy consumption and latency and show huge potentials in very large-scale integrated circuits.

High-κ Hf0.3Zr0.7O2 film with morphotropic phase boundary for DRAM capacitor by controlling H2O dose

For the miniaturization of dynamic random-access memory (DRAM), it is necessary to obtain low equivalent oxide thickness (EOT) and low leakage capacitor materials with complementary metal-oxide semiconductor (CMOS) process compatibility. Herein, we explore the influence of the dose of H2O reactants on the phase structure and electrical characteristics of Hf0.3Zr0.7O2 (HZO) thin films during the atomic layer deposition (ALD). By controlling the H2O dose as well as other conditions including inserting alumina, adjusting annealing temperature and electric field cycling, a high dielectric constant of ∼45 (EOT ∼ 0.54 nm) and low leakage current density (<7.7 × 10−8 A/cm2 at ±0.5 V) are achieved in the TiN/Al2O3 (∼0.3 nm)/Hf0.3Zr0.7O2 (∼6 nm)/TiN capacitor near the morphotropic phase boundary (MPB). Furthermore, the dielectric constant remains above 40 with endurance >1012 cycles (even extrapolated to 1015 cycles under voltage pulse of 0.5 V @10 MHz) at both room temperature and 85 °C. These results are helpful for achieving a high dielectric constant and low leakage for future generation DRAM capacitor materials.

5.1 Å EOT and low leakage TiN/Al2O3/Hf0.5Zr0.5O2/Al2O3/TiN heterostructure for DRAM capacitor

Further scaling of dynamic random-access memory (DRAM) faces critical challenges because of the lack of materials with both high dielectric constant and low leakage. In this work, engineering Hf1−xZrxO2 (HZO) films to the morphotropic phase boundary (MPB) and inserting Al2O3 interface layers with a wide bandgap are utilized to overcome this bottleneck. By tuning Zr composition and the woken-up process, the ratio of tetragonal and orthorhombic phases is manipulated to achieve the desired high dielectric constant MPB state. On this basis, Al2O3 ultrathin layers are inserted to further enhance the dielectric constant as well as reduce the leakage current. As a result, a high dielectric constant of ∼ 46.7 (equivalent oxide thickness ∼ 5.1 Å) and low leakage current density (&amp;lt;10−7 A/cm2 at ±0.5 V) are achieved in TiN/Al2O3 (0.2 nm)/Hf0.5Zr0.5O2 (5.6 nm)/Al2O3 (0.3 nm)/TiN capacitors. Furthermore, long dielectric breakdown time of the heterostructure confirms its application potential. These results are useful for developing next generation DRAM capacitor devices.

Investigation and passivation of boron and hydrogen impurities in tetragonal ZrO2 dielectrics for dynamic random access memory capacitors

Tetragonal ZrO2 high-k material as the dielectric layer of dynamic random access memory (DRAM) capacitors faces bulk defect related leakage current, which is one of the main obstacles to the down-scaling of DRAM devices. Boron and hydrogen impurities are known to be responsible for leakage current degradation and are hard to be removed in DRAM capacitors. However, the defect origins of boron and hydrogen leakage current are still puzzling, and corresponding suppression methods are urged. In this work, the properties of boron and hydrogen impurities in tetragonal ZrO2 are investigated using first-principles calculations, and defect types such as boron and hydrogen interstitials are discovered to have detrimental defect levels related to leakage current. Based on the discovery, a chlorine co-doping approach that can passivate detrimental defects by forming defect complexes is further proposed. By introducing level repulsion due to coupling between defect states, defect levels of passivated defect complexes are moved out of the region of leakage current contribution. Thus, bulk defect related leakage current in tetragonal ZrO2 based DRAM capacitors can be effectively suppressed without device structure modification, and a broad vista is opened for next-generation DRAM devices.

In Quest of Low‐Leakage Dynamic Random Access Memory Enabled by Doped TiO2 Dielectrics

AbstractHigh permittivity rutile TiO2 has been regarded as a promising candidate for the capacitor dielectric in ultra‐scaled dynamic random access memory (DRAM), but its low band gap and low interfacial Schottky barrier cause the bothering leakage current problem. It is in principle possible to tune the electrode Fermi level to the mid‐gap of TiO2 for leakage current reduction. In this work, the generalized gradient approximation (GGA)‐1/2 method is shown as a viable first‐principles approach to predict the Schottky barriers of TiO2 based capacitors. Through RuO2/TiO2/RuO2 and IrO2/TiO2/IrO2 full capacitor calculations, the impact of trivalent cation dopants (Al, Ga, La, and Y) on the Schottky barrier tuning is systematically studied. Among the four dopants, it is discovered that Y doping is most effective in hindering the formation of oxygen vacancies by analyzing formation energy and crystal orbital Hamilton population. Y‐doped rutile TiO2 is a promising material for next‐generation high capacitance and low leakage DRAM capacitors.

Study of Metal–Dielectric Interface for Improving Electrical Properties and Reliability of DRAM Capacitor

AbstractThe interface between a dielectric thin film and a metal electrode is studied to improve reliability as well as electrical properties of the metal–insulator–metal (MIM) capacitor in dynamic random‐access memory (DRAM) devices. The interfacial layers between a dielectric thin film and a metal electrode play important functional roles such as increasing the electrical barrier or preventing oxygen defects in high‐k dielectrics. By introducing an electrical barrier layer or a sacrificial layer at the metal–dielectric interface for engineering the electronic band, lattice, or dipole, various effects could be confirmed such as the conduction band offset (CBO), bandgap or mismatch modulation for controlling the dielectric loss depending on the AC frequency or leakage current of MIM capacitors. Upon the insertion of Al2O3 as an electrical barrier layer, CBO increased because of the band engineering. Further, upon the insertion of TiO2 as a sacrificial layer at the interface, CBO increased because of the dipole formation at the interface, attributed to the difference in electronegativity. Thus, a robust MIM capacitor for DRAM that maintains a low leakage current and has improved reliability which is realized using the proper combination of interfacial layers.

Equivalent oxide thickness scalability of Zr-rich ZrHfO2 thin films by Al-doping

With ultra-miniaturization of dynamic random-access memory (DRAM), it is very important to achieve equivalent-oxide-thickness (EOT) scaling of capacitors using materials applied to mass production. Compared to ZrO2, Zr1-xHfxO2 has a high possibility of improved electrical properties by doping in wide composition ranges. Therefore, we investigated the effect of Al-doping on electrical properties of Zr-rich Zr1-xHfxO2 thin films. Up to Al-doping of 2.1%, the leakage current was significantly improved without degradation of the dielectric constant, and it was possible to reduce the EOT by 0.12 nm in the leakage current specification applicable to DRAM capacitors.

The Contrasting Impacts of the Al2O3 and Y2O3 Insertion Layers on the Crystallization of ZrO2 Films for Dynamic Random Access Memory Capacitors

AbstractThis study examines the influences of the Al2O3 and Y2O3 insertion layers (ILs) on the structural and electrical features of ZrO2 thin films for their application to dynamic random access memory capacitors. The ultra‐thin Al2O3 IL (0.1–0.2 nm) dissolves into the ZrO2 layers, which causes the top and bottom portions of the ZrO2 film to merge and have smaller lattice parameters. However, the thicker Al2O3 IL (&gt;≈0.4 nm) forms a continuous layer and separates the top and bottom portions of the ZrO2 film. Interestingly, the diffusion of Al does not occur in this case. Overall, the dielectric constant (κ) of the ZrO2/Al2O3/ZrO2 film is lower than that of the undoped ZrO2 film due to the involvement of the low‐κ Al2O3 IL. In contrast, the Y2O3 IL does not interfere with the grain growth of ZrO2, rendering the continuous ZrO2 grain formation throughout the entire film thickness despite the presence of the continuous region with a higher Y‐concentration. The most crucial finding is that the Y‐doping significantly decreases the leakage current without sacrificing the dielectric constant. This leakage current decrease can be ascribed to the p‐type doping effect of Y ions in the n‐type ZrO2.

2.45 e-RMS Low-Random-Noise, 598.5 mW Low-Power, and 1.2 kfps High-Speed 2-Mp Global Shutter CMOS Image Sensor With Pixel-Level ADC and Memory

This article presents a low random noise, a low-power, and a high-speed 2-mega pixels (Mp) global-shutter (GS)-type CMOS image sensor (CIS) using an advanced dynamic random access memory (DRAM) technology. GS CIS is one of the alternatives to solve image distortion issues caused by a conventional rolling-shutter (RS) CIS operation, since a 2-D image data can be simultaneously sampled by the in-pixel analog memory. To achieve a high-performance GS CIS, we proposed a novel architecture for digital pixel sensor (DPS) which is a high-speed GS operation CIS with a pixel-wise analog-to-digital converter (ADC) and an in-pixel digital memory. The major technologies of the proposed DPS can be summarized as follows: 1) two large coupling capacitors with mature DRAM technology; 2) extremely narrow pitch Cu-to-Cu (C2C) bond; and 3) finally low-powered ADC with a near sub-threshold operation. A perfect auto-zero operation for ADC is implemented using two DRAM capacitors, and a large number of transistors have to be integrated in the single pixel for realizing pixel-level ADC. Thus, each pixel has two fine-pitch C2C interconnections. This makes it possible to realize wafer-level stacked unit pixel. The proposed DPS with low-power consuming analog circuits has been successfully designed and developed for extremely fast-readout speed of max. 1200 frames per second (fps) and high sensitivity for low-illumination conditions.

Modelling the Atomic Layer Deposition of Cobalt and Ruthenium on NHx-Terminated Metal Surfaces

Atomic layer deposition (ALD) is widely used in microelectronics and semiconductor industry to deposit very thin films as part of device fabrication in nano- or subnano-dimensions. The key advantages of ALD are the conformality and precise thickness control at the atomic scale, which are difficult for physical or traditional chemical vapor deposition methods. Cobalt (Co) and Ruthenium (Ru) are used as a seed layers for metallization of interconnects. They are also potential materials for the electrode in dynamic random-access memory (DRAM) capacitors and metal-oxide-semiconductor field-effect transistors (MOSFETs). Plasma-enhanced ALD (PE-ALD) is used for low-temperature thin film growth by alternating exposures of metal precursors and plasma reactants. During the PE-ALD growth of metals, N-plasma, for example, NH3 or a mixture of N2 and H2, has been applied to avoid surface metal oxidation. The PE-ALD of Ru and Co has been experimentally investigated using metal precursors such as RuCp2, Ru(EtCp)2, CoCp2, and CoCp(CO)2. However, the reaction mechanism is not clear and theoretical studies on the reaction mechanism is entirely lacking.In this presentation, we study the PE-ALD growth of Co and Ru by first principle calculations. The (001) surface of both metals, with a hexagonal structure, is the most stable and the (100) surface with a zigzag structure is less stable but has high reactivity. These two surfaces allow the study of the influence of the surface facet. The surface saturation coverage was studied by considering individual adsorption and co-adsorption of NH and NH2 to terminate both surfaces. On the (001) surface, the zero K saturation coverage for NH is 1ML on Ru and 6/9ML on Co. For NH2, the saturation coverages are 6/9ML on Co and Ru surfaces. On the (100) surface, the saturation coverages are 2ML for NH on Ru and Co surfaces, 1.33 ML for NH2 on Ru, and 1ML for NH2 on Co surface. The higher saturation coverage on (100) surface is attributed to the unique trench structure, which provides more available surface sites than that of (001) surface. We also consider co-adsorption of NH and NH2 on (001) and (100) surfaces. The results are then analyzed with ab initio thermodynamics by calculating the Gibbs free energy. Both the ultra-high vacuum (UHV) condition and standard ALD operating condition are used to elucidate the effect of pressure and temperature on the termination of metal surfaces.The adsorption and reactions of metal precursors (CoCp2 and RuCp2) on NHx terminated metal surfaces were investigated with the inclusion of van der Waals corrections. Two possible adsorption structures, namely the precursor lying parallel and perpendicular to the NHx-terminated surfaces, were considered at zero K and ALD conditions. Possible reactions include: precursor adsorption, first hydrogen transfer, first Cp ligand dissociation, first Cp ligand desorption, second hydrogen transfer, and second Cp ligand desorption. The barrier for proton transfer was calculated using climbing image nudged elastic band (CI-NEB) method. Our results show that (100) surface has higher activity than (001) surface. In addition, the Cp ligand elimination of CoCp2 has lower barrier than RuCp2, regardless of surface facet. After the metal precursor pulse, the surface is terminated with MCp fragment or M atom depending on surface facet, where M is Ru or Co. The surface N atom and H atom can be eliminated during the following plasma step by forming NH3, N2 or H2. After a full cycle, the surface is an NHx-terminated metal surface and ready for the next cycle. This work will be important to reveal the mechanism and feasibility of atomic layer deposition of metals using N-plasma.

Improved Properties of the Atomic Layer Deposited Ru Electrode for Dynamic Random-Access Memory Capacitor Using Discrete Feeding Method.

Ruthenium (Ru) thin films deposited via atomic layer deposition (ALD) with a normal sequence and discrete feeding method (DFM) and their performance as a bottom electrode of dynamic random-access memory (DRAM) capacitors were compared. The DFM-ALD was performed by dividing the Ru feeding and purge steps of the conventional ALD process into four steps (shorter feeding time + purge time). The surface morphology of the Ru films was improved significantly with the DFM-ALD, and the preferred orientation of the Ru films was changed from relatively random to a <101>-oriented direction. Under the DFM-ALD condition, the higher susceptibility of oxygen atoms to the Ru electrode resulted in a higher proportion of the RuO2 formation on the Ru film surface during the subsequent TiO2 ALD process. This higher RuO2 portion leads to higher crystallinity of the local-epitaxially grown TiO2 films with a rutile phase. Such improvement also decreased the interfacial component of equivalent oxide thickness (EOTi) by ∼0.1 nm compared with the cases on sputtered Ru film, which showed an even smoother surface morphology. Consequently, the minimum EOT values when the Ru bottom electrodes deposited via DFM-ALD were adopted were 0.76 and 0.48 nm for TiO2 and Al-doped TiO2 films, respectively, while still satisfying the DRAM leakage current density specification (<10-7 A/cm2 at a capacitor voltage of 0.8 V).

Extending the resolution limits of nanoshape imprint lithography using molecular dynamics of polymer crosslinking

Emerging nanoscale applications in energy, electronics, optics, and medicine can exhibit enhanced performance by incorporating nanoshaped structures (nanoshape structures here are defined as shapes enabled by sharp corners with radius of curvature < 5 nm). Nanoshaped fabrication at high-throughput is well beyond the capabilities of advanced optical lithography. Although the highest-resolution e-beams and large-area e-beams have a resolution limit of 5 and 18 nm half-pitch lines or 20 nm half-pitch holes, respectively, their low throughput necessitates finding other fabrication techniques. By using nanoimprint lithography followed by metal-assisted chemical etching, diamond-like nanoshapes with ~3 nm radius corners and 100 nm half-pitch over large areas have been previously demonstrated to improve the nanowire capacitor performance (by ~90%). In future dynamic random-access memory (DRAM) nodes (with DRAM being an exemplar CMOS application), the implementation of nanowire capacitors scaled to <15 nm half-pitch is required. To scale nanoshape imprint lithography down to these half-pitch values, the previously established atomistic simulation framework indicates that the current imprint resist materials are unable to retain the nanoshape structures needed for DRAM capacitors. In this study, the previous simulation framework is extended to study improved shape retention by varying the resist formulations and by introducing novel bridge structures in nanoshape imprinting. This simulation study has demonstrated viable approaches to sub-10 nm nanoshaped imprinting with good shape retention, which are matched by experimental data.