Dynamic Processor Research Articles

MC-DPS:Scheduling of mixed-criticality system with dynamic processor speed

MC-DPS:Scheduling of mixed-criticality system with dynamic processor speed

THE EFFECTS OF COMPRESSOR PLUG-INS ON THE DYNAMIC RANGE IN MUSIC PRODUCTION

This study investigated the role of dynamic processors in audio processing and music production and the effects of different types of design on the audio signal. It has been tried to give information about the designs and parameters of dynamic processors. In order to create the sound sample analyzed within the scope of the study, a mono sample recording was taken from the virtual instrument plug-in. The sound sample taken from the bass guitar model was preferred in order to contain all the general envelope structure features of an audio signal. In this direction, the sound sample was chosen from the virtual instrument in order to keep it away from external factors during the recording stages and to make the work repeatable and developable. It is used as basic tools for dynamic processors to control and balance audio signals and create sensory effects. In this context, the effects of compressors in the dynamic processor class and their basic parameters and different design types on the audio signal are examined. Differences in tonal characteristics and dynamic changes of different compressor designs have been observed. In this context, the effects of FET, VCA, Vari-Mu, Optical and Digital compressor plug-ins on the audio signal were analyzed and the results were presented. These analyzes can provide guidance for the selection of different compressor designs for lecturers, students, and those interested in and working in the field of music technology. In future studies, the role of different music genres, instruments and recording conditions on the effects of compressor designs can be explored more deeply, and more comprehensive results can be reached by collecting experimental data and using machine learning techniques.

SimNet

While cycle-accurate simulators are essential tools for architecture research, design, and development, their practicality is limited by an extremely long time-to-solution for realistic applications under investigation. This work describes a concerted effort, where machine learning (ML) is used to accelerate microarchitecture simulation. First, an ML-based instruction latency prediction framework that accounts for both static instruction properties and dynamic processor states is constructed. Then, a GPU-accelerated parallel simulator is implemented based on the proposed instruction latency predictor, and its simulation accuracy and throughput are validated and evaluated against a state-of-the-art simulator. Leveraging modern GPUs, the ML-based simulator outperforms traditional CPU-based simulators significantly.

SimNet

While cycle-accurate simulators are essential tools for architecture research, design, and development, their practicality is limited by an extremely long time-to-solution for realistic applications under investigation. This work describes a concerted effort, where machine learning (ML) is used to accelerate microarchitecture simulation. First, an ML-based instruction latency prediction framework that accounts for both static instruction properties and dynamic processor states is constructed. Then, a GPU-accelerated parallel simulator is implemented based on the proposed instruction latency predictor, and its simulation accuracy and throughput are validated and evaluated against a state-of-the-art simulator. Leveraging modern GPUs, the ML-based simulator outperforms traditional CPU-based simulators significantly.

Assessing the Effectiveness of Generalized Likelihood Ratio Test Detector Schemes in Seismic Event Detection and the Avoidance of Nontarget Signals

ABSTRACT Cross-correlation techniques have played a long-standing and pivotal role in seismic event monitoring. However, the performance of correlation-based detectors is challenged by nuisance seismicity, or nontarget signals. Such detections are a problem when the mission is to automatically map events to the correct source region. Using aftershocks of the 2014 Mw 6.0 South Napa, California, earthquake, we demonstrate the effectiveness of utilizing a dynamic correlation processor framework in a generalized likelihood ratio test (GLRT) detector configuration to minimize nontarget detections. A GLRT maximizes a detection statistic with respect to one or more unknown parameters. In this case, the detection statistic is a template signal match against the waveform in a window sliding over a data stream, and the unknown parameter is an index variable indicating group membership of the template event or events. Detected events are assigned to the event group that yields the largest detection statistic. Our results show that a GLRT detector will outperform a suite of independently operating correlation and subspace detectors in terms of having a lower nontarget detection rate at a given missed detection rate. We also show that a GLRT detector composed of a few high-rank subspace detectors has a slightly higher nontarget detection rate, but a significantly lower missed detection rate, than a GLRT detector composed of many low-rank subspace detectors. The high-rank GLRT configuration produced impressive results even with marginal data (single channel, single station, and very low time bandwidth product), which bodes well for the utility of building efficient aftershock classification systems and global monitoring systems at larger scales. However, future work is required to assess performance at the regional scale and to assess the performance of the system at detecting target events not used in the detector template creation.

An Economic and Non-cooperative Load-balancing Framework among Federated Cloudlets

Edge computing servers like cloudlets from different service providers compensate scarce computational and storage resources of mobile devices, are distributed across access networks. However, the dynamically varying computational requirements of associated mobile devices make cloudlets either overloaded or under-loaded. Hence, load-balancing among neighboring cloudlets appears to be an essential research problem. Especially, the load-balancing problem among federated cloudlets from the same as well as different service providers for low-latency applications needs significant attention. Thus, in this paper, we propose a load-balancing framework among federated cloudlets for low-latency applications that focuses on latency bound rather than latency minimization. In this framework, we employ dynamic processor slicing for internal handling of job requests from heterogeneous classes by the cloudlets. We propose a continuous-action reinforcement learning automata-based algorithm that enables cloudlets to independently compute the load-balancing strategies against their neighboring cloudlets in a software-defined networking enabled distributed network setting without any exhaustive control message exchange. To capture the economic interaction among federated cloudlets, we model this load-balancing problem as an economic and non-cooperative game and by scaffolding the properties of the game formulation, we achieve faster convergence of the reinforcement learning automata. Furthermore, through extensive simulations, we study the impacts of exploration and exploitation on learning accuracy.

Concerto: Dynamic Processor Scaling for Distributed Data Systems with Replication

A surge of interest in data-intensive computing has led to a drastic increase in the demand for data centers. Given this growing popularity, data centers are becoming a primary contributor to the increased consumption of energy worldwide. To mitigate this problem, this paper revisits DVFS (Dynamic Voltage Frequency Scaling), a well-known technique to reduce the energy usage of processors, from the viewpoint of distributed systems. Distributed data systems typically adopt a replication facility to provide high availability and short latency. In this type of architecture, the replicas are maintained in an asynchronous manner, while the master synchronously operates via user requests. Based on this relaxation constraint of replica, we present a novel DVFS technique called Concerto, which intentionally scales down the frequency of processors operating for the replicas. This mechanism can achieve considerable energy savings without an increase in the user-perceived latency. We implemented Concerto on Redis 6.0.1, a commercial-level distributed key-value store, demonstrating that all associated performance issues were resolved. To prevent a delay in read queries assigned to the replicas, we offload the independent part of the read operation to the fast-running thread. We also empirically demonstrate that the decreased performance of the replica does not cause an increase of the replication lag because the inherent load unbalance between the master and replica hides the increased latency of the replica. Performance evaluations with micro and real-world benchmarks show that Redis saves 32% on average and up to 51% of energy with Concerto under various workloads, with minor performance losses in the replicas. Despite numerous studies of the energy saving in data centers, to the best of our best knowledge, Concerto is the first approach that considers clock-speed scaling at the aggregate level, exploiting heterogeneous performance constraints across data nodes.

CNN Technology-Tools and Applications

Cellular neural/nonlinear networks were invented almost 30 years ago. The CNN research led to high performance computational architectures, neuromorphic modells of the visual and auditory pathways, stability results for arrays of coupled dynamic processors, and for practical image processing results. The main stages of the research and the results are summarized in this paper.

I Could Have Been a Bushman: A Brief Reflection on Bronfenbrenner's Ecological Theory on Child Development

Adopting a contextual worldview of children as dynamic processors of environmental input, Bronfenbrenner adopted elements from mechanistic models viewing change as continual and as resulting primarily from outside influences. Integrating this model with the organismic model’s perspective of the developmental process as active under the influence of internal forces, Bronfenbrenner’s scheme is a contextual view of child development.

Architecture of ASIP Crypto-Processor for Dynamic Runtime Security Applications

<p>Nowadays, demands of data security are increasing, especially after introduction of wireless communications to the masses. Cryptographic algorithms are mainly used to obtain confidentiality and integrity of data in communication. There are a variety of encryption algorithms have been developed. This paper provides quantitative analysis and comparison of some symmetric key cryptographic ciphers (DES, 3DES, AES, Blowfish, RC5, and RC6). The quantitative analysis approach is a step towards optimizing the security operations for an efficient next generation family of network processors with enhanced speed and power performance. A framework will be proposed as a reference model for quantitative analysis of security algorithm mathematical and logical operations. This paper also provides a dynamic crypto processor used for selected symmetric key cryptographic ciphers and provides an implementation of 16bit cryptographic processor that performs logical operations and arithmetic operations like rotate shift left, modular addition 2^16, S_box operation, and key expansion operation on spartan6 lower power, xc6slx150L-1lfgg676 FPGA. Simulation results show that developed processor working with high Speed, low power, and low delay time. </p>

Temperature-aware adaptive power management: An analytical approach for joint processor and cooling mode selection

This paper presents a temperature-aware adaptive power management policy for a Markovian single-processor system equipped with a cooling fan working under variable ambient temperature. The method tries to minimize the jitter of the system performance, subject to a given power consumption constraint. The adaptation is performed through simultaneous dynamic processor speed selection (to control power of the system processor) and dynamic fan mode selection (to control power of its cooling fan). First, we provide an analytical method for calculation of the system power consumption and performance under some processor and fan speed setups. All the inter-effects among the processor dynamic power, leakage power, temperature, and the system stochastic properties are taken into account in the calculations to reach more accurate analysis. Then, to adapt the system power consumption with respect to the variations of the ambient temperature, we have used a model predictive control (MPC) approach beside some optimizations based on the analysis to appropriately change the processor and fan speed setups. Simulation results show the efficacy of the proposed adaptive method with an emphasis on the preference of the considered backlog-dependent mode selection comparing to some traditional static mode selection methods.

Evolution of Dynamic Loads in Steel Spur Gears

The Complete study of Literature and reporting on how Spur gears are designed using steel-steel alloys and dynamic load is calculated for the spur gears. The analytical model is developed to simulate the load sharing characteristics through a mesh cycle. The model takes into account the main internal factors of dynamic load as time-varying mesh stiffness and composite tooth profile errors. Comparative different types of dynamic load processors study are included, which shows the different processors of the dynamic load. Pro E is an interactive CAD/CAM system, a fully 3-D double precession system that allows accurate description of almost any geometric shape. Pro E modeling provides capabilities to help the design engineer to perform conceptual and detailed deigns. It is a feature and constrained based solid modeler that allows users to create and edit complex solid models interactively. MSC Nastran is a powerful general purpose, Finite element analysis solution for small to complex assemblies. A standard tool, in the field of structural analysis for over four decades, Nastran provides a wide range of analysis capabilities including linear, static's, dynamic, displacement, strain, stress, vibration, heat transfer and more. Nastran can handle any material type from plastic and metal to composites and hyper elastic materials.

An Energy-Efficient Approach to Hot-Plugging of Embedded Multiprocessors

With the increasing of the number of processors in one chip, the energy consumption became increasingly important in the low power design of embedded system. In time-sharing OS, different application scenarios lead to different workload. A novel policy for energy saving is that some processors can be hot-plugged on while the workload of the system becomes high and some processors can be hot-plugged off while the workload becomes low. This paper proposed an energy-efficient workload prediction approach called PID prediction algorithm (PPA) which aims dynamic processors number changes for energy saving and reduces the frequency of processors switch on/off for saving extra energy costs. The experiments show that energy consumption is reduced by 19% and the frequency of processors switch on/off is reduced by 30%.

Dynamic power dissipation control method for real-time processors based on hardware multithreading

In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.

An event-driven power management scheme for mobile consumer electronics

Dynamic processor power management based on periodic monitoring of processor load is being widely used to enhance battery life of mobile consumer electronics. The existing power management schemes, however, often lead to poor user-perceived responsiveness, which is a crucial factor for the quality of user experiences, by making inadequate or delayed decisions on the processor performance level. This paper presents a novel event-driven scheme of the processor power management to guarantee high responsiveness while minimizing ineffective energy consumption. The proposed scheme exploits the characteristic of an interactive event, which is triggered by a user input instead of a periodic timer interrupt. The prototype of the proposed event-driven scheme is implemented for an application launch event as an example. In order to quantify user-perceived responsiveness and energy consumption simultaneously, this paper introduces a latency measurement benchmark program. In the evaluation with the benchmark, the proposed power management scheme showed comparable responsiveness with higher energy savings up to 20 % than the existing dynamic schemes when the interactive workload is mixed with a CPU-intensive background task.

Chameleon

The rise of multi-core processors has shifted performance efforts towards parallel programs. However, single-threaded code, whether from legacy programs or ones difficult to parallelize, remains important. Proposed asymmetric multicore processors statically dedicate hardware to improve sequential performance, but at the cost of reduced parallel performance. However, several proposed mechanisms provide the best-of-both-worlds by combining multiple cores into a single, more powerful processor for sequential code. For example, Core Fusion merges multiple cores to pool caches and functional units, and Intel's Turbo Boost raises the clock speed of a core if the other cores on a chip are powered down. These reconfiguration mechanisms have two important properties. First the set of available cores and their capabilities can vary over short time scales. Current operating systems are not designed for rapidly changing hardware: the existing hotplug mechanisms for reconfiguring processors require global operations and hundreds of milliseconds to complete. Second, configurations may be mutually exclusive: using power to speed one core means it cannot be used to speed another. Current schedulers cannot manage this requirement. We present Chameleon, an extension to Linux to support dynamic processors that can reconfigure their cores at runtime. Chameleon provides processor proxies to enable rapid reconfiguration, execution objects to abstract the processing capabilities of physical CPUs, and a cluster scheduler to balance the needs of sequential and parallel programs. In experiments that emulate a dynamic processor, we find that Chameleon can reconfigure processors 100,000 times faster than Linux and allows applications full access to hardware capabilities: sequential code runs at full speed on a powerful execution context, while parallel code runs on as many cores as possible.

Chameleon

The rise of multi-core processors has shifted performance efforts towards parallel programs. However, single-threaded code, whether from legacy programs or ones difficult to parallelize, remains important. Proposed asymmetric multicore processors statically dedicate hardware to improve sequential performance, but at the cost of reduced parallel performance. However, several proposed mechanisms provide the best-of-both-worlds by combining multiple cores into a single, more powerful processor for sequential code. For example, Core Fusion merges multiple cores to pool caches and functional units, and Intel's Turbo Boost raises the clock speed of a core if the other cores on a chip are powered down. These reconfiguration mechanisms have two important properties. First the set of available cores and their capabilities can vary over short time scales. Current operating systems are not designed for rapidly changing hardware: the existing hotplug mechanisms for reconfiguring processors require global operations and hundreds of milliseconds to complete. Second, configurations may be mutually exclusive: using power to speed one core means it cannot be used to speed another. Current schedulers cannot manage this requirement. We present Chameleon, an extension to Linux to support dynamic processors that can reconfigure their cores at runtime. Chameleon provides processor proxies to enable rapid reconfiguration, execution objects to abstract the processing capabilities of physical CPUs, and a cluster scheduler to balance the needs of sequential and parallel programs. In experiments that emulate a dynamic processor, we find that Chameleon can reconfigure processors 100,000 times faster than Linux and allows applications full access to hardware capabilities: sequential code runs at full speed on a powerful execution context, while parallel code runs on as many cores as possible.

A Study of Ferroelectric Properties of the Oscillator Model of PZT-22

The typical properties of ferroelectric films are applied in the construction of nonvolatile memory devices (for example, FeRAM), dynamic random access memory, capacitors, infrared receivers, optical processors, waveguide and delay-circuits (delay-lines), appliances of surface-acoustic waves, and various acoustic devices. The physical properties of the films depend on the state (condition) of the surface, stoichiometry, crystalline nature, thickness, microcrystalline nature, crystallographic orientation, and high processing (that is, methods of obtaining films) temperature [1]. The investigation of dielectric properties in millimeter and sub-millimeter spectral range often provides essential information about the dynamic properties of dielectrics [2]. In this letter, we conduct a brief study of the contemporary technologies of ferroelectric films and the experimental

Adapting to the times [review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008)

The focus of this volume is on postsilicon adaption to overcome process and environmental variations, to ensure that a design operates to specifications even in the presence of process and environmental variations. Some of the topics covered include: an introduction, discussing sources of variation and the notion of a control system with a feedback loop to adaptively compensate for variations; adaptively changing body biases, processor frequencies, and supply voltages to react to variations; an Intel view, demonstrated on the design of a TCP/IP processor with dynamic and adaptive supply voltage, body bias, and frequency optimization, including measurement results; building ultradynamic-voltage-scaled (UDVS) systems; the design of the XScale embedded processor; the design of sensors for monitoring critical-path delays under variations, including control and calibration mechanisms; architectural methods for adaptive computing; asynchronous systems and adaptation; and SRAM design and optimization and testing techniques specific to adaptive systems, as demonstrated on the Intel Montecito processor. The book brings together a variety of voices, explaining various views regarding on-chip adaptation. The overall story comes across extraordinarily well and lucidly.

Lakes and Forests as Determinants of Downstream Nutrient Concentrations in Small Mountain Watersheds

ABSTRACTLakes are dynamic processors of nutrients and may hold an active role in modifying the water chemistry of stream systems. In this study, we examine the influence of lakes and an important terrestrial component—forest cover—on the nutrient levels of stream water in 11 Rocky Mountain (Idaho) watersheds. Water samples were collected from the inflow and outflow of lakes with varying amounts of upstream lakes and forested area during spring runoff and summer base flow. During base flow, mean total nitrogen concentrations at the inflow of final lakes were significantly related to relative upstream lake area, increasing from 34 to 103 µg N L−1 as upstream lake cover in the watersheds increased from 0% to 4%. Forest cover was not significantly correlated with total nitrogen concentrations exported from the watersheds. However, similar to other studies, inflow nitrate concentrations were negatively correlated with relative forest cover. At the scale of individual lakes, dissolved organic carbon and dissolved organic nitrogen increased, and nitrate was significantly reduced from inflows to outflows. The results indicate a potentially critical role of mountain lakes in governing nitrogen flux downstream, and suggest the role of lakes as nitrogen sinks or sources may reverse between spring runoff and summer base flow.