Dynamic Power Supply Current Research Articles

Fault features analysis for soft faults of analog circuits with tolerance

Soft faults of analog circuits are more difficult to diagnose than hard faults because the soft faults are caused by the deviations of component parameters. Node voltages were traditionally used as the testing signals to diagnose analog circuits. With the rapid development of integrated circuits technology, fewer and fewer circuit nodes are accessible. Only the output voltage can be tested in many cases. This cries for other new accessible signal except for the traditional voltage signal. In this paper, the fault features of testing signal in both time-domain and frequency-domain are analysed. The output voltage was acquired firstly. Its fault features were extracted and used for fault diagnosis. The results show that the soft faults of Tow-Thomas filter cannot be uniquely located by using this output voltage only. Then a new accessible signal, which named dynamic power supply current, was acquired and its fault features were analysed. And the results were compared with those using output voltages. The comparing results show the validity of dynamic power supply current. This signal contains information related with the circuits’ topology and can be used for fault diagnosis of analog circuits.

Testing Analog Circuits by PCA of Power Supply Current

A method using principal component analysis (PCA) of dynamic power supply current was proposed for testing of analog circuits in this paper. The basic model of the proposed method and the general rule for analog fault detection were described in detail. At first, the principal component model of fault-free circuits was constructed. Then the circuits-under-test was compared with the principal component model to calculate the statistic for fault detection. The features of power supply current in both time and frequency domain were combined by PCA, and it could overcome the difficulty to determine threshold by empirical knowledge. The proposed method was applied to detect faults of the signal filtering and amplifying circuit, which is used in the ultrasonic liquid-level sensor. The results show that the power supply current contains information about the circuit’s faults, and can be used for fault detection of analog circuits by analyzing this signal.

Structural Test Approach for Embedded Analog Circuits Based on a Built-in Current Sensor

This paper presents a test method based on the analysis of the dynamic power supply current, both quiescent and transient, of the circuit under test. In an off-chip measurement, the global interconnect impedance associated with the chip package and the test equipment and, also, the chip input/output cells will complicate the extraction of the information provided by the current waveform of the circuit under test. Thus, the supply current is measured on-chip by a built-in current sensor integrated in the die itself. To avoid the effective reduction of the voltage supply, the measurement is performed in parallel by replicating the current that flows through selected branches of the analog circuit. With the aim of reducing the test equipment requirements, the built-in current sensor output generates digital level pulses whose width is related to the amplitude and duration of the circuit current transients. In this way the defective circuit is exposed by comparing the digital signature of the circuit under test with the expected one for the fault-free circuit. A fault evaluation has been carried out to check the efficiency of the proposed test method. It uses a fault model that considers catastrophic and parametric faults at transistor level. Two benchmark circuits have been fabricated to experimentally verify the defect detection by the built-in current sensor. One is an operational amplifier; the other is a structure of switched current cells that belongs to an analog-to-digital converter.

SRAM transparent testing methodology using dynamic power supply current

A new transparent testing methodology using dynamic power supply current is proposed which is much simpler than traditional transparent testing algorithms. It employs the dynamic power supply current instead of making signatures so that it does not need the extra steps and hardware to generate a signature. The paper describes how to convert a March algorithm to a transparent one and how to cover the fault models considered. The transformed algorithm is much simpler and test time can be greatly reduced. In addition, it can detect extra faults that the original algorithm cannot. The whole BIST architecture is described, together with a new peak current detector.

Signature analysis for fault detection of mixed-signal ICs based on dynamic power-supply current

In this paper we have investigated a unified and simultaneous fault detection method for mixed-signal integrated circuits. The method is based on the analysis of the power-supply current through the circuit under test. The analysis has been done paying attention to the dynamic behaviour of the power-supply current, in order to avoid measurement problems related to the large amount of quiescent current drop across many analog blocks. The analysis of the dynamic power-supply current entails certain problems related to the complexity of the measurement process, especially those due to the high speed of the current transients. These problems have been addressed by considering a design for test procedure based on the use of built-in dynamic current sensors. The goal of the design for test methodology proposed is to represent the Iddt through the mixed-signal IC under test by a digital signature. The paper presents some advantages of this approach such as a good tolerance to cross-talk noise and the need for only a conventional digital tester on the complete mixed-signal IC for fault detection. The analysis is illustrated with some test results.

Built‐in current testing for CMOS logic circuits using random patterns

AbstractWith respect to CMOS logic circuits, it is reported that a fault can occur cannot be covered by conventional classical fault model, and the current testing is considered to be interesting as a testing method to detect such a fault.This paper proposes a fault‐detection method for the CMOS logic circuit which can detect the stuck‐at fault and the stuck‐open fault based on the dynamic power supply current observed when a pseudorandom pattern is applied as the input. A built‐in testing circuit for realizing the principle is shown. The feature of the current testing is that the fault can be detected by observing the power supply current as long as the fault in the circuit is activated, and it is not required to propagate the fault information to the output. Based on that property, a random pattern with a small test generation cost is used as the test pattern.As the test pattern, the pseudorandom pattern is generated autonomously by utilizing the output signal of the circuit under test. The fault detection is made easier by this pattern generation since the effect of the fault on the power supply current is enhanced. In determining whether or not the power supply current is that of the normal circuit, a method based on the time‐course of the power supply current is used, with the power supply currents for various test patterns as the feature parameter. The proposed procedure is evaluated by a simulation, and the usefulness of the proposed method is demonstrated.

Testing of static random access memories by monitoring dynamic power supply current

This article presents a correlation between dynamic power supply current and pattern sensitive faults in SRAMs. It is shown that the dynamic power supply current provides a window for observing the internal switching behavior of the memory cells. Switching of the logic state of a memory cell results in a transient current pulse in the power supply rails. A new current-testable SRAM structure is presented which can be used to isolate normal current transients from those resulting from pattern sensitivity. The new structure differs from traditional SRAM structures only in the way that power is distributed to the cells. The new structure allows for very high coverages of disturb-type pattern sensitivity using a simple algorithm of length 5n where n is the number of cells.