Dynamic Partial Reconfiguration Systems Research Articles

Intelligent Optimization Approaches for a Secured Dynamic Partial Reconfigurable Architecture-Based Health Monitoring System

In this work, an intelligent multi-objective optimization technique is proposed to optimize various parameters such as power consumption ([Formula: see text]), computation time ([Formula: see text]) and area ([Formula: see text]) for a health monitoring system designed using the Secured Dynamic Partial Reconfiguration (SDPR) architecture. The cost-efficient Dynamic Partial Reconfiguration (DPR)-based field-programmable gate array (FPGA) is very useful for analyzing many applications such as automation and data processing. The novelty of this paper is to design a new intelligent SDPR (i-SDPR) module in order to achieve better performance in a health monitoring system by considering various performance parameters. The SDPR architecture is incorporated with two reconfigurable modules such as Encrypt and Authenticate, which results in an increase in the core power consumption ([Formula: see text]), computation time ([Formula: see text]) and area ([Formula: see text]). So, to improve the performance of the SDPR-based health monitoring system, there is a necessity to optimize the performance parameters and it is achieved through intelligent multi-objective evolutionary (MOEA) techniques. The intelligent multi-objective evolutionary techniques such as Niched-Pareto Genetic Algorithm (NPGA), Pareto Archived Evolution Strategy (PAES) and Pareto Envelope-based Selection Algorithm (PESA) have been considered for better optimization in the performance parameters. For the study, the free-to-use MIMIC-III dataset is taken, which contains critically admitted various intensive care unit patient data. The dataset is processed through any one of the multi-objective evolutionary operators till satisfying the conditions and then forwarded to implementation. The proposed architecture has been implemented and tested using Cyclone[Formula: see text] V SX SoC Development Kit. The comparative analysis of various performance parameters was done for the proposed i-SDPR with the existing techniques such as the DPR and SDPR approach to show the improvement. The results declare that the proposed techniques obtain better performance compared to the existing techniques.

Automatic and Simultaneous Floorplanning and Placement in Field-Programmable Gate Arrays With Dynamic Partial Reconfiguration Based on Genetic Algorithm

Using dynamic partial reconfiguration (DPR) feature in field-programmable gate array (FPGA) systems seems inevitable by considering the tremendous benefits, such as reduced cost and power. Nowadays, manual floorplanning is one of the difficulties in implementing DPR systems, which relies on the designer's views and his command over designing the concepts for arranging the modules on the physical layout of the FPGA more efficiently, as the results of floorplanning can influence the next stages, such as the placement. In other words, placement and floorplanning that are separately conducted in the today's tools are interdependent and the floorplanning results play a role in the placement and vice versa. This article aimed to propose a method for conducting floorplanning and placement simultaneously in DPR systems according to the genetic algorithm (GA). The proposed algorithm was tested on 20 largest MCNC benchmark circuits with DPR-support capability. Based on the results, wirelength and critical path delay improved by 14% and 17%, respectively, compared with Xilinx's early access partial reconfiguration design flow (EAPR). However, area and runtime increased by about 2% and 8%, respectively. The proposed method was also compared with other research that uses B* tree and simulated annealing algorithm. The results showed that our proposed algorithm is competitive in various parameters with other research.

A dynamic partial reconfigurable system with combined task allocation method to improve the reliability of FPGA

Currently most FPGAs use SRAM-based technology, which are susceptible to faults from external electromagnetic radiation or produced by long-time internal overload operation. The dynamic partial reconfigurable (DPR) system, as an emerging technology, provides a promising way to solve this problem by reallocating the tasks in damaged resource areas to non-faulty regions at runtime. Based on such idea, an infrastructure for coordinately executing specialized hardware tasks on a reconfigurable FPGA is presented to achieve the flexibility for tolerating the occurring faults at runtime. Moreover, a method named MER-3D-Contact that combines the maximum empty rectangles (MER) technique with the adjacency heuristic is proposed to allocate tasks in the dynamical partial reconfiguration system for higher resource utilization, higher task acceptance ratio and lower fragmentation ratio. At last, experiments are carried out to evaluate the performance of the proposed system, results show that the proposed system can make the highest improvement 36% without damaged areas and the highest improvement 58% with damaged resources in terms of task acceptance ratio. Thus, the proposed system is expected a wide application in the field of more reliable FPGAs.

An online fault injection method for the dynamic partial reconfiguration system based on a lightweight ICAP controller

An online fault injection method for the dynamic partial reconfiguration system based on a lightweight ICAP controller

Partial dynamic reconfiguration framework for FPGAs through remote access

With the advent of internet of things (IoT) and ubiquitous computing, the need for resource aware reconfiguration platform is increasing tremendously. Though a number of dynamic partial reconfiguration systems are available, they consume a significant portion of base system area in comparison with the application running on the system. Larger area requirements of reconfigurable platform cannot take the advantage of reconfigurable systems. Hence, a light weighted and flexible reconfigurable framework with remote access reconfiguration is proposed. The system occupied less than 1% of the total device resources and attained 400 MBps reconfiguration throughput. This framework can be used to any number of reconfiguration regions and is suitable for any application. The proposed framework for partial dynamic reconfiguration through remote access is tested on Virtex 5 XC5VFX70T and Virtex 6 XC6VLX240T FPGAs with 1 Gbps Ethernet link.

Partial dynamic reconfiguration framework for FPGAs through remote access

With the advent of internet of things (IoT) and ubiquitous computing, the need for resource aware reconfiguration platform is increasing tremendously. Though a number of dynamic partial reconfiguration systems are available, they consume a significant portion of base system area in comparison with the application running on the system. Larger area requirements of reconfigurable platform cannot take the advantage of reconfigurable systems. Hence, a light weighted and flexible reconfigurable framework with remote access reconfiguration is proposed. The system occupied less than 1% of the total device resources and attained 400 MBps reconfiguration throughput. This framework can be used to any number of reconfiguration regions and is suitable for any application. The proposed framework for partial dynamic reconfiguration through remote access is tested on Virtex 5 XC5VFX70T and Virtex 6 XC6VLX240T FPGAs with 1 Gbps Ethernet link.

AC_ICAP: A Flexible High Speed ICAP Controller

The Internal Configuration Access Port (ICAP) is the core component of any dynamic partial reconfigurable system implemented in Xilinx SRAM-based Field Programmable Gate Arrays (FPGAs). We developed a new high speed ICAP controller, named AC_ICAP, completely implemented in hardware. In addition to similar solutions to accelerate the management of partial bitstreams and frames, AC_ICAP also supports run-time reconfiguration of LUTs without requiring precomputed partial bitstreams. This last characteristic was possible by performing reverse engineering on the bitstream. Besides, we adapted this hardware-based solution to provide IP cores accessible from the MicroBlaze processor. To this end, the controller was extended and three versions were implemented to evaluate its performance when connected to Peripheral Local Bus (PLB), Fast Simplex Link (FSL), and AXI interfaces of the processor. In consequence, the controller can exploit the flexibility that the processor offers but taking advantage of the hardware speed-up. It was implemented in both Virtex-5 and Kintex7 FPGAs. Results of reconfiguration time showed that run-time reconfiguration of single LUTs in Virtex-5 devices was performed in less than 5 μs which implies a speed-up of more than 380x compared to the Xilinx XPS_HWICAP controller.

Supporting a wide variety of communication protocols using dynamic partial reconfiguration

Supporting a variety of communication protocols for test support equipment has typically required extensive hardware and Input/Output (I/O) interfaces targeting each protocol specifically. Recent advanced designs in the past ten years have created more dynamic approaches by using Field Programmable Gate Arrays (FPGA) and embedded hardware to implement or simulate previous hardware I/O designs. The dynamic possibilities of FPGA have been expanded with the introduction of Dynamic Partial Reconfiguration (DPR), which allows part of the FPGA to be reconfigured while the rest of the logic remains static. To determine whether this new technology was a viable option for test equipment, a DPR system was designed and implemented to interface with various communication protocols used in test equipment. The end result outlined some important advantages and disadvantages to consider when developing such a system.

Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption

Protecting the confidentiality and integrity of a configuration bitstream is essential for the dynamic partial reconfiguration (DPR) of field-programmable gate arrays (FPGAs). This is because erroneous or falsified bitstreams can cause fatal damage to FPGAs. In this paper, we present a high-speed and area-efficient bitstream protection scheme for DPR systems using the Advanced Encryption Standard with Galois/Counter Mode (AES-GCM), which is an authenticated encryption algorithm. Unlike many previous studies, our bitstream protection scheme also provides a mechanism for error recovery and tamper resistance against configuration block deletion, insertion, and disorder. The implementation and evaluation results show that our DPR scheme achieves a higher performance, in terms of speed and area, than previous methods.

A high-level methodology for automatically generating dynamic partially reconfigurable systems using IP-XACT and the UML MARTE profile

Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building complex systems remains a daunting task. Recently, approaches based on Model-Driven Engineering (MDE) and UML MARTE standard have emerged which aim to simplify the design of complex SoCs, and in some cases, DPR systems. Nevertheless, many of these approaches lacked a standard intermediate representation to pass from high-levels of descriptions to executable models. However, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. We present the MARTE modeling concepts and how these models are mapped to IP-XACT objects; the emphasis is given to the generation of IP cores that can be used in the Xilinx EDK (Embedded Design Kit) environment, since we aim to develop a complete flow around their Dynamic Partial Reconfiguration design flow. Finally, we present a case study integrating the presented concepts, showing the benefits in design efforts compared with a purely VHDL approach and using solely EDK. Experimental results show a reduction of the design efforts required to obtain the netlist required for the DPR design flow from hours required in VHDL and Xilinx EDK, to less the one hour and minutes for IP integration.

EuTOPIA: Facilitating Processor-Based DPR Systems for non-DPR Experts

Dynamic Partial Reconfiguration (DPR) allows the targeted FieldProgrammable Array (FPGA) to selectively update portions of the programmable logic while the remainder of the fabric stays active. Previously, designers were required to manually create DPR systems with minimal support from Computer Aided Design (CAD) tools. Xilinx ® ’s PlanAhead TM software now automates much of the DPR system generation process for ISE-based DPR systems. This paper presents EuTOPIA (EDK TO PlanAhead Implementation Automation), a CAD tool that extends the automation in Xilinx’s current DPR design flow to include microprocessor based designs. Given an architecture described in Xilinx’s Embedded Design Kit (EDK), EuTOPIA automates the process of converting it into a PlanAhead project for a DPR design. EuTOPIA abstracts the low level details of DPR implementation so that designers need only have nominal knowledge of the underlying process to create their initial DPR system. EuTOPIA is shown to reduce implementation time by a factor of 18 times over manual implementations by experienced designers, and can be further increased for novice designers. Over the design-cycle of a product where designers may generate tens or even hundreds of different implementations of their DPR design, these time savings could be extremely significant.

Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic

Dynamic partial reconfiguration (DPR) allows us to adapt hardware resources to meet time-varying requirements in power, resources, or performance. In this paper, we present two new DPR systems that allow for efficient implementations of 1D FIR filters on modern FPGA devices. To minimize the required partial reconfiguration region (PRR), both implementations are based on distributed arithmetic. For a smaller required PRR, the first system only allows changes to the filter coefficient values while keeping the rest of the architecture fixed. The second DPR system allows full FIR-filter reconfiguration while requiring a larger PR region. We investigate the proposed system performance in terms of the dynamic reconfiguration rates. At low reconfiguration rates, the DPR systems can maintain much higher throughputs. We also present an example that demonstrates that the system can maintain a throughput of 10 Mega-samples per second while fully reconfiguring about seventy times per second.