Dynamic Hot Carrier Research Articles

Gate Voltage Pulse Rising Edge Dependent Dynamic Hot Carrier Degradation in Poly-Si Thin-Film Transistors

Dynamic degradation becomes a critical issue for thin-film transistors (TFTs) used in emerging new displays driven by high frequency gate voltage ${V}_{\text {G}}$ pulses. In this study, ${V}_{\text {G}}$ pulse rising edge dependent dynamic hot carrier degradation of poly-Si TFTs is investigated. It is demonstrated that rising edge of ${V}_{\text {G}}$ pulses which swing within the OFF-state of TFTs causes the degradation, while that of normal ${V}_{\text {G}}$ pulses which switch between the ON and OFF states across the flat band voltage ${V}_{\text {FB}}$ of TFTs does not. Based on transient TCAD simulation, the underlying mechanism of rising edge dependent degradation is proposed, which is based on the non-equilibrium PN junction degradation model previously proposed to explain ${V}_{\text {G}}$ pulse falling edge dependent degradation of poly-Si TFTs. Hence, the dynamic degradation model of poly-Si TFTs related to both rising and falling edge of the ${V}_{\text {G}}$ pulses can be unified now, which is applicable to fast gate pulses with steep rising and/or falling edges in sub- $\mu \text{s}$ level.

Reversely-Synchronized-Stress-Induced Degradation in Polycrystalline Silicon Thin-Film Transistors and Its Suppression by a Bridged-Grain Structure

In this letter, a reversely synchronized stress (RSS) is proposed to simulate the working condition of switching thin-film transistors (TFTs) in active-matrix displays. The reliability of polycrystalline silicon (poly-Si) TFTs under RSS is characterized and investigated. RSS brings huge device degradation. A dynamic hot carrier (HC) effect, dependent on transition edges of RSS, dominates the degradation. Combined with a transient simulation, the degradation mechanism under RSS in poly-Si TFTs is discussed and developed. To suppress RSS-induced HC degradation, a bridged-grain (BG) structure is employed in the active layer of poly-Si TFTs. Via BG lines’ reducing the lateral electric field in the channel at source/drain sides, the reliability of BG TFTs under RSS is significantly improved.

Optimized Design of Carrier Injection Terminal for Reliable Low-Temperature Poly-Si TFTs Under Dynamic Hot-Carrier Stress

Dynamic hot-carrier (HC) degradation can be effectively suppressed in four-terminal low-temperature poly-Si (LTPS) thin film transistors (TFTs) with a carrier injection terminal. In order to enhance the reliability of the four-terminal LTPS TFTs, geometry effect of the carrier injection terminal, such as width and location, on the dynamic HC degradation is systematically studied. It shows that a wider carrier injection terminal, which provides more carriers injection, can suppress the degradation more effectively. As for the location, if the injection terminal is adjacent to the edge of the drain depletion region, which extends into the channel at the falling time of the gate voltage pulses, the four-terminal TFTs can provide the best immunity to the dynamic HC degradation. The proposed optimization scheme can greatly enhance the reliability of LTPS TFTs, and the mechanism can be understood based on the nonequilibrium p-n junction degradation model.

Degradation Induced by Forward Synchronized Stress in Poly-Si TFTs and Its Reduction by a Bridged-Grain Structure

In this letter, forward synchronized stress (FSS) is proposed to further simulate the working conditions of switching thin-film transistors (TFTs) in active-matrix displays. The FSS induces tremendous device degradation in polycrystalline (poly-Si) TFTs, which is dominated by a dynamic hot carrier (HC) effect. For the first time, it is found that the dynamic HC effect is dependent on both rising time and falling time. Incorporated with TCAD simulations, the degradation mechanism is tentatively discussed. To alleviate such FSS-induced tremendous degradation, a bridged-grain structure, which can effectively suppress the peak value of lateral electric field by multiple reversed junctions, is applied in the active channel of poly-Si TFTs.

TCAD Analysis of the Four-Terminal Poly-Si TFTs on Suppression Mechanisms of the DC and AC Hot-Carrier Degradation

Four-terminal poly-Si thin-film transistors (TFTs), with a counter-doped body terminal connected to the floating channel, can suppress both dc and dynamic hot-carrier (HC) degradation of TFTs. With 3-D TCAD simulation, we clarify the underlying mechanisms of the suppression effect and analyze its dependence on the position and width of the body terminal. Under dc HC condition, a wider body terminal or that closer to the drain collects more holes generated from impact ionization in the drain depletion region and suppresses the parasitic bipolar junction transistor effect, subsequently reduces the kink current more effectively. Under dynamic HC condition, the body terminal injects holes at the end of the falling time of the gate pulse, partially removes the non-equilibrium state, significantly relieves the transient maximum electric field in the drain depletion region, thus suppresses the dynamic HC degradation. A wider body terminal can inject more holes and the holes injected by that closer to the drain diffuse to drain depletion region first, thus suppress the dynamic HC degradation better.

OFF-State-Stress-Induced Instability in Switching Polycrystalline Silicon Thin-Film Transistors and Its Improvement by a Bridged-Grain Structure

In this letter, an off-state stress is proposed to simulate the operation conditions of switching polycrystalline thin-film transistors in active-matrix displays for the first time. A dynamic hot carrier (HC) effect, dependent on data pulse falling time, dominates the device degradation. Incorporated with the transient simulations, the device degradation mechanism is tentatively discussed. Finally, a bridged-grain structure, which can effectively shares the stress voltage drop via multiple reverse junctions, is employed to relieve such off-state-stress-induced dynamic HC degradation.

Static and dynamic hot carrier accelerated TDDB: Influencing factors and impact on product lifetime

In this paper we show the full picture of hot carrier accelerated TDDB from static single transistor tests to AC stress and finally, to real product assessments. The different influencing factors like voltage, temperature and Vth are shown to be similar for all stress types. Moreover, an AC frequency dependency – that can be explained by the considerable lifetime of hot carriers – results in a further reduction of the breakdown time. The field relevance is assessed by long term (4000h) HTOL product tests.

“Driving”-Stress-Induced Degradation in Polycrystalline Silicon Thin-Film Transistors and Its Suppression by a Bridged-Grain Structure

In this letter, degradation of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under “driving” stress is characterized and analyzed for the first time. Dynamic hot carrier (HC) effect, related to pulse falling time, dominates device degradation. To suppress such “driving”-stress-induced dynamic HC degradation, a bridged-grain (BG) structure is applied to the active channel of poly-Si TFTs. Due to the lateral electric field reduction at source/drain junctions, “driving”-stress-induced dynamic HC degradation is significantly improved by the BG structure. Incorporated with transient simulations, the degradation mechanism is elucidated.

Dynamic-Gate-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

In this paper, degradation behaviors of bridged-grain (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are systematically characterized and investigated. Device degradation exhibits a two-stage behavior, which is related to pulse falling time ( $t_{f}$ ). A faster $t_{f}$ brings a larger ON-current ( $I_{\mathrm{\scriptscriptstyle ON}}$ ) increase in the first stage and a larger $I_{\mathrm{\scriptscriptstyle ON}}$ decrease in the second stage. Electron trapping/injection into gate oxide and dynamic hot carrier effect are found to be responsible to $I_{\mathrm{\scriptscriptstyle ON}}$ increase in the first stage and $I_{\mathrm{\scriptscriptstyle ON}}$ decrease in the second stage, respectively. Compared with normal poly-Si TFTs, BG poly-Si TFTs show much more reliable performance under the same dynamic gate stress. The larger $I_{\mathrm{\scriptscriptstyle ON}}$ increase in the first stage in BG poly-Si TFTs is attributed to the enhanced vertical electric field in the channel near the gate oxide, while the much smaller $I_{\mathrm{\scriptscriptstyle ON}}$ decrease in the second stage is attributed to lateral electric field reduction caused by the sharing of the field across multiple reversely biased junctions inside the active channel. Incorporated with transient simulations, the degradation mechanisms for both the first stage and the second stage are elucidated. In addition, the impact of the first-stage degradation on the second-stage degradation is also clarified.

Suppress Dynamic Hot-Carrier Induced Degradation in Polycrystalline Si Thin-Film Transistors by Using a Substrate Terminal

Dynamic hot-carrier induced degradation is a major reliability issue for polycrystalline Si thin-film transistors (TFTs) under various pulsed voltage operations. To suppress the degradation, four-terminal TFT with an additional substrate terminal connected to the floating channel is proposed. The role of the substrate terminal is to supply majority carriers during the fast voltage transition and eliminate the nonequilibrium state associated with the channel/source and channel/drain junctions. It is demonstrated that device lifetime can be extended by more than one order of magnitude using the proposed structure. It can be more effective for forward biased substrate terminal and for narrow width TFTs, providing a feasible solution to enhance the TFT reliability.

Abnormal sub-threshold swing degradation under dynamic hot carrier stress in HfO2/TiN n-channel metal-oxide-semiconductor field-effect-transistors

This work finds abnormal sub-threshold swing (S.S.) degradation under dynamic hot carrier stress (HCS) in n-channel metal-oxide-semiconductor field-effect-transistors with high-k gate dielectric. Results indicate that there is no change in S.S. after dynamic HCS due to band-to-band hot hole injection at the drain side which acts to diminish the stress field. Moreover, the impaired stress field causes the interface states to mainly distribute in shallow states. This results in ON state current and transconductance decreases, whereas S.S. degradation is insignificant after dynamic HCS. The proposed model is confirmed by one-side charge pumping measurement and gate-to-drain capacitance at varying frequencies.

Degradation Mechanisms of MILC P-Channel Poly-Si TFTs under Dynamic Hot-Carrier Stress Using a Novel Test Structure

In this study, dynamic hot carrier effect in the MILC p-channel TFT device can be characterized by the unique struture. This novel structure is capable of spatially resolving the hot carrier effect and is highly sensitive to detect the defect-rich region. The dynamic hot carrier stress is focused on the impacts of the frequency, the rising time and the falling time. In varied frequency stress condition, the degradation in the DMT increases monotonically with increasing frequency, infering that more defects are generated by extra dynamic stress contribution in the drain side and degrade the characteristic of device. Under varied falling time stress condition, the on-current degradtion become severe with decreasing falling time due to the extra voltage drop during voltage switch, The final part is effect of rising time, whose degradation is resulted from the the large voltage drop exists between the channel and the junction while device switches.

Degradation Mechanisms of MILC P-Channel Poly-Si TFTs under Dynamic Hot-Carrier Stress

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An investigation of drain pulse induced hot carrier degradation in n-type low temperature polycrystalline silicon thin film transistors

Degradation of n-type low temperature polycrystalline silicon thin film transistors under drain pulse stress is first investigated. Stress parameters are pulse amplitude, frequency and transition time. Device degradation is found to be dominated by a dynamic hot carrier effect, which is independent of pulse falling time but depends on pulse rising time. Shorter rising time brings larger device degradation. Based on experimental results and device simulation, a PN junction degradation model taking trap related carrier emission and trapping into account is proposed.

Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors Under Synchronized Voltage Stress

Device degradation of n-type metal-induced laterally crystallized polycrystalline silicon thin-film transistors is systematically investigated under synchronized Vg and Vd pulse stresses. ON-state degradation is dominated by a pulse duty-time-related self-heating (SH) mechanism for low-frequency stresses whereas by a pulse transient time-related dynamic hot carrier (HC) mechanism for high-frequency stresses. OFF-state degradation is dominated by the dynamic HC effect, irrespective of stress frequency. It is first observed that such dynamic HC degradation is independent of the pulse falling time (tf) but dependent on the rising time (tr). During tr, HCs are generated in the drain depletion region by a high transient coupling electric field arising from Vg switching. However, during tf, the HC effect is screened by SH that caused high temperature rise. Device saturation is confirmed to play a key role in dynamic HC degradation under synchronized stresses. The proposed degradation model is verified by comparing it with various stress test results.

Investigation of defects introduced by static and dynamic hot carrier stress on SOI partially depleted body-contact MOSFETs

SOI partially depleted body-contact MOSFETs were subjected to static and dynamic hot carrier stress. Drain current was investigated by means of Deep Level Transient Spectroscopy and switch-ON transient analysis in a wide temperature range. Under static degradation regime, drain current behaviour was determined by the creation of two discrete traps most likely located in the drain vicinity; a hole trap cited in the literature and a defect of metastable nature. Under dynamic degradation regime, drain current behaviour was determined by body–Si/SiO 2 interface-state generation. Experimental data and fitting results based on stretched exponential law are in accordance.

Dynamic hot-carrier induced degradation in n-channel polysilicon thin-film transistors

The effects of hot-carriers under dynamic stress on the transfer characteristics and the noise performance of n-channel polysilicon thin-film transistors are analysed. The observed decrease in the on-state current is directly related to the mobility of a damaged region extended over a length of about 0.53 μm beside the drain, which is evaluated through analysis of the transfer characteristics at low drain voltage. The mobility degradation in the damaged region is due to the formation of traps located near the polysilicon/gate oxide interface as evidenced by the 1/ f noise measurements.

Dynamic hot carrier degradation effects in CMOS submicron transistors

Hot carrier degradation in submicron LDD CMOS transistors under dynamic operation is studied. Anomalous degradation modes are shown in p-channel transistors, and a simple model for their interpretation is presented. Correct characterization of hot carrier damage and its physical mechanisms are discussed.