Dynamic Energy Reduction Research Articles

COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications

The growing trend of pervasive computing has consolidated the everlasting need for power efficient devices. The conventional cache subsystem of general-purpose CPUs, while being able to adapt to many use cases, suffers from energy inefficiencies in some scenarios. It is well-known by now in the academic literature that the utilization of a scratchpad memory (SPM) can help reducing the overall energy consumption of embedded systems. This work proposes a hybrid cache-SPM architecture with support logic for semi-transparent data management and spatial locality improvement. Selected data are transferred and stored in the SPM in a compact form using dynamic layout transformation. As a second major contribution, we introduce a methodology to identify memory access sequences that make an inefficient use of the cache, marking them as candidates to be moved to an SPM of constrained space. The methodology does not require access to the source code of the target applications, relying on binary instrumentation and offline profiling. The resulting mapping policies have been tested on a simulated system, showing a mean memory dynamic energy reduction of 43% and a mean speed gain of 13% with a representative benchmark set.

Writing-only in-MRAM computing paradigm for ultra-low power applications

In-memory computing (IMC) is demonstrated as a breakthrough in terms of few interconnection delay and high density. Computing in nonvolatile memory, e.g., spin-transfer-torque (STT)-MRAM, is expected to realize near-zero leakage power consumption and unlimited endurance. Based on circuit-level reconfiguration, we propose a in-MRAM computing scheme to perform data storage and Boolean arithmetic simultaneously. This proposed scheme is implemented with a 28-nm CMOS process and a 40-nm Magnetic tunnel junction (MTJ) compact model. The self-write-termination method achieves 84.7% writing energy saving within 20-ns write access duration. A high-level simulation is performed with 28×28 pixels image similarity analysis. It demonstrates 24% dynamic energy reduction comparing to the previous method. The proposed in-MRAM computing scheme is also applicable to other resistive memories with the identical bit-cell structure.

Early Address Prediction

Achieving low load-to-use latency with low energy and storage overheads is critical for performance. Existing techniques either prefetch into the pipeline (via address prediction and validation) or provide data reuse in the pipeline (via register sharing or L0 caches). These techniques provide a range of tradeoffs between latency, reuse, and overhead. In this work, we present a pipeline prefetching technique that achieves state-of-the-art performance and data reuse without additional data storage, data movement, or validation overheads by adding address tags to the register file. Our addition of register file tags allows us to forward (reuse) load data from the register file with no additional data movement, keep the data alive in the register file beyond the instruction’s lifetime to increase temporal reuse, and coalesce prefetch requests to achieve spatial reuse. Further, we show that we can use the existing memory order violation detection hardware to validate prefetches and data forwards without additional overhead. Our design achieves the performance of existing pipeline prefetching while also forwarding 32% of the loads from the register file (compared to 15% in state-of-the-art register sharing), delivering a 16% reduction in L1 dynamic energy (1.6% total processor energy), with an area overhead of less than 0.5%.

SeFAct2: Selective Feature Activation for Energy-Efficient CNNs Using Optimized Thresholds

This work presents a framework for dynamic energy reduction in hardware accelerators for convolutional neural networks (CNNs). The key idea is based on the early prediction of the features that may be important, with the deactivation of computations related to unimportant features and static bitwidth reduction. The former is applied in late layers of the CNN, while the latter is more effective in the early layers. The procedure includes a methodology for automated threshold tuning to detect feature activation. For various state-of-the-art neural networks, the results show that energy savings of up to about 30% are achievable, after accounting for all implementation overheads, with a small loss in the accuracy.

A Restore-Free Mode for MLC STT-RAM Caches

Spin-transfer torque RAM (STT-RAM) caches are foreseen to replace traditional static RAM caches because of their nonvolatile nature and high density. Multilevel cell (MLC) STT-RAMs further enhance the storage density of single-level cell STT-RAMs. However, the two-step read/write process in MLC STT-RAMs adversely affects performance, energy consumption, and lifetime. Moreover, technology scaling makes the read operations disturb the stored data in MLC STT-RAMs, giving rise to an issue called read disturbance (RD). Restore operations, which are required to cope with RD, further add to the problems of using MLCs. In this brief, we propose a Restore-free mode for frequently reused cache lines in MLC STT-RAMs that leverages single-step read/write operations to the MLC without the need for restore operations. Our proposed scheme in single-core (quad-core) systems, achieves a 27.4% (23%) dynamic energy reduction, a 3.7% (7%) increase in performance, and an 81% (62.5%) lifetime improvement.

Synthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoT

This paper identifies novel directions of standard-cell-based synthesizable memory design. A compact 18T-bitcell of OR-AND-Invert (OAI) and AND-OR-Invert (AOI) logic gates is presented with bit-selective write and multiplexed read accesses. It reduces the bitcell area by 11%–40% compared to the state-of-the-art clock-gating-based D-latch schemes while avoiding custom-cell design. The improved storage density comes from the tight integration on two levels–coupling the read multiplexing within each bitcell and taking advantage of structured datapath placement in bitcell arrays by using commercial CAD tools. As measured on a 40 nm SRAM of 90 kb, the OAI/AOI-gate-based synthesizable memory features 0.4 V minimum access voltage, 30 fJ minimum read energy per bit, and a leakage power of 1.4 pW per bit at 0.3 V data retention voltage. It is ideally suited for IoT-node design operating in sub- $V_{\mathrm {t}}$ for joint dynamic energy and leakage power reduction. Further, it enables fast turn-around times by IP reuse over technology nodes with minimal (re)design effort.

Dynamic Energy Reduction in TCAM Match-Line Sensing Using Charge-Sharing and Positive Feedback

Network routers use ternary content addressable memory (TCAM) for high-speed table look-up. A match-line (ML) sensing scheme for TCAM combining charge-sharing and positive feedback is presented. The objective is to simplify the ML sense amplifier (MLSA) of existing charge-sharing scheme while reducing ML energy consumption during look-up. The look-up has been performed in two steps. In the first step, a segment of each TCAM word is compared with the search key to detect large percentage of the mismatched words. The detected mismatched words are deactivated in the second step to reduce energy consumption. In the second step, the charge stored in a matched ML first segment is shared with second ML segment. Use of positive feedback in this step makes the MLSA circuit simple. Post-layout simulations implemented using 180[Formula: see text]nm 1.8[Formula: see text]V CMOS logic have been performed. In addition to lower scheme complexity and 16.5% reduction in circuit area, the proposed scheme provides dynamic energy saving up to 5.5% and peak power reduction of 52% compared to existing state-of-the-art charge-sharing technique.

Type Information Elimination from Objects on Architectures with Tagged Pointers Support

Implementations of object-oriented programming languages associate type information with each object to perform various runtime tasks such as dynamic dispatch, type introspection, and reflection. A common means of storing such relation is by inserting a pointer to the associated type information into every object. Such an approach, however, introduces memory and performance overheads when compared with non-object-oriented languages. Recent 64-bit computer architectures have added support for tagged pointers by ignoring a number of bits - tag - of memory addresses during memory access operations and utilize them for other purposes; mainly security. This paper presents the first investigation into how this hardware support can be exploited by a Java Virtual Machine to remove type information from objects. Moreover, we propose novel hardware extensions to the address generation and load-store units to achieve low-overhead type information retrieval and tagged object pointers compression-decompression. The evaluation has been conducted after integrating the Maxine VM and the ZSim microarchitectural simulator. The results, across all the DaCapo benchmark suite, pseudo-SPECjbb2005, SLAMBench and GraphChi-PR executed to completion, show up to 26 and 10 percent geometric mean heap space savings, up to 50 and 12 percent geometric mean dynamic DRAM energy reduction, and up to 49 and 3 percent geometric mean execution time reduction with no significant performance regressions.

Reducing Wire and Energy Overheads of the SMART NoC Using a Setup Request Network

Network-on-chip (NoC), due to its superior scalability, has become increasingly popular in multicore and many-core designs. A recent state-of-the-art NoC design, called single-cycle multihop asynchronous repeated traversal (SMART), enables ultralow latency performance by enabling a flit to bypass the pipelines of intermediate routers entirely. This enables a flit to traverse multiple routers within a single clock cycle. However, there are two concerns related to SMART: 1) it employs dedicated broadcast wires to transmit SMART-hop setup requests (SSRs), incurring large wire and energy overheads and 2) it needs a complex allocator to arbitrate multiple simultaneous SSRs. In this paper, we propose an SSR network to address these two concerns. This is a specialized network that replaces long and overlapping broadcast wires with shorter wires and switches. It reduces the wire and energy overheads significantly. It also eliminates low-priority SSRs before they reach the allocator and, therefore, leads to a simplified allocator design. We evaluate SSR networks in various contexts. Our evaluation demonstrates that the SSR network can reduce the wire overhead by up to $12.2\times $ . Moreover, it results in up to 63.7% area reduction, and up to 15.7% dynamic energy reduction. It also makes multiple physical networks and/or wider flits feasible. This paper shows that with fewer wires and the same amount of buffer space, multiple simple SMART-1D networks can deliver a higher bandwidth and lower latency than a single complex SMART-2D network, when our SSR network is used.

Minimum energy consumption for rate monotonic scheduled tasks

Limited battery power is a typical constraint in stand-alone embedded systems. One way to extend the battery lifetime is by reducing CPU power consumption. Because of the quadratic relationship between power consumption in CMOS circuits and CPU voltage, power reduction can be obtained by scaling down supply voltage, or dynamic voltage scaling. However, reducing supply voltage slows down CPU speed since supply voltage has a proportional relationship with CPU frequency. On the other hand, in any real-time embedded environment (especially hard real-time), timing constraints are critical. In this paper, we focus on dynamic energy reduction of tasks scheduled by rate monotonic (RM) algorithm in a hard real-time embedded environment. The RM algorithm preemptively schedules any set of periodic tasks by assigning higher priorities to frequent tasks. For any periodic task set that satisfies the CPU utilization bound, we determine the provably optimal scaling of the worst-case execution time of each task that consumes minimum dynamic energy while satisfying the utilization bound. As RM algorithm is widely used, we expect this work can lead to better energy reduction management and expectations.

Improved Charge-shared Match-line Sensing Scheme for Dynamic Energy Reduction in TCAM

ABSTRACTTernary content addressable memory (TCAM) is used for high-speed table look-up. A match-line (ML) sensing scheme to reduce energy consumption in ML during look-up is presented. The look-up is performed in two steps. In the first step, small segment of each TCAM word is compared with the search key to detect most of the mismatched words. These words remain deactivated in the next step causing energy saving. In the second step, the charge stored in a matched ML first segment is recycled by allowing charge sharing with second ML segment. Charge recycling and absence of ML charging from power supply make total energy consumption low. Post-layout simulation of the scheme implemented using 180 nm 1.8 V CMOS logic shows that for a search time of 2479 ps, the scheme can provide larger noise margin than some popular techniques. It offers at least 80%, 31%, and 29% energy savings compared to the conventional, current-race, and state of the art charge sharing scheme, respectively. For 32 nm technology node, the energy savings are at least 46% and 15% compared to the current-race and the existing charge sharing scheme, respectively.

Energy-Efficient Pixel-Arithmetic

With the advent of pervasive computing, the performance requirements of visual applications have increased significantly. On the other hand, the energy budget for future devices may decrease due to reduced form factors and thus smaller battery sizes. It is thus imperative to improve energy efficiency of visual applications to meet their stringent demands in energy-constrained devices. This paper presents a novel energy-efficient floating-point unit (E <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> FPU) that dynamically detects multiplications in which at least one operand is an integer power of two or the sum of consecutive integer powers of two (POW2 operands) and executes them on the E <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> FPU. We show that POW2 operands are extremely common in visual applications. For non-POW2 operands, we propose dynamic approximation of suitable operands as the closest POW2 operand with the same exponent while ensuring a small and limited approximation error. Finally, we exploit the limited dynamic range of pixel values to enhance the E <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> FPU to support low-energy FP addition for a sub-set of the single-precision floating-point dynamic range. The proposed E <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> FPU can reduce execution energy by 35 percent with a negligible impact on the peak signal to noise ratio. Overall, at the chip-level, our approaches yield a 12 percent dynamic energy reduction for a graphics processing unit (GPU).

AN ENERGY-EFFICIENT DEMAND-DRIVEN REGISTER FILE FOR MOBILE GPUs

In response to the remarkable increase in 3D applications in mobile devices in recent years, mobile GPUs have become widely available. Although the computation requirements are tremendous of 3D applications, they are highly data parallel operations. Therefore, mobile GPUs are usually hardware multithreaded to increase their throughput and achieve real-time rendering. This design increases energy consumption by duplicate register files in shaders. However, the register usage of shading programs is often relatively low, which causes many duplicated registers to go unused, and thus wastes energy. In addition, long latency memory operations can consume unnecessary energy to activate registers as well. This study proposes a compiler-assisted energy-efficient demand-driven register file (EDRF) to reduce energy consumptions of registers that are unused and waiting for long latency memory operations. The proposed EDRF is shared on demand between concurrent threads with multiple power gating modes. The management scheme of EDRF puts registers into different power modes to save leakage energy. In addition, the partitioned structure of EDRF saves dynamic energy for accessing registers. Results show that the average dynamic and leakage energy reduction ratios are 84.18% and 99.20%, respectively. Furthermore, the performance degradation from the proposed EDRF is only 0.50% on average.

A match-line dynamic energy reduction technique for high-speed ternary CAM using dual feedback sense amplifier

Ternary content addressable memory (TCAM) has become popular in applications requiring high-speed table lookup. This paper presents a match-line (ML) sensing scheme to reduce dynamic energy consumption in MLs during the table lookup operation. Positive feedback has been used twice in the ML sense amplifier to achieve improved performance over existing schemes employing single feedback. Post-layout simulation of the scheme implemented using 180nm 1.8V CMOS logic shows that it can have match detection time as small as 907ps. The scheme can also provide large voltage margin of 734mV. Compared to popular current-race sensing scheme, the proposed scheme offers 83.8% energy reduction. It can achieve 64.5%, 74.7% and 77.8% energy savings compared to existing feedback schemes namely mismatch dependent, active feedback and resistive feedback, respectively. The energy saving is even larger for more advanced technology node.

Criticality guided energy aware speculation for speculative multithreaded processors

Unending quest for performance improvement coupled with the advancements in integrated circuit technology have led to the development of new architectural paradigm. Speculative multithreaded architecture (SpMT) philosophy relies on aggressive speculative execution for improved performance. However, aggressive speculative execution comes with a mixed flavor of improving performance, when successful, and adversely affecting the energy consumption (and performance) because of useless computation in the event of mis-speculation. Dynamic instruction criticality information can be usefully applied to control and guide such an aggressive speculative execution. In this paper, we present a model of micro-execution for SpMT architecture that we have developed to determine the dynamic instruction criticality. We have also developed two novel techniques utilizing the criticality information namely delaying the non-critical loads and the criticality based thread-prediction for reducing useless computations and energy consumption. Experimental results showing break-up of critical instructions and effectiveness of proposed techniques in reducing energy consumption are presented in the context of multiscalar processor that implements SpMT architecture. Our experiments show 17.7% and 11.6% reduction in dynamic energy for criticality based thread prediction and criticality based delayed load scheme respectively while the improvement in dynamic energy delay product is 13.9% and 5.5%, respectively.

Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures

Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar and simultaneous multi-threading (SMT) processors for instruction-level parallelism and thread-level parallelism exploitation. However, the large BTB not only dominates the predictor energy consumption, but also becomes a major roadblock in achieving faster clock frequencies at deep sub-micron technologies. The authors propose here a filtering scheme to dramatically reduce the accesses to the BTB to achieve significantly reduced energy consumption in the BTB while maintaining the performance. For a simulated superscalar microprocessor, the experimental evaluation shows that the BTB access filtering (BAF) design achieves an 88.5% dynamic energy reduction with negligible performance loss. The authors also study the leakage behaviour and its control in the BAF design. The results show that by applying a drowsy strategy, very effective leakage control can be achieved. For the high-performance design, the BAF can also improve BTB's performance scalability at new technologies. For the simultaneous multi-threading environment, the authors evaluate the effectiveness of the BAF design and propose a banked BAF (BK-BAF) scheme to further reduce the energy consumption and performance overhead. The experimental results confirm that the BK-BAF scheme can be an energy/performance-effective design for next generation SMT processors.

Yield-Driven Near-Threshold SRAM Design

Voltage scaling is desirable in static RAM (SRAM) to reduce energy consumption. However, commercial SRAM is susceptible to functional failures when VDD is scaled down. Although several published SRAM designs scale VDD to 200-300 mV, these designs do not sufficiently consider SRAM robustness, limiting them to small arrays because of yield constraints, and may not correctly target the minimum energy operation point. We examine the effects on area and energy for the differential 6T and 8T bit cells as VDD is scaled down, and the bit cells are either sized and doped, or assisted appropriately to maintain the same yield as with full VDD. SRAM robustness is calculated using importance sampling, resulting in a seven-order run-time improvement over Monte Carlo sampling. Scaling 6T and 8T SRAM VDD down to 500 mV and scaling 8T SRAM to 300 mV results in a 50% and 83% dynamic energy reduction, respectively, with no reduction in robustness and low area overhead, but increased leakage per bit. Using this information, we calculate the supply voltage for a minimum total energy operation (VMIN) based on activity factor and find that it is significantly higher for SRAM than for logic.

Interests and Limitations of Technology Scaling for Subthreshold Logic

Subthreshold logic is an efficient technique to achieve ultralow energy per operation for low-to-medium throughput applications. In this paper, the interests and limitations of technology scaling for subthreshold logic are investigated from 0.25 mum to 32 nm nodes. Scaling to 90/65 nm nodes is shown to be highly desirable for medium-throughput applications (1-10 MHz) due to great dynamic energy reduction. However, this interest is limited at 45/32 nm nodes by high static energy due to degraded subthreshold swing and delay variability. Moreover, for low-throughput applications (10-100 kHz), this limitation is worsened by the increase of minimum supply voltage to achieve sufficient functional yield, which results in bad energy efficiency starting at 0.13 mum node. Upsizing the channel length is proposed as a straightforward circuit-level technique to efficiently mitigate these effects. At 32 nm node, this technique reduces energy per operation by 60% at medium throughput and by two orders of magnitude at low throughput.

Energy efficient DVS schedule for fixed-priority real-time systems

Energy consumption has become an increasingly important consideration in designing many real-time embedded systems. Variable voltage processors, if used properly, can dramatically reduce such system energy consumption. In this paper, we present a technique to determine voltage settings for a variable voltage processor that utilizes a fixed-priority assignment to schedule jobs. By exploiting more efficiently the processor slack time, our approach can be more effective in reducing the execution speed for real-time tasks when necessary. Our approach also produces the minimum constant voltage needed to feasibly schedule the entire job set. With both randomly generated and practical examples, our heuristic approach can achieve the dynamic energy reduction very close to the theoretically optimal one (within 2%) with much less computation cost.

An Energy-Efficient Partitioned Instruction Cache Architecture for Embedded Processors

Energy efficiency of cache memories is crucial in designing embedded processors. Reducing energy consumption in the instruction cache is especially important, since the instruction cache consumes a significant portion of total processor energy. This paper proposes a new instruction cache architecture, named Partitioned Instruction Cache (PI-Cache), for reducing dynamic energy consumption in the instruction cache by partitioning it to smaller (less power-consuming) sub-caches. When the proposed PI-Cache is accessed, only one sub-cache is accessed by utilizing the temporal/spatial locality of applications. In the meantime, other sub-caches are not accessed, leading to dynamic energy reduction. The PI-Cache also reduces dynamic energy consumption by eliminating the energy consumed in tag lookup and comparison. Moreover, the performance gap between the conventional instruction cache and the proposed PI-Cache becomes little when the physical cache access time is considered. We evaluated the energy efficiency by running a cycle accurate simulator, SimpleScalar, with power parameters obtained from CACTI. Simulation results show that the PI-Cache improves the energy-delay product by 20%--54% compared to the conventional direct-mapped instruction cache.