Dynamic Element Matching Method Research Articles

A Symmetric Group Control Dynamic Element Matching Method Applied in High Resolution SAR ADCs for Biomedical Applications

Capacitor mismatch plays an important part in the spurious-free dynamic range (SFDR) performance of high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs). This paper presents a symmetric group control dynamic element matching (SGCDEM) method aiming at enhancing SFDR of SAR ADCs applied in biomedical applications. The proposed scheme symmetrically divides the capacitor array into four sub-DACs, using quantization results corresponding to each sub-DAC as rotary control codes to symmetrically control the rotation of the capacitors. In order to improve the energy efficiency and save chip area, the proposed method replaces the pseudo-random number generator (PRNG) with quantization results of ADC as the rotary control code. Moreover, split rotator technology is applied in the proposed scheme to reduce the number of multiplexers (MUX) used in the rotator, which introduces a low logic depth. The proposed architecture has been implemented on a 12-bit SAR ADC model in MATLAB in order to verify its performances. After taking a standard deviation of 1% for the unit capacitance into consideration, this method achieves above 77.3[Formula: see text]dB SFDR, enabling to correct the SFDR by more than 23.6[Formula: see text]dB compared with the structure without DEM.

An improved Random Swapping Thermometer Coding (RSTC) Dynamic Element Matching (DEM) method

ABSTRACT An improved Random Swapping Thermometer Coding (RSTC) Dynamic Element Matching (DEM) method is presented for Nyquist-rate Digital to Analog converters (DACs). In contrast to the RSTC DEM method, the presented method prevents the Spurious-free dynamic range (SFDR) reduction in DACs in low signal frequencies. Also, while ”RSTC with the restricted jumping technique” method is unable to prevent the SFDR reduction in low frequencies for non-full-scale sinusoidal signals, this new method prevents the SFDR reduction in low frequencies for both full-scale and non-full-scale sinusoidal signals. The Fast fourier transform (FFT) analysis for a behavioural model of a 6-Bit thermometer coded DAC at ( is the signal frequency and is the sample rate) shows 2.1 dB SFDR improvement in comparison to ”RSTC with the restricted jumping technique” method. In addition, the presented method achieves a reasonable trade-off between SFDR and Switching activity in comparison to other DEM methods.

Two-Dimensional Structure Compatible with DEM Methods Utilizing in DACs

A two-dimensional digital-to-analog converter (DAC) structure compatible with dynamic element matching (DEM) methods is presented. Unlike the DACs using segmented structure for employing DEM, the new structure randomizes inter-segment error. This advantage is achieved because of the characteristics of the algorithm of two-dimensional decoding. The simulation results in 180[Formula: see text]nm CMOS technology, 319.72[Formula: see text]MHz signal frequency and 800[Formula: see text]MS/s sample rate for an 8-bit two-dimensional DAC utilizing the presented structure, shows 14.94[Formula: see text]dB spurious-free dynamic range (SFDR) improvement compared to the SFDR of the same DAC without employing the presented structure. Also, the IMD3 of the DAC employing the presented structure for [Formula: see text][Formula: see text]MHz and [Formula: see text][Formula: see text]MHz is 50.1[Formula: see text]dB.

All-CMOS low supply voltage scattered thermal monitoring front-end

Presented is a low-voltage all-CMOS scattered thermal monitoring architecture front-end designed in a 0.5 µm process. To support low-voltage operation for scaled CMOS technologies, MOSFETs operating in the subthreshold region and an amplifier with a bulk-driven technique are used. To reduce the offset error caused by device mismatches, gain boosting, dynamic offset cancellation and dynamic element matching methods are adopted. The sensor node occupies an area of 90×70 µm2. The measured minimum supply voltage was 1.1 V over a −55 to 125 °C temperature range. The front-end was chamber tested and the performances are reported. Experiments demonstrated the multi-corner thermal monitor detecting on-chip temperature gradients from 1.2 to 26 °C/mm.

A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Employing a One-Element-Shifting Dynamic Element Matching

This paper proposes a new dynamic element matching (DEM) method referred to as one-element-shifting (OES) for the implementation of high spurious-free dynamic range (SFDR) multi-bit Delta-Sigma modulators (DSMs). Generic DEM techniques are successful at suppressing the mismatch error and increasing the SFDR of data converters. However, they will induce additional glitch energy in most cases. Some recent DEM methods achieve improvements in minimizing glitch energy but sacrificing their effects in harmonic suppression due to mismatches. OES technique proposed in this paper can suppress the effect of glitch while preserving the reduction of element mismatch effects. Hence, this approach achieves better SFDR performance over the published DEM methods. With the proposed OES, a 3rd order, 10 MHz bandwidth continuous-time DSM is implemented in 90 nm CMOS process. The measured SFDR attains 83 dB for a 10 MHz bandwidth. The measurement result also shows that OES improves the SFDR by higher than 10 dB.

Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC

Dynamic element matching (DEM) has been employed to increase the spurious-free dynamic range of data converters. However, generic DEM techniques will induce additional glitch energy. This brief describes a type of the DEM method called random swapping thermometer coding for the implementation of Nyquist-rate current-steering digital-to-analog converters. The selecting direction for a sequence of unit current sources will be randomly changed. Furthermore, combining the restricted jumping technique simultaneously can further smooth low-frequency idle tones. This approach can minimize the number of switched elements as codes change, while achieving good spectrum purity as other DEM implementations. Examples from a behavior-level simulation for 6-bit converters are given to illustrate harmonic suppression and glitch energy improvement achieved by the proposed algorithm.

A Deterministic Dynamic Element Matching Approach for Testing High-Resolution ADCs With Low-Accuracy Excitations

Dynamic element matching (DEM) is capable of providing good average linearity performance in matching critical circuits in the presence of major component mismatch, but the approach has received minimal industrial adoption outside of /spl Sigma/-/spl Delta/ structures because of challenges associated with implementation of a required randomizer and because of the time-local nonstationarity. This paper presents a DEM approach to analog-to-digital converter (ADC) testing in which low-precision DEM digital-to-analog converters (DACs) are used to generate stimulus signals for ADCs under test. It is shown that in a testing environment, this approach provides very high precision test results, and time-local nonstationarity is of no concern. In addition to traditional random DEM techniques, a deterministic DEM (DDEM) strategy that eliminates the need for a randomizer is introduced. The performance of the DDEM method is established mathematically and validated with detailed simulation results. Furthermore, the DDEM method requires far fewer samples to achieve the same level of average linearity than the random DEM approach. It is demonstrated that both the random DEM and DDEM methods can be used to accurately test ADCs with linearity that far exceeds that of the DAC used as a signal generator. This technique of using imprecise excitations and DEM to test much more accurate ADCs offers potential for use in both production test and built-in self-test environments where high linearity test sources are difficult to implement.

Noise shaping dynamic element matching method using tree structure

The authors present a practical high-speed noise-shaping dynamic element-matching method requiring small additional circuits by introducing the tree structured vector quantiser (VQ) The VQ hardware size is drastically reduced from order N log N to order N.

A sigma-delta modulator as an A/D converter

A sigma-delta modulator system is discussed as an alternative to the dual-slope converter. A simple auto-zero circuit and cold switching of the gain setting can be obtained. The implementation of the analog system in the form of two bipolar IC's offers an attractive application as a multi-input data acquisition system with a scanning capability. A combination with a D/A converter increases the resolution with a small Increase in conversion time. Hardly any accurate elements are required in this application if the dynamic element matching method is used in the D/A converter.