Dynamic Element Matching Algorithm Research Articles

A glitch energy reduction method with low complexity dynamic element matching for data converters

Due to the appearance of huge glitch while using traditional Dynamic Element Matching (DEM) in data converters, different kinds of glitch-reduce structures are designed into DEM. However, most of these structures will work with high complexity. Based on random-rotation-binary-weighted selection (RRBS), this paper presents a novel low complexity glitch-reduced DEM algorithm, which can greatly reduce mismatch. The proposed DEM constructs glitch-reduce structure through data selector and comparator, so the complexity is reduced through using less components. As a result, the glitch-reduced DEM increases spurious free dynamic range (SFDR) to 92.47dB at 7.6MHz. Moreover, compared with conventional RRBS, glitch-reduced DEM makes the glitch reduce by 49% with low complexity in a 12-bit digital-to-analog converter (DAC).

Dynamic Element Matching for the Grounded Inductor Simulator Output Stage in Ultrasonic Distance Sensor Applications

This letter describes a new dynamic element matching (DEM) technique usable in a resonant circuit during reverberation measurement. Traditionally, DEM algorithms switch circuit elements during the operating cycle, which would inject periodic noise into such sensitive circuits and degrade parameters of the overall system. We describe a new approach that eliminates this problem by switching elements between operating cycles and processing results from multiple operation cycles. This new DEM technique is specifically targeted for use with a grounded inductor simulator in transformerless park assist sensors. The described DEM approach was verified using a test chip and a digital control implemented in a field-programmable gate array. Measurement results confirming performance of the described DEM approach are presented.

Current Steering Digital Analog Converter with Partial Binary Tree Network (PBTN)

DACs are essential devices in many digital systems which require high performance data converters. Thus, shrinking of supply voltage, budget constraints of test times, and rising bandwidth requirement causing DAC architectures to highly relying on matched components to perform data conversions. However, matched components are nearly impossible to fabricate; there are always mismatch errors which causes the difference between the designed and actual component value. Dynamic Element Matching (DEM) is one of the techniques that are commonly used to reduce component mismatch error. This technique is a randomization technique to select one of the appropriate codes for each of the digital input value before entering DAC block. Thus, in this research, a new DEM algorithm is proposed on Current-Steering DAC with Partial Binary Tree Network (PBTN) algorithm that utilizes a lower complexity circuit to produce output signals with less glitches. Simulation results for 6-bit 1-MSB PBTN DAC produces 0.3184LSB of DNL, 0.0062LSB of INL, and a power consumption of 14.13 mW, while using only 126 transmission gates.

A 18-mW, 20-MHz bandwidth, 12-bit continuous-time Σ Δ modulator using a power-efficient multi-stage amplifier

A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130-nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-bit internal quantizer and three current steering feedback DACs. A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter. Non-return-to-zero DAC pulse shaping is utilized to reduce clock jitter sensitivity. A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy, avoiding the use of a dynamic element matching algorithm to induce excess loop delay. The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio, and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.

A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation

A digital ΔΣ fractional-N frequency synthesizer for 4G communication standards is presented which is able to achieve wide loop bandwidth while producing low fractional spurs. The loop adopts a fractional-N divider based on a phase interpolator, allowing to shrink the TDC dynamic range and to improve its linearity. A dynamic-element matching algorithm is employed to further improve TDC linearity and an original correlation algorithm is used to correct for the phase interpolator mismatches. Both digital algorithms operate in background and they are demonstrated to be concurrently effective in reducing in-band fractional spurs below -57 dBc. The circuit is fully integrated in a 65 nm CMOS process and it synthesizes a carrier in the 3.0-3.6 GHz range from a 40 MHz crystal reference with 40 Hz resolution. It achieves -104-dBc/Hz phase noise at 400-kHz offset and a 3.2-MHz maximum loop bandwidth. The synthesizer dissipates 80 mW and occupies 0.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 100-dB gain-corrected delta-sigma audio DAC with headphone driver

An oversampled digital-to-analog converter (DAC) with a 100-dB A-weighted dynamic range is presented. It uses a switched-capacitor (SC) array to transfer the sampled charges directly into the headphone driver. The overall DAC gain is precisely controlled by a novel reference stage. A new dynamic element matching algorithm, based on split-set data-weighted averaging (SDWA), is used to improve the dynamic range and to reduce the nonlinearity caused by mismatches in the multibit DAC.

Split-set data weighted averaging

A modified dynamic element matching algorithm, based on splitting the unit element set into subsets, is proposed. Simulations show that it can improve the spur-free dynamic range of data-weighted averaging significantly, without degrading its signal-to-noise ratio.

High Precision Image Centroid Computation via an Adaptive K-Winner-Take-all Circuit in Conjunction with a Dynamic Element Matching Algorithm for Star Tracking Applications

An approach for implementing a high precision image target centroid—center of mass (COM) detection system via an adaptive K-winner-take-all (WTA) circuit in conjunction with a 2-D dynamic element matching (DEM) algorithm implementation for image sensor arrays is proposed. The proposed system outputs a high precision COM location of the most salient target in a programmable active region of the field of view (FOV) for star tracking purposes and is suitable for real time applications. The system allows target selection and locking with multiple targets tracking capability. This solution utilizes the separability property of the COM, and therefore reduces the computational complexity by utilizing 1-D circuits for the computation. The DEM algorithm, commonly used in ADC and DAC circuits, allows reducing the required WTA circuit precision to 5–6 bits, while still achieving a high output precision. Simulation results prove the concept and demonstrate the high precision COM result. In addition, a possible low-level hardware implementation is described.

A multibit sigma-delta ADC for multimode receivers

A 2.7-V sigma-delta modulator with a 6-bit quantizer is fabricated in a 0.18-/spl mu/m CMOS process. The modulator makes use of noise-shaped dynamic element matching (DEM) and quantizer offset chopping to attain high linearity over a wide bandwidth. The DEM algorithm is implemented in such a way as to minimize additional delay within the feedback loop of the modulator, thereby enabling the use of the highest resolution quantizer yet reported in a multibit sigma-delta analog-to-digital converter of this speed. The part achieves 95-dB peak spurious-free dynamic range and 77-dB signal-to-noise ratio over a 625-kHz bandwidth, and consumes 30 mW at a sampling frequency of 23 MHz. The part achieves 70-dB signal-to-noise ratio over a 1.92-MHz bandwidth and dissipates 50 mW when clocked at 46 MHz.

An analysis of dynamic element matching flash digital-to-analog converters

Although many dynamic element matching (DEM) digital-to-analog converters (DACs) have identical architectures, analyses of DEM DACs have been specific to the DAC DEM algorithm or based on simulation results. In this paper, a commonly used flash DEM DAC architecture is analyzed. Using this analysis, a DEM DAC's mean integral nonlinearity (INL), variance of the LNL, output signal-to-distortion ratio, output signal-to-(noise plus distortion) ratio, and spurious-free dynamic range can be calculated theoretically. These theoretical measures can be used as criteria for comparing the performance of different DEM algorithms applied to the particular flash DEM DAC architecture analyzed in this paper. As an example, two new DEM algorithms-a barrel shift network controlled by a white stochastic signal and a generalized cube interconnection network (GCN) controlled by a colored stochastic signal-are introduced and compared with two stochastic DEM algorithms: a Benes network and a GCN-both of which are controlled by a white stochastic signal-and one deterministic DEM algorithm called clock-level averaging. In the example, the performance criteria are calculated theoretically and by simulation.

A quadrature data-dependent DEM algorithm to improve image rejection of a complex ΣΔ modulator

A dynamic element matching (DEM) algorithm is presented that is controlled by the quadrature output data of a complex sigma-delta modulator. This DEM technique is used to correct the gain and phase errors between the circuits in the in-phase and quadrature-phase feedback paths of the modulator. The key feature of this DEM technique is that it does not cause leakage of high-frequency quantization noise in the signal band, as encounters with the periodic or pseudorandom DEM techniques. No test signal is required to measure the gain and phase errors, and as the DEM circuit is operating continuously, it compensates for changes in, e.g., temperature and supply voltage. A 0.35-/spl mu/m CMOS prototype chip has been designed to test the DEM circuit. A batch of 38 measured samples shows a typical mismatch-independent image rejection ratio of 63 dB with DEM.

Generalised cube-based dynamic element matching algorithms for digital to analogue converters

Dynamic element matching (DEM) digital to analogue converters (DACs) often use interconnection networks to implement their DEM algorithms. A hardware implementation of a generalised cube network (GCN) DEM DAC algorithm is described, and this implementation is shown to be more hardware efficient than other GCN-based DEM algorithms when used in DEM DACs with less than six bits.

Linearity enhancement of multibit ΔΣ A/D and D/A converters using data weighted averaging

A dynamic element matching algorithm, data weighted averaging, is introduced for use in multibit /spl Delta//spl Sigma/ data converters. Using this algorithm, distortion spectra from DAC linearity errors are shaped by first-order noise shaping, resulting in a dynamic range improvement of 9 dB/octave when DAC errors dominate. Combining this technique with random dithering nearly eliminates the aliasing of the DAC errors into the baseband. Simulations show that with only 1% element matching 110 dB signal-to-noise ratio (18 b) is achieved for a third-order 3-b modulator with an oversampling ratio of 128.