Dynamic Content Addressable Memory Research Articles

AIDA: Associative In-Memory Deep Learning Accelerator

This work presents an associative in-memory deep learning processor (AIDA) for edge devices. An associative processor is a massively parallel non-von Neumann accelerator that uses memory cells for computing; the bulk of data is never transferred outside the memory arrays for external processing. AIDA utilizes a dynamic content addressable memory for both data storage and processing, and benefits from sparsity and limited arithmetic precision, typical in modern deep neural networks. The novel in-data processing implementation designed for the AIDA accelerator achieves a speedup of 270× over an advanced central processing unit at more than three orders-of-magnitude better energy efficiency.

Dual bit control low-power dynamic content addressable memory design for IoT applications

The Internet of things (IoT) is an emerging area in the semiconductor industry for low-power and high-speedapplications. Many search engines of IoT applications require low power consumption and high-speed content addressablememory (CAM) devices for the transmission of data packets between servers and end devices. A CAM is a hardwaredevice used for transfer of packets in a network router with high speed at the cost of power consumption. In this paper,a new dual bit control precharge free (PF) dynamic content addressable memory (DCAM) has been introduced. Theproposed design uses a new charge control circuitry, which is used to control the dual DCAM cell to get the match lineoutput for match/miss. Elimination of the precharge phase before the evaluation phase allows the proposed design toperform more search operations within the evaluation time. The proposed 64-bit PF-DCAM design is implemented usinga CMOS 45-nm technology node and Monte Carlo simulations are performed for power and search delay validation. Thesimulation results show that the proposed design reduces power and search delay when compared to conventional DCAMdesigns.

Precharge free dynamic content addressable memory

A precharge free dynamic content addressable memory (DCAM) is introduced for low-power and high-speed search applications. Elimination of precharge prior to search allows hardware engine to perform more number of searches within the stipulated time. The proposed DCAM cell not only removes precharge of matchline (ML) but also utilises decoupling of bitline and searchline so that unwanted capacitive couplings are minimised at charge storage nodes. A 512 bit of the proposed scheme is implemented using 45 nm CMOS technology and its efficacy is verified and proved through rigorous variations with 1000-point Monte-Carlo sampling of ML voltage as well as multi-search dissipation analysis.

Metallic tube‐tolerant ternary dynamic content‐addressable memory based on carbon nanotube transistors

The design of a dynamic content-addressable memory (DCAM) cell using carbon nanotube (CNT) field effect transistors is explored. A four CNTFET design is presented and the functionality of a ternary DCAM cell using SPICE simulation is verified. Using an array of asymmetrically correlated tube technique, it is demonstrated how the presented design could be made functional even in the presence of metallic CNTs.

Decoupled dynamic ternary content addressable memories

The content addressable memory (CAM) is a memory in which data can be accessed on the basis of contents rather than by specifying physical address. In the paper, five novel dynamic ternary CAM cells with decoupled match lines are presented. A ternary CAM cell is capable of storing and matching three values: zero (0), one (1), and don't care (X). The proposed dynamic CAM (DCAM) cells range in the number of transistors from 6 n-type transistors up to 10.5 n- and p-type transistors (one transistor is shared between two cells). The cells are capable of fast match and read operations enhancing the performance of the memory system. Using a 0.25-/spl mu/m CMOS technology, simulations of the proposed CAM cells were performed to compare their performance. With this technology, the shortest match delay is 89.7 ps for the 7.5 DCAM cell. A complete characterization of the five cells is provided in this paper. These results show that the novel CAM cells outperform existing cells. The compact size and low power dissipation of these ternary CAM cells make them suitable for many applications such as routers, database, and associative cache memories.

A programmable dynamic interconnection network router with hidden refresh

A VLSI implementation of a programmable pipelined router scheme for parallel machine interconnection networks is presented in this paper. The implementation is based on a dynamic content-addressable memory (DCAM) that supports unique bit masking per entry. The number of required DCAM entries is extremely small; it is of the same order as the node degree (output ports). This, in turn, makes it possible to implement a dynamic content-addressable memory in order to reduce the physical size of the system. A DCAM is implemented with only six and a half transistors (one transistor is shared by two cells). We have provided circuitry and arranged timing to achieve refreshing of the stored data in a hidden fashion. In addition to the DCAM, we have incorporated a fast priority scheme that allows only one entry to he selected. The router executes routing algorithms in 1.5 clock cycles, this being the fastest approach for flexible routers. The prototype router has 24 entries, and is able to sustain a throughput of one routing decision per cycle.

Dynamic cross-coupled bit-line content addressable memory cell for high-density arrays

The design of a novel dynamic content addressable memory (CAM) cell suitable for high-density arrays is described. The proposed cell is capable of storing three internal states: ONE, ZERO, and `don't care' (MASK). The cell consists of five NMOS transistors of which four are used to store and access data and one is used as a diode to isolate current paths. Charge is stored on the gate of a transistor which results in nondestructive current-driven READ and MATCH operations and increases the charge storage time leading to higher reliability and improved immunization to alpha particles. Using 2-/spl mu/m design rules, buried contacts, single-level metal, and low-resistance polycide lines results in a CAM cell area of 25/spl times/22 /spl mu/m/SUP 2/, which is comparable to 64-kb static random access memory (RAM) cell areas. The CAM cell was successfully fabricated using a 4-/spl mu/m NMOS process and its operation was verified with a 2/spl times/3-bit array.