Dummy Patterns Research Articles

P‐90: Automatic Design Optimization Platform for FMM Mask Dummy Pattern Simulation Based on AMOLED Display Screen

In this paper, the automatic design optimization platform for FMM dummy pattern simulation based on AMOLED display screen has the advantages of short time, high precision, simple process and wide range of design combination. Specifically, the project simulation design time is reduced by half, the error rate in the simulation design process is reduced from 10% to 1%, the design combination range is increased by more than 10 times, and the FMM mask compensation accuracy is increased by 10%. Automated design optimization platform is helpful to improve product yield and save cost.

Effect of Oxide Thickness by Metallic Residue during Radical Oxidation Using Vertical Batch-Type Furnace Equipment on 300-Mm-Diameter Silicon Substrates

Metallic residues have a detrimental effects on device performance as well as retard gate oxide growth rate to induce unintended thinner oxide layer. In this study, we found that oxide thickness could be subjective to metallic residues on the edge of silicon substrate. Hydrogen-assisted radical oxidation was investigated using vertical batch-type furnace equipment for a 300-mm wafer fab. Radical oxidation has been used to improve gate oxide quality overcoming the disadvantages of conventional wet or dry thermal oxidation for some applications. Since the radical oxidation method reduces dangling bonds and defects in the oxide layer due to activated oxygen radicals, a high-quality oxide film can be formed. It also helps improve reliability due to reduced dependence on the silicon crystal direction of oxidation, enabling uniform membrane deposition of stress-focused corner rounding oxidation. In addition, it has excellent throughput as it is possible to process up to 100 wafers simultaneously. This study has shown that as the number of wafers with metallic residues in the dummy pattern on the edge due to the wafer edge exposure (WEE) difference for each photo step increases in the same batch for radical oxidation, the median thickness has decreased. When the silicon wafer with the metallic residue was included within the same batch of the furnace equipment, the thickness of the oxide layer was reduced by 1.8% compared to when the metallic residue-free silicon wafer was included. The radical oxygen have a tendency to react to tungsten rather than silicon, which reduces the O2 value required to form SiO2 and lowers the thickness, which is due to the difference in electronegativity between silicon and tungsten, 1.9 and 2.36 respectively. The study is expected to improve gate oxide quality by controlling metal residues on the wafer edge or backside during the fab process.

Optimal Dummy Pattern Design Method for PWB Warpage Control Using the Human-Based Genetic Algorithm.

In this work, a method that minimizes printed wiring board (PWB) warpage by dummy pattern design is proposed. This work suggests that dummy patterns are placed on a preset discretized location in the PWB to reduce the warpage. On each discretized candidate area, the dummy pattern can be set or unset. The warpage is numerically simulated based on direct modeling of the as-is PWB patterns to evaluate the warpage alongside the dummy pattern design set. The optimal pattern that minimizes warpage is determined using the human-based genetic algorithm where the objective function is evaluated by the structural simulation. The optimization method is realized in a spreadsheet that allows scripting language with which the input and output files of the simulation tool can be modified and read. Two different cases have been tested and the results show that the method can determine the optimal dummy patterns. The measured and simulated deflections agree well with each other. Moreover, it has been shown that certain dummy pattern designs that should reduce the warpage can be sought by the optimization.

A Dummy-Pattern-Assisted Lift-Off Method for Small and Dense Nanostructures

Nanostructures have attracted much attention because of wide application. Moreover, most of the nanostructures play the function through small and dense patterns in irregular shape, which indicates that the fabrication process is utmost important. In general, a lift-off process is used to transfer the pattern from resist to substrate. However, for small and dense patterns, the lift-off does not work well. In this paper, a dummy-pattern-assisted lift-off method is present. With added dummy patterns, a deep and thin valley forms on the resist but does not contact the substrate. The following deposited metal film may not fully cover the valley or form a weak connection in the valley. Therefore, the metal film is easily lifted off in the valley when the sample is dipped in the acetone, which could result in a successful lift-off. This novelty method is able to improve the quality of nanofabrication by lift-off process.

Optimization of Intense Pulsed Light Sintering Considering Dimensions of Printed Cu Nano/Micro-paste Patterns for Printed Electronics

An intense pulsed light (IPL) was irradiated for the sintering of screen-printed copper (Cu) nano/micro-paste patterns on a polyimide substrate. The pattern widths and intervals affect the sintering behavior owing to the opto-thermal relationship during IPL irradiation. The temperature histories of the patterns during the IPL sintering process were predicted using a self-developed heat transfer simulation program. By comparing the experimental and simulation results, the tendency according to the size of the Cu pattern was confirmed. At the same IPL irradiation energy, the wider the pattern and the narrower the interval between the patterns, the higher the heat generated. To demonstrate the tendency, in situ resistance monitoring of the Cu patterns was conducted and their microscopic structures were investigated using a scanning electron microscope. Through the tendency of IPL sintering according to the widths and intervals of the Cu pattern, guidelines of IPL sintering process for electrodes with multi-size pattern were suggested: A dummy pattern was added between the existing digitizer patterns to achieve uniform sintering in all regions. When IPL sintering was conducted with the dummy patterns, the uniformly sintered line resistance could be obtained in entire areas of the digitizer pattern.

A New Liftoff Method for Small and Dense Nanostructures

Introduction Nanostructures have unique properties which attract much attention and have a wide application. For example, metalens could replace the traditional optical components to develop a simple and effective optical system[1]. The key elements of AR and VR smart glasses are based on grating patterns with small dimension[2,3]. Nanostructures are mainly fabricated by electron beam lithography (EBL) which provides excellent patterning solution and flexible pattern variation[4,5]. After the EBL, nanostructures are transferred from the resist to the substrate by etching or liftoff. Because the resist is not a good hard-mask for dry etch and the nanostructures could be distorted during etching, a liftoff process is adopted for the nanostructures transfer[6]. Moreover, small and dense patterns in irregular shape are frequently designed in the nanostructures, so it becomes difficult to fabricate the nanostructures same as the designed-mask by a liftoff process. Therefore, a simple and effective liftoff method should be developed. Experiment A p type silicon wafer is used as the substrate, after the standard cleaning procedure (SC1, SC2, BOE), the wafer is baked at 180℃ for 10 mins. Following by the polymethyl methacrylate (PMMA) coating, the resist thickness is 230 nm. After coating, the wafer is baked at 150℃for 3 mins. The EBL with 80 KV acceleration voltage and a beam current of 9 nA is used. After the exposure, the sample is developed in a developer (IPA:MIBK=3：1) for 3 minutes. Then the wafer is dried by N2 gas. Results and Discussions The pattern used in the EBL is shown in Fig. 1 to explain the role of dummy pattern. Fig. 1(a) is the original mask pattern and the blue region is for exposure. A line of small square patterns with the dimension of 20 nm is added in the no-exposure region, as shown in Fig. 1(b) and (c). After exposure, a 70 nm Chromium (Cr) film is deposited on the PMMA by ebeam evaporator, as shown Fig. 2(a), following by a liftoff process in acetone for about 5 mins. Then the sample is cleaned in DI water and dried by N2 gas, as shown in Fig. 2(b). With dummy small patterns added on the liftoff region, after exposure and development, the dummy patterns could form a deep and thin valley on the resist but not contact the substrate. Following the metal deposition, the metal film may not fully cover the valley or form a week connection in the valley region. Therefore, the metal film is very easy to break in the valley when the sample is dipped in the acetone, which could results in a successful liftoff. However, the exposure dose for the dummy pattern should be tested to find the optimum value; otherwise, the dummy pattern could appear in the nanostructure, as shown in Fig. 2(c), and destroy the function of the nanostructure. Conclusions A new liftoff method is present. With dummy small patterns added to the original mask pattern, a deep and thin valley on the resist but not contact the substrate is formed. This method leads to a simple and effective liftoff process. Acknowledgements The research was founded by “Research and application on high dense nanopillar by electron beam lithography”(Grant no:JCYJ20170817105420497) References 1 J. Park, S. Bae, and K. Jeong, presented at the 2018 International Conference on Optical MEMS and Nanophotonics (OMN), 2018. 2 H. Raad, C. White, H. Schmitzer, D. Tierney, A. Issac, and A. Hammoodi, presented at the 2017 Progress in Electromagnetics Research Symposium - Fall (PIERS - FALL), 2017. 3 L. Silin, T. Shiqi, and X. Jinsong, presented at the 2016 Progress in Electromagnetic Research Symposium (PIERS), 2016 (unpublished). 4 H. Duan, D. Winston, J.K.W. Yang, B.M. Cord, V.R. Manfrinato, and K.K. Berggren,Sub-10-nm half-pitch electron-beam lithography by using poly(methyl methacrylate) as a negative resist Journal of Vacuum Science & Technology B 28, (2010) C6C58. 5 C. Nien, L.-C. Chang, J.-H. Ye, V.-C. Su, C.-H. Wu, and C.-H. Kuan,Proximity effect correction in electron-beam lithography based on computation of critical-development time with swarm intelligence Journal of Vacuum Science & Technology B 35, (2017) 6 M. Hatzakis, B.J. Canavello, and J.M. Shaw,Single-Step Optical Lift-Off Process IBM Journal of Research and Development 24, (1980) 452. Figure 1

Reversible integer wavelet transform for blind image hiding method.

In this article, a blind data hiding reversible methodology to embed the secret data for hiding purpose into cover image is proposed. The key advantage of this research work is to resolve the privacy and secrecy issues raised during the data transmission over the internet. Firstly, data is decomposed into sub-bands using the integer wavelets. For decomposition, the Fresnelet transform is utilized which encrypts the secret data by choosing a unique key parameter to construct a dummy pattern. The dummy pattern is then embedded into an approximated sub-band of the cover image. Our proposed method reveals high-capacity and great imperceptibility of the secret embedded data. With the utilization of family of integer wavelets, the proposed novel approach becomes more efficient for hiding and retrieving process. It retrieved the secret hidden data from the embedded data blindly, without the requirement of original cover image.

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

A thorough investigation of the parasitic resistance and capacitance (RC) effects of a single-fin FinFET on logic CMOS devices and circuits is presented. As parasitic RC effects become increasingly prominent in nanoscaled FinFET technologies, they are critical to the overall device and circuit performance. In addition, the effects of dummy patterns as well as multifin structures are analyzed and modeled in detailed. By incorporating parasitic resistance and capacitance extracted by both measurement and simulation, the static and dynamic performance characteristics of standard six transistor static random-access memory (6T-SRAM) cells are comprehensively evaluated as an example of parasitic RC effects in this investigation.

Electron beam lithography patterned hydrogen silsesquioxane resist as a mandrel for self-aligned double patterning application

The semiconductor industry has developed various alternative approaches for obtaining high resolution patterns (sub-30 nm) using existing lithography techniques. Of the alternative approaches, self-aligned double patterning (SADP) is the approach which involves the fewest lithography steps. In SADP, a dummy pattern, also known as a mandrel, is first formed, followed by a conformal spacer material deposited on the patterned mandrel. Using dry reactive ion etching, spacer sidewalls are then formed. In the final step, the mandrel is removed by an etch process. The result is the double pattern of the spacer material. The advantage of this approach is that only one lithography step with the critical dimension of the double patterns is defined by the deposited spacer thickness. The disadvantage is the requirement of multiple, successive deposition and etch processes. In the present research, the authors demonstrate a reduction in required processing steps by using a novel mandrel/spacer approach for the SADP scheme. Using electron beam lithographically patterned hydrogen silsesquioxane resist and plasma enhanced chemical vapor deposition deposited low stress silicon nitride, the authors demonstrate a proof of concept of the SADP patterning scheme with reduced process steps.

(Invited) Pattern and Emissivity Insensitive Dopant Activation and Silicide Contact Formation Annealing in a Hot Wall Rapid Thermal Annealing System

Rapid thermal annealing (RTA) enabled shallow junction formation requires very short time annealing at high temperatures for low thermal budget. RTA is typically done by lamp-based radiant heating. Radiant power from lamp arrays is close-loop controlled to execute the temperature of the Si wafer as programmed. The increase of annealing temperature and the decrease of annealing time are generally required for more aggressive device scaling. However, the use of non-equilibrium radiant heat sources (photon energy from lamp arrays) makes the heating process sensitive to the optical properties of the Si wafers. Local temperature non-uniformity during RTA is considered an important contributor for within-die process variations which cause significant problems for advanced complimentary metal-oxide-semiconductor (CMOS) device manufacturing. RTA-induced variations strongly depend on circuit layout patterns and optical properties of exposed materials on the surface of the Si wafers. This phenomenon is often referred to as “pattern effect” known from the early days of RTA introduction in the semiconductor industry. In efforts to reduce the “pattern effect”, various approaches have been proposed and implemented in device manufacturing. Shielding device patterns from the radiant heat source is a common approach, having limited success. It is done by either placing a dummy wafer on the pattern side of the Si wafer or backside heating. One other common approach is to homogenize the optical properties of the pattern side of Si wafer by either adding an optical absorption layer or dummy patterns. A differential thermal energy control technique is also proposed for pattern effect suppression. Non-radiative heating techniques have been proposed and demonstrated effectiveness of this “pattern effect” suppression. In this paper, various silicide contact formations on implanted single crystalline Si in source/drain region and implanted poly-Si in gate region were studied over wide ranges of RTA temperature and time using a hot wall RTA system which uses mainly natural convection and conduction through ambient gas. Dopant profiles of the silicide and doped Si after silicidation in the hot wall RTA system were characterized. Proposed possible silicide formation and dopant diffusion mechanisms are discussed. Differences between radiant heating and non-radiant heating on the silicide formation and dopant profiles are compared. The pattern and emissivity insensitive dopant activation and silicide contact formation annealing results will be introduced and potential applications of the hot wall RTA technique in advanced CMOS devices will be proposed.

Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware Dummification

Extreme ultraviolet (EUV) flare and post-chemical mechanical polishing (CMP) metal thickness are two main manufacturability concerns that introduce critical dimension distortions in nanometer process technology. Dummification, the addition of dummy patterns, is an effective technique to address the two concerns. However, while the two dummification objectives are competing in nature, existing works only tackle them separately, leading to problem-prone solutions because optimizing one would unavoidably deteriorate the other. This paper presents a new and effective method that simultaneously considers both concerns during dummification. Manufacturing sensitivity toward the two concerns are taken into account with a user-specified evaluation model adaptive to the adopted technology. Given the point spread function of a system and the evaluation model, our proposed two-stage method is able to find at the first stage an initial dummy assignment with better EUV flare uniformity than that obtained by a previous quasi-inverse method. With the initial assignment as the starting point, the gradient-guided optimization is then adopted to iteratively refine dummy distribution toward improved CMP quality. Experimental results on industrial test cases show the effectiveness of our method.

Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods

Although self-aligned double and quadruple patterning (SADP, SAQP) have promising processes for sub-20 nm node advanced technologies and beyond, not all layouts are compatible with them. In advanced technologies, feasible wafer image should be generated effectively by utilizing SADP and SAQP where a wafer image is determined by a selected mandrel pattern. However, predicting a mandrel pattern is not easy since it is different from the wafer image (or target pattern). In this paper, we propose new routing methods for spacer-is-dielectric (SID)-type SADP, SID-type SAQP, and spacer-is-metal (SIM)-type SADP to generate a feasible layout satisfying the connection requirements. Routing algorithms comprising simple connecting and cutting rules are performed on a new grid structure where two (SID-type SADP) or three colors (SID-type SAQP and SIM-type SADP) are assigned alternately to grid-nodes. Then a mandrel pattern is selected without complex coloring or decomposition methods. Also, we try to reduce hotspots (potentially defective regions) by the proposed dummy pattern flipping for SID-type SADP. In experiments, feasible layouts meeting the connection requirements are generated and the effectiveness of the proposed framework is confirmed.

Process Optimization of Integrated SiCr Thin-Film Resistor for High-Performance Analog Circuits

We investigated the characteristic variation of an integrated thin-film resistor (TFR), which is composed of silicon chromium (SiCr), according to process conditions and its effects on analog circuits. To improve TFR properties, such as temperature coefficient of resistance (TCR) and mismatch, the integrated TFR was examined under various process conditions. First, the sputtering power and the annealing temperature were optimized to control the TCR property. Secondly, the etching time and the dummy pattern were optimized to enhance the mismatch property. The measured TCR is -3.9 ppm/ <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C and the calculated mismatch slope from the standard deviation of resistance mismatch is 0.34%·μm. These results show that the fabricated TFR had near-zero TCR and a high matching constant. To verify the TFRs effects on analog circuits, low-pass filters (LPFs) were fabricated and measured as a test vehicle; the use of the optimized resistor considerably improved the performance of the resulting LPFs.

Patterning of Si nanowire array with electron beam lithography for sub-22nm Si nanoelectronics technology

In order to form practical arrays of Si nanowires narrower than 22nm using electron beam lithography (EBL) with hydrogen silsesquioxane (HSQ) resist and reactive ion etching (RIE) process with inductively-coupled plasma, a new type of lithography/etching interaction is studied. The inter-pattern electrostatic repulsion appears to determine the patterning limit to be 28nm while causing the RIE dummy patterns to collapse. Approaches to reduce the electrostatic force on the RIE dummies are tried from design and process perspectives. Designing additional dummy patterns next to the RIE dummies and fixing pattern-to-pattern distance to be 70nm are tried. Another efficient approach is to use thinner HSQ resist to reduce the repulsion among patterns. Here we confirm that the nanowire patterns narrower than 20nm can be formed by using diluted HSQ solutions.

1-D Cell Generation With Printability Enhancement

As process technologies advance to the subwavelength era, the 1-D design style is regarded as one of the most effective ways to continue scaling down the minimum feature size. To improve the printability of 1-D cell design, it is essential to insert dummy patterns and optimize line-end gap distribution for each layer. This paper presents novel 1-D cell generation algorithms that simultaneously minimize 1-D cell area and enhance the printability. Experimental results show that the proposed algorithms can effectively and efficiently reduce the number of diffusion gaps, minimize used routing tracks, insert sufficient dummy patterns, and eliminate stage-like line-end gaps without power and timing overhead. Consequently, the 1-D cell area is minimized and the printability of the cell is enhanced. To the best of our knowledge, this is also the first work in the literature that considers line-end gap distribution during 1-D cell generation.

Analysis and modeling of the optical endpoint signal for precision etching

Endpoint detection is an essential methodology for process control in dry etching for modern semiconductor manufacturing technology. In this paper, an analysis has been performed on the factors, such as the local etch rate, the local film thickness differences, and the open area and the global uniformities of the etch rate and film thickness, affecting the change in the optical emission endpoint signals on a patterned device wafer. Also, a model of the endpoint signal evolution, which includes an effective open ratio, the ratio of the relative open area after considering the local difference in the etch rate and the film thickness to the total open area at the very beginning of the etch process, has been established. Compared to the conventional open ratio, which is the ratio derived from the reticle used for lithography, the effective open ratio is better in explaining and predicting the endpoint signal change. The effective open ratio can be used to design dummy patterns that are used to improve endpoint detection in critical dry etch processes such as gate cuts in logic gate formation, etc.

Characterization of Fogging and Develop-Loading Effects in Electron-Beam Direct-Writing Technology

We investigated long-range critical dimension (CD) error factors, such as fogging and develop loading, to improve CD uniformity in electron-beam direct-writing (EBDW) technology. It was found that the impact of both effects reached 20 mm and the CD of the monitor pattern decreased by no less than 10%. Fogging and develop loading were separated by comparing the newly designed test patterns that were exposed using both EB and a krypton-fluoride excimer laser. We confirmed that the impact of fogging and develop loading by arranging dummy patterns with a density of 40% was estimated to be +8.9 and -18.9% in the CD, respectively. Based on success in separating each effect, fogging and develop loading were decreased by applying an antistatic agent and multipuddle development, respectively.

The L28 STI CMP Dummy Pattern Study on Topography for Advanced Fixed Abrasive and High Selective Slurry

The STI CMP performance was major determined by the uniformity of STI step height which was characterized by the ranges of within-die (WID) and within-wafer (WIW) thickness for both silicon nitride and trench oxide surface of isolation area. Currently, for 28nm generation, two advanced approaches for STI CMP were high selective slurry (HSS) and fixed abrasive (FA) CMP. For these two approaches, the design and layout of dummy were important to overcome the effect of various pattern densities and feature sizes. Therefore this research focused on the effect of dummy type for HSS and FA CMP. The result shows HSS CMP is the most robust process in STI CMP. The nitride thickness after HSS CMP shows good uniformity, 2~3 %, and is slightly affected by dummy type and PD of test key comparing with FA CMP.

The L28 STI CMP Dummy Pattern Study on Topography for Advanced Fixed Abrasive and High Selective Slurry CMP Processes

not Available.

A Study of Flare Variation in Extreme Ultraviolet Lithography for Sub-22 nm Line and Space Pattern

One of the critical issues in extreme ultraviolet lithography (EUVL) is flare, which is an integrated light scattering from surface roughness in the EUVL optical system. Flare degrades the control of critical dimension (CD) uniformity across the exposure field. Also, it generates larger CD sensitivity as line and space (L/S) half pitch size decreases. Therefore, we discussed the calculation of accurate flare maps to compensate for flare variation. The influence of three-dimensional (3D) mask topography on flare was investigated with different absorber thicknesses, off-axis illumination angles, and azimuthal angles. Some types of dummy patterns were found to be effective in controlling the flare variation within a L/S patterned target and the average flare of a L/S patterned target. Our studies has definitely made progress in an effective flare variation compensation using a rule-based correction for sub-22 nm L/S half pitch node and beyond.