Dummy Chips Research Articles

Study on the Manufacturability of XDFOI Package with Organic RDLs (XDFOI-O)

The concept of chiplet has been proposed in the post Moore era, while how to achieve the layout of multiple chips of different processes and sizes in the manufacturing process is a coming problem that needs to be considered. Different layouts may significantly affect the manufacturability during the packaging process. Prospective finite element analysis (FEA) can evaluate various layouts by optimizing the layout and increasing the placement of dummy chips as stiffeners, thereby selecting the best layout and combination method. In addition, the characteristic of chiplet packaging is that multiple chips may come from different sources, such as different foundries, processes, sizes, or even thicknesses. This really poses challenges to the subsequent flip chip and wafer thinning process for leveling the total package. It is necessary to confirm the evaluation of the impact of chips with different thicknesses and underfill coverage in the process, so as to ensure the consistency in processing and improve the yield of packages.

Study on the Manufacturability of X Dimension Fan Out Integration Package with Organic RDLs (XDFOI-O)

The concept of chiplet was proposed in the post- Moore era. How to layout the multiple chips with different processes and sizes in the package structure is a problem that needs to be considered as different layouts may significantly affect the manufacturability during the packaging process. XDFOI-O is a 2.5D organic interposer structure with a significant coefficient of thermal expansion mismatch in it. Different layouts may cause excessive stress concentration in the package structure, as well as large wafer warpage, which can affect the normal operations of the production line. Stress accumulation on specific chiplet during the wafer thinning process is another manufacturability problem, leading to chip cracking. Prospective finite element analysis can be applied to evaluate the various layouts. In simulation work, different placement processes of dummy chips as stiffeners, as well as different chiplet thicknesses and underfill coverage, can be used as factors for simulation studies, thereby making a reference for further chiplet package design.

ALICE ITS 3: the first truly cylindrical inner tracker

The high integration density of MAPS, with silicon sensor and readout electronics implemented in the same device, allows very thin structures with a greatly reduced material budget. Thicknesses of (50 μm), values at which silicon chips become flexible, are readily used in many applications. In addition, MAPS can be produced in sensors of wafer size by a process known as stitching. This in turn allows to build detector elements that are large enough to cover full tracker half-layers with single bent sensors. The ALICE ITS 3 project is planning to build a new vertex tracker based on truly cylindrical wafer-scale sensors, with <0.05% X/X0 per layer and located as close as 18 mm to the interaction point. R&D on all project aspects (including mechanics for bent wafer-scale devices, test beams of bent MAPS, design of stitched sensors) is rapidly progressing with the aim for installation during LHC long shutdown 3 (2025–2027). This contribution summarises the project motivation, its R&D schedule, and will show selected highlights of recently accomplished project milestones, including full-scale engineering prototypes with dummy chips and small-scale, fully functional assemblies of functional, bent MAPS.

Evaluating thermoset resin substrates for 3D mechatronic integrated devices and packaging

AbstractMiniaturization efforts and increasing demands regarding reliability of mechatronic systems require new materials and processes for the 3D mechatronic integrated devices (3D-MID) technology. Currently, in the area of 3D-MID mostly thermoplastic materials are in use in the industry, which are metallized using the LPKF-LDS® process. This paper is supposed to demonstrate the eligibility of thermoset resins as a new material class for 3D-MID applications and as a packaging option for silicon chips which are currently encapsulated using transfer molding of thermosets. The reliability of the conductor tracks made using a LDS-additive free process as well as the adhesion forces are investigated. Different laser parameters for structuring of two different substrate materials are compared. For reliability testing a thermal shock test is applied. Furthermore, the adhesion is tested using Hot-Pin-Pull testing. The conductor tracks surpass 2000 cycles thermo-mechanical load without showing strong deterioration of the track resistivity. The incorporated approach enables electrically reliable functionalization of packaged dummy chips including vias for connection to terminals on the chips. The results of the tested injection moldable thermoset resins are comparable to state-of-the-art 3D-MID thermoplastic substrates and thus, suited as circuit carrier material in electronic packaging.

Reliability analysis of sintered Cu joints for SiC power devices under thermal shock condition

In this study, the thermal shock reliability of sintered Cu joints on SiC power device application was investigated. Firstly, sintered Cu joints were used to bond chips and substrate consisting of various materials to evaluate their bondability. Secondly, SiC dummy chips were bonded to DBC substrate and thermal shock test from −40 °C to 250 °C were performed both in the ambient atmosphere and in vacuum. Finally, the SiC MOSFETs bonded by sintered Cu joints were evaluated by power cycle test from 25 °C to 200 °C and the thermal conductivity was evaluated by T3ster equipment. The results showed the sintered Cu exhibited extremely high reliability during the thermal shock aging test in ambient atmosphere although inferior reliability was observed in vacuum. This phenomenon was investigated and explained by field-emission scanning microscope, energy-dispersive X-ray spectroscopy, and X-ray diffractometer.

Mechanical property and reliability of bimodal nano-silver paste with Ag-coated SiC particles

Purpose This study aims to develop a bimodal nano-silver paste with improved mechanical property and reliability. Silicon carbide (SiC) particles coated with Ag were introduced in nano-silver paste to improve bonding strength between SiC and Ag particles and enhance high-temperature stability of bimodal nano-silver paste. The effect of sintering parameters such as sintering temperature, sintering time and the proportion of SiC particles on mechanical property and reliability of sintered bimodal nano-silver structure were investigated. Design/methodology/approach Sandwich structures consist of dummy chips and copper substrates with nickel and silver coating bonded by nano-silver paste were designed for shear testing. Shear strength testing was conducted to study the influence of SiC particles proportions on the mechanical property of sintered nano-silver joints. The reliability of the bimodal nano-silver paste was evaluated experimentally by means of shear test for samples subjected to thermal aging test at 150°C and humidity and temperature testing at 85°C and 85 per cent RH, respectively. Findings Shear strength was enhanced obviously with the increase of sintering temperature and sintering time. The maximum shear strength was achieved for nano-silver paste sintered at 260°C for 10 min. There was a negative correlation between the proportion of SiC particles and shear strength. After thermal aging testing and humidity and temperature testing for 240 h, the shear strength decreased a little. High-temperature stability and high-hydrothermal stability were improved by the addition of SiC particles. Originality/value Submicron-scale SiC particles coated with Ag were used as alternative materials to replace part of nano-silver particles to prepare bimodal nano-silver paste due to its high thermal conductivity and excellent mechanical property.

Fabrication of Ni–P coating film on diamond/Al composite and its soldering reliability

Although the diamond/Al composite is a good heat sink material due to its high thermal conductivity and low cost, its surface cannot be wetted directly for microelectronic packaging. Using modified electroless plating procedures and recipes, a glossy, continuous, and uniform Ni–P film was successfully fabricated on the diamond/Al composite surface for the first time with a bonding strength of 15.1 MPa. This Ni–P coating layer is solderable for both lead-free SAC305 and Sn63Pb37 alloys on Cu dummy chips. A continuous intermetallic compound (IMC) layer was formed at the interface without any crack or void defects, and the shear strength of both solder joints was in the range of 39.9–41.2 MPa. During thermal storage tests, the growth of IMC was slow at 125 and 150 °C, but it elevated sharply at 175 °C. According to growth kinetics analyses, a Ni element can hinder IMC growth. The diffusion activation energy (Q) of (Cu,Ni)6Sn5 was calculated as 62.6 kJ/mol in SAC305 and 97.7 kJ/mol in Sn63Pb37 solder joints. Both microstructures and mechanical properties of the solder joint using the Ni–P coated diamond/Al composite can satisfy the requirement of microelectronic industrial applications.

Thermal Fatigue Behavior of Silicon-Carbide-Doped Silver Microflake Sinter Joints for Die Attachment in Silicon/Silicon Carbide Power Devices

We studied the thermal fatigue behavior of submicron silicon carbide particle (SiCp)-doped silver (Ag) microflake sinter joints for die attachment in next-generation power devices. Si dummy chips and direct bonded copper substrates with various metallization schemes were bonded using SiCp-doped Ag microflakes under mild conditions (250°C, 30 min, 0.4 MPa). The SiCp was distributed homogeneously in the porous Ag network and inhibited morphological evolution during thermal cycling tests. The shear strength of as-sintered pure Ag and SiCp-added joints was ∼50 MPa and 35 MPa, respectively. Thermal cycling tests from −40°C to 250°C were conducted for up to 1000 cycles (hours) to characterize the thermostability of the bonded joints. After 1000 cycles, joints with and without SiCp experienced bonding degradation, with shear strength of ∼25 MPa and 20 MPa, respectively. Thus, after 1000 cycles, the shear strength of pure Ag and SiCp-doped joints decreased by 58% and 42%, respectively, compared with their maximum value. Coarsening of porous Ag occurred in pure Ag joints. SiCp addition inhibited morphological evolution of SiCp-doped joints during thermal cycling. However, vertical cracks generated by thermal stress were observed in joints both with and without SiCp, which may limit long-term reliability.

Study on high temperature bonding reliability of sintered nano-silver joint on bare copper plate

Nano-silver paste has become an alternative lead-free (Pb-free) die attach material for microelectronic packaging, compared to traditional solders and adhesive films, due to its higher thermal and electrical conductivity, higher temperature operation and higher heat dissipation. In this study, the reliable joints of sintered nano-silver paste on bare copper plate with large-area dummy chips were introduced and thermally aged at 150°C, 180°C, or even higher than 250°C in air or in a coarse vacuum environment. The bonding strength and interfacial reaction were investigated. The results showed, after aging specimens at 150°C for 960h in air or at 250°C for 960h in a coarse vacuum, the interfaces between the sintered nano-silver and bare copper still consisted of simple inter-diffusion bands and with almost no change in bonding strength. However, the bonding strength sharply decreased to 50% after aging at 180°C for 72h in air and it decreased to 20% after aging at 250°C for 72h in air. The decrease in bonding strength was mainly attributed to the oxidation of copper at relative elevated temperature in this work.

Addition of SiC Particles to Ag Die-Attach Paste to Improve High-Temperature Stability; Grain Growth Kinetics of Sintered Porous Ag

To improve the high-temperature reliability of sintered Ag joints, three types of silicon carbide particle (SiCp) of different size and morphology were added to Ag micron-flake paste. Quality sintered joints between Cu dummy chips and Cu substrate were obtained at a relatively low temperature (250°C), in air, under low load (0.4 MPa), and 35 MPa die-shear strength was achieved. High-temperature stability was investigated by means of aging tests at 150, 200, and 250°C for 500 h, and by thermal cycling between −50°C and 250°C for up to 170 cycles. The best distribution and compatibility with porous sintered Ag structures was observed for sub-micron SiC particles with an average diameter of 600 nm. After high-temperature storage for 500 h at 250°C, mean Ag grain size of the SiC-containing joints was unchanged whereas that for pure sintered Ag increased from 1.1 to 2.5 μm. Ag joints containing the optimum amount (2 wt.%) of SiCp retained their original strength (20 MPa) after storage at 250°C for 500 h. The shear strength of Ag joints without added SiCp decreased from 27 to 7 MPa after 500 h because of grain growth, which obeyed the classical parabolic law. Grain growth in pure Ag joints is discussed in terms of a temperature-dependent exponent n and activation energy Q. Our SiCp-containing joints resisted the grain growth that induces interfacial cracks during thermal cycling.

Thermal Characterization of Both Bare Die and Overmolded 2.5-D Packages on Through Silicon Interposers

The next generation of heterogeneous integration requires 2.5-D packages on through silicon interposer (TSI) as enabling technology for less signal delay, faster speed, and more functionality. In the meantime, the introduction of multiple chips on interposer tends to increase the heat density with added interconnect complexity, which requires systematic thermal analysis and characterization. In this paper, thermal characterization of 2.5-D packages on TSI is reported in both bare-die package and overmolded package formats. The test vehicle consists of two dummy chips and thermal test die assembled on the same interposer of 18 mm × 18 mm × 0.1 mm through the flip chip bumping and joining process. A thermal test chip of 5.08 mm × 5.08 mm is built in with heaters and diodes for thermal characterization. Thermal measurements are conducted for thermal resistances from junction to the ambient, from junction to the board, and from junction to top casing. Measurement accuracy is improved through distributed through silicon via network, multidie temperature monitoring and uncertainty analysis and minimization. It is found that the overmolded package has lower thermal resistances than the bare die package. In addition, the thermal resistance from the junction to the casing is also characterized with a liquid-cooled minichannel cold plate as heat sink, indicating the vast difference between bare die package and molded package. Besides experimental measurements, thermal simulation models under different boundary conditions are established, respectively, to compare with the measurements. Good agreements are generally achieved between simulation and measurements. Further simulation is also conducted to examine the effects of overmold thickness and power dissipation from the multichips module on the interposer.

Development of n-in-p silicon planar pixel sensors and flip-chip modules for very high radiation environments

Abstract In this paper we present RD small diodes were employed to investigate the width from the active diode to the dicing edge and the guard rings. Tests involving the diodes showed that the strong increase of leakage current was attributed to the edge current when the lateral depletion zone reaches the dicing edge and the lateral depletion along the silicon surface was correlated with the ‘field’ width. The onset was observed at a voltage of 1000 V when the width was equal to ∼400 μm. The pixel sensors that were diced at a width of 450 μm could successfully maintain a bias voltage of 1000 V. Hybrid flip-chip pixel modules with dummy and real chips were also fabricated. Lead (PbSn) solder bump bonding proved to be successful. However, lead-free (SnAg) solder bump bonding requires further optimization.

Evaluation of test methods for silicon die strength

The objective of this study is to evaluate the existing test methods of die strength, including widely-accepted three-point and four-point bending tests, and a newly-proposed point-load test by testing silicon die specimens with different surface conditions. It has been reported that there are three factors to influence die strength: the surface conditions of the die (including grinding-mark direction and surface roughness), the edge crack of the die (so-called chipping created during the cutting process), and the weak planes of the crystal lattice of silicon on (1, 1, 0) and (1, −1, 0). In this study, the focus will be on how these factors affect the strength data from these three test methods. Apart from performing these three tests, the roughness of the die surfaces (including the ground, polished and untreated surfaces) measured by atomic force microscopy, and edge chipping conditions by optical microscopy were correlated with strength data obtained from the tests. It was found that the four-point bending test gives the lowest strength data and its independence on the surface condition, due to much domination by the edge chipping. On the other hand, the three-point bending test provides intermediately high strength data, with slight difference between different surface conditions, and some major control by the edge chipping. It was also observed that both bending tests suffer the effect of the grinding-mark direction. By contrast, the point-load test associated with the applied force-maximum stress equation which is proved to be valid for Hertzian contact and, sometimes, required to take into account geometrically nonlinear effect, gives the highest values of strength among these methods. This test not only provides the data which are merely dependent on the surface roughness and free from the edge chipping and grinding-mark direction effects, but also it gives a bi-stress field similar to the temperature loading and provides direct test for dummy or real IC chips. As a result, the point-load test is one of the most adequate test methods for determining the die strength exclusively due to surface roughness effect.

Testing and Evaluation of Silicon Die Strength

In the applications of 3-D packages or stacked die packages, mostly the silicon wafers have to be ground thinner, and then the strengths of the dies from the wafers are needed for assuring good design and reliability of the packages. The purposes of this study are twofold: one is to attempt to develop a new, suitable test method for differentiating the factors that affect the variability of die strength, and the other is to investigate the failure and fatigue strengths of silicon dies. In this paper, a new test method, a plate-on-elastic-foundation test (PEFT) associated with point- or line-loading has been proposed and evaluated. It is found that the PEFT can provide not only a simple, chipping-free test for dummy or real IC chips without limitation of size, but also a (bi-axial) stress field similar to the temperature loading. The strength data of failures on IC and ground surfaces in real IC chips are presented. The good consistency of the die strength data with a minor scatter from both the point- and line-load tests is found for the specimens failed on IC surfaces, but not for the ones failed on the ground surfaces. The inconsistency of strength data from both tests for failure on ground surfaces is due to edge chipping involved. The large scatter is caused by the combined factors of the angle of grinding marks, planes of weakness of material, and loading stress states with uni-axial stress for line-load test and with unequal bi-axial stress for point-load test of rectangular specimens. The surface roughness of the dies (including the IC and ground surfaces) measured by atomic force microscopy is correlated with the failure modes and strengths from the tests. It is found that the silicon die strengths are dominated by the roughness on failure surfaces, and their failure modes always appear cracks along the directions parallel and normal to the edges of the die, which might be the weak plane of the crystal lattice of silicon. The specimens with artificial cracks have been further tested. It has been proved that the die strength dominated by the crack initiation depends on the most severe defect but not on the amount of the defects, and its failure mode is controlled by a special weak plane after the crack initiation. Conclusively, there are four factors to influence die strength: the surface conditions of the die (including grinding-mark direction and surface roughness), the edge crack of the die (so-called chipping created during the cutting process), the weak planes of the crystal lattice of silicon, and, sometimes, different tests with various loading conditions. The fatigue strength of the die is also determined to be about 25% lower than the static one.

Test Methods for Silicon Die Strength

Recently, the 3D or stacked-die packages become increasingly popular for packaging ICs into a system or subsystem to satisfy the needs of low cost, small form factor, and high performance. For the applications of these packages, IC silicon wafers have to be ground to be relatively thin through the wafer-thinning processes (such as grinding, polishing, and plasma etching). The strength of dies has to be determined for the design requirement and reliability assurance of the packages. From the published data, there still exist some issues, including a large scatter existed in die strength data and difficulties in differentiating the causes of the low strength between from the wafer grinding and from wafer sawing by either the three-point bending or four-point bending test. The purposes of this study are to develop new, reliable, and simple test methods for determination of die strength, in order to improve the data scatter, and to provide a solution for differentiating the factors that affect the variability of die strength for finding out the causes of the weakness of the die strength. In this study, two new test methods, point-loaded circular plate with simple supports test (PLT-I) and point-loaded plate on elastic foundation test (PLT-II), are proposed and then evaluated by testing two groups of silicon dies with different surface conditions. The surface conditions (roughness) of the specimens are determined by atomic force microscopy and correlated to failure strength. The failure forces from both tests have to be modified by using maximum stress obtained from theories or finite element analyses to obtain the failure strength. The test results are compared to each other and further with a widely used four-point bending test. The results suggest that, unlike the four-point bending test suffering the chipping effect, both methods provide very consistent data with a small scatter for each group of specimens and can be used for identifying the effect of surface grinding (roughness) on the die strength. It is also shown that the die strength is highly dependent on the surface roughness. Accordingly, these two methods can provide not only a (biaxial) stress field similar to temperature-loaded die in the packages, but also simple, feasible, reliable, and chipping-free tests for silicon dies of dummy or real IC chips, without strict geometrical limitation, such as beam-type geometry for the three-point or four-point bending test.