Dual-processor Architecture Research Articles

Energy Management for Fault-tolerant (m,k)-constrained Real-time Systems That Use Standby-Sparing

Fault tolerance, energy management, and quality of service (QoS) are essential aspects for the design of real-time embedded systems. In this work, we focus on exploring methods that can simultaneously address the above three critical issues under standby-sparing. The standby-sparing mechanism adopts a dual-processor architecture in which each processor plays the role of the backup for the other one dynamically. In this way, it can provide fault tolerance subject to both permanent and transient faults. Due to its duplicate executions of the real-time jobs/tasks, the energy consumption of a standby-sparing system could be quite high. With the purpose of reducing energy under standby-sparing, we proposed three novel scheduling schemes: The first one is for (1, 1)-constrained tasks, and the second one and the third one (which can be combined into an integrated approach to maximize the overall energy reduction) are for general ( m,k )-constrained tasks that require that among any k consecutive jobs of a task no more than ( k - m ) out of them could miss their deadlines. Through extensive evaluations and performance analysis, our results demonstrate that compared with the existing research, the proposed techniques can reduce energy by up to 11% for (1, 1)-constrained tasks and 25% for general ( m,k )-constrained tasks while assuring ( m,k )-constraints and fault tolerance as well as providing better user perceived QoS levels under standby-sparing.

An efficient control flow validation method using redundant computing capacity of dual-processor architecture

Microprocessors in safety-critical system are extremely vulnerable to hacker attacks and circuit crosstalk, as they can modify binaries and lead programs to run along the wrong control flow paths. It is a significant challenge to design a run-time validation method with few hardware modification. In this paper, an efficient control flow validation method named DCM (Dual-Processor Control Flow Validation Method) is proposed basing on dual-processor architecture. Since a burst of memory-access-intensive instructions could block pipeline and cause lots of waiting clocks, the DCM assigns the idle pipeline cycles of the blocked processor to the other processor to validate control flow at run time. An extra lightweight monitor unit in each processor is needed and a special dual-processor communication protocol is also designed to schedule the redundant computing capacity between two processors to do validation tasks better. To further improve the efficiency, we also design a software-based self-validation algorithm to help reduce validation times. The combination of both hardware method and software method can speed up the validation procedure and protect the control flow paths with different emphasis. The cycle-accurate simulator GEM5 is used to simulate two ARMv7-A processors with out-of-order pipeline. Experiment shows the performance overhead of DCM is less than 22% on average across the SPEC 2006 benchmarks.

Development of high synchronous acquisition accuracy wireless sensor network for machine vibration monitoring

Vibration-based condition monitoring is an important approach to ensure the reliability of industrial machines. On the one hand, traditional wired monitoring systems exhibit certain limitations in specific cases. Wireless sensor networks (WSNs), on the other hand, have excellent potential to avoid these constraints. However, there are still some problems that remained to be solved, such as high sampling rate and synchronous acquisition. In the present study, a machine vibration monitoring system based on WSNs has been developed and presented. Firstly, a wireless sensor node with dual-processor architecture is designed to balance cost, power consumption and performance. Then, in order to improve the accuracy of synchronous acquisition, a novel solution based on hardware cross-layer design is adopted. Lastly, experiments of the proposed node are performed and the effectiveness of the proposed machine vibration monitoring system is validated. The results show that the mean value of synchronous triggering error is reduced to 87.85ns.

An asymmetric dual-processor architecture for low-power information appliances

As users become increasingly conscious of their energy footprint—either to improve battery life or to respect the environment—improved energy efficiency of systems has gained in importance. This is especially important in the context of information appliances such as e-book readers that are meant to replace books, since their energy efficiency impacts how long the appliance can be used on a single charge of the battery. In this article, we present a new software and hardware architecture for information appliances that provides significant advantages in terms of device lifetime. The architecture combines a low-power microcontroller with a high-performance application processor, where the low-power microcontroller is used to handle simple user interactions (e.g., turning pages, inking, entering text) without waking up the main application processor. We demonstrate how this architecture is easily adapted to the traditional way of building user interfaces using a user interface markup language. We report on our initial measurements using an E Ink-based prototype. When comparing our hybrid architecture to a simpler solution we found that we can increase the battery life by a factor of 1.72 for a reading task and by a factor of 3.23 for a writing task. We conclude by presenting design guidelines aimed at optimizing the overall energy signature of information appliances.

A real-time system for power quality testing

This paper presents a real-time system that can be used for quick and reliable power quality testing. The system is based on a dual-processor architecture with a digital signal processor (DSP) interfaced to a personal computer (PC). Real-time tasks are delegated to run on the optimized hardware of the DSP board, while system-level requirements are handled by the PC. The real-time processing (RTP) kernel implemented on the DSP supports multitasking to handle tasks associated with data collection, data analysis, and interprocessor communication. The results of real-time analysis are presented in the PC through a menu-driven, graphical interface. Tests show that the system complies with IEC standards for power quality monitoring. This system offers many significant advantages. Real-time analysis of acquired data significantly reduces storage requirements. Data analysis algorithms can be modified to suit specific testing needs. Test results available in the PC can be exported to other computer analysis tools. The system is portable and holds promise as a powerful, low-cost tool for practising power quality engineers.

A digital signal processor for digital audio use

The authors describe the D/sup 2/SP digital signal processor which is designed with a dual processor architecture, and is especially effective for stereo audio signal processing. The D/sup 2/SP has two independent processor units, the left processor and right processor. The D/sup 2/SP contains an audio data interface, external dynamic random-access memory (DRAM) interface, microcomputer interface, and a sequence controller. The single chip D/sup 2/SP is capable of performing audio signal processing needed for graphic equalizers, surround, and sound power spectrum calculation. The dual processor mainly consists of a 24-bit multiplier with a 108-ns cycle time and is assembled on a single chip fabricated from 1.2- mu m CMOS technology. The total number of integrated transistors is approximately 300 K. Applications, such as use as a seven-band graphic equalizer, seven-band power spectrum calculator, and surround sound processing, are briefly discussed. >

A Custom VLSI Chip Set for Digital Signal Processing in High-Speed Voiceband Modems

Systems modems intended for use in relatively large private networks are characterized by high performance, reliability and flexibility to support network management, and multiple modes of operation and user features. This paper describes a programmable digital signal processor which is teamed with a 16-bit microprocessor in a dual processor architecture satisfying the requirements of high-speed voiceband systems modems. The architecture of the two custom integrated circuits which form the basis of the signal processor is presented. This processor has novel arithmetic, data structure address generation, and program flow-control capabilities, which result in a high utilization of the arithmetic unit and a low program overhead for housekeeping tasks. Some of these features are illustrated by programming examples.